tree 4e77afe1e3b6d3ca0290cf98c4490456787bc895
parent 20df29c46c46756cd54f0fe702b6bf099ceed08e
author Manish V Badarkhe <Manish.Badarkhe@arm.com> 1625671630 +0100
committer Manish V Badarkhe <Manish.Badarkhe@arm.com> 1629966591 +0100

feat(sys_reg_trace): initialize trap settings of trace system registers access

Trap bits of trace system registers access are in architecturally
UNKNOWN state at boot hence

1. Initialized trap bits to one to prohibit trace system registers
   accesses in lower ELs (EL2, EL1) in all security states when system
   trace registers are implemented.
2. These bits are RES0 in the absence of system trace register support
   and hence set it to zero to aligns with the Arm ARM reference
   recommendation,that mentions software must writes RES0 bits with
   all 0s.

Change-Id: I4b6c15cda882325273492895d72568b29de89ca3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>