feat(mt8196): add APU kernel control operations
Add APU kernel control operations to provide the bootup init functions.
1. Add software workaround for certain operations on mt8196.
2. Add APU logger operations.
3. Add function to clear mbox spare register, which is used in APU
booting process.
4. Add function to setup CE binary to make sure the CE binary version
is align with the APU firmware.
Change-Id: Ic99adba1409c020c72179ea135e0d4291fc3f384
diff --git a/plat/mediatek/drivers/apusys/apusys.c b/plat/mediatek/drivers/apusys/apusys.c
index 5eccb3c..87e8960 100644
--- a/plat/mediatek/drivers/apusys/apusys.c
+++ b/plat/mediatek/drivers/apusys/apusys.c
@@ -71,6 +71,24 @@
case MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_APUMMU:
ret = apusys_kernel_apusys_rv_setup_apummu();
break;
+#ifdef CONFIG_MTK_APUSYS_LOGTOP_SUPPORT
+ case MTK_APUSYS_KERNEL_OP_APUSYS_LOGTOP_REG_DUMP:
+ ret = apusys_kernel_apusys_logtop_reg_dump((uint32_t)x2, smccc_ret);
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_LOGTOP_REG_WRITE:
+ ret = apusys_kernel_apusys_logtop_reg_write((uint32_t)x2, (uint32_t)x3,
+ smccc_ret);
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_LOGTOP_REG_W1C:
+ ret = apusys_kernel_apusys_logtop_reg_w1c((uint32_t)x2, smccc_ret);
+ break;
+#endif
+ case MTK_APUSYS_KERNEL_OP_APUSYS_COLD_BOOT_CLR_MBOX_DUMMY:
+ ret = apusys_rv_cold_boot_clr_mbox_dummy();
+ break;
+ case MTK_APUSYS_KERNEL_OP_APUSYS_SETUP_CE_BIN:
+ ret = apusys_rv_setup_ce_bin();
+ break;
default:
ERROR(MODULE_TAG "%s unknown request_ops = %x\n", MODULE_TAG, request_ops);
break;
diff --git a/plat/mediatek/drivers/apusys/apusys.h b/plat/mediatek/drivers/apusys/apusys.h
index 2def47d..709379e 100644
--- a/plat/mediatek/drivers/apusys/apusys.h
+++ b/plat/mediatek/drivers/apusys/apusys.h
@@ -10,20 +10,25 @@
#define MODULE_TAG "[APUSYS]"
enum MTK_APUSYS_KERNEL_OP {
- MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON, /* 0 */
- MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF, /* 1 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER, /* 2 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_RESET_MP, /* 3 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT, /* 4 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP, /* 5 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP, /* 6 */
- MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX, /* 7 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_SEC_MEM, /* 8 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_DISABLE_WDT_ISR, /* 9 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_CLEAR_WDT_ISR, /* 10 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_GATING, /* 11 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_UNGATING, /* 12 */
- MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_APUMMU, /* 13 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_ON, /* 0 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_PWR_TOP_OFF, /* 1 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_REVISER, /* 2 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_RESET_MP, /* 3 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT, /* 4 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP, /* 5 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP, /* 6 */
+ MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX, /* 7 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_SEC_MEM, /* 8 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_DISABLE_WDT_ISR, /* 9 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_CLEAR_WDT_ISR, /* 10 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_GATING, /* 11 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_CG_UNGATING, /* 12 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_APUMMU, /* 13 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_LOGTOP_REG_DUMP, /* 14 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_LOGTOP_REG_WRITE, /* 15 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_LOGTOP_REG_W1C, /* 16 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_COLD_BOOT_CLR_MBOX_DUMMY, /* 17 */
+ MTK_APUSYS_KERNEL_OP_APUSYS_SETUP_CE_BIN, /* 18 */
MTK_APUSYS_KERNEL_OP_NUM,
};
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
index 4dbf950..714ed75 100644
--- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
@@ -4,6 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
+
/* TF-A system header */
#include <common/debug.h>
#include <drivers/delay_timer.h>
@@ -15,7 +17,14 @@
#include "apusys_rv.h"
#include "apusys_rv_mbox_mpu.h"
#include "apusys_rv_pwr_ctrl.h"
+#include "apusys_rv_sec_info.h"
+#ifdef CONFIG_MTK_APUSYS_SEC_CTRL
+#include "apusys_security_ctrl_perm.h"
+#endif
+#include "apusys_security_ctrl_plat.h"
#include "emi_mpu.h"
+#include <mtk_mmap_pool.h>
+#include <mtk_sip_svc.h>
#ifdef CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT
#include "apusys_ammu.h"
@@ -114,13 +123,53 @@
return 0;
}
+static int hw_sema2_release(uint32_t timeout)
+{
+#ifdef CONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT
+ int ret;
+
+ ret = apu_hw_sema_ctl(HW_SEMA2, HW_SEMA_USER, 0, timeout, 0);
+ if (ret) {
+ ERROR("%s: HW semaphore release timeout\n", __func__);
+ }
+
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+static int hw_sema2_acquire(uint32_t timeout)
+{
+#ifdef CONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT
+ int ret;
+
+ ret = apu_hw_sema_ctl(HW_SEMA2, HW_SEMA_USER, 1, timeout, 0);
+ if (ret) {
+ ERROR("%s: HW semaphore acquire timeout\n", __func__);
+ }
+
+ return ret;
+#else
+ return 0;
+#endif
+}
+
int apusys_kernel_apusys_rv_stop_mp(void)
{
+ int ret;
+
+ ret = hw_sema2_acquire(HW_SEM_TIMEOUT);
+ if (ret)
+ return ret;
+
spin_lock(&apusys_rv_lock);
mmio_write_32(MD32_RUNSTALL, MD32_STALL);
spin_unlock(&apusys_rv_lock);
- return 0;
+ ret = hw_sema2_release(HW_SEM_TIMEOUT);
+
+ return ret;
}
int apusys_kernel_apusys_rv_setup_sec_mem(void)
@@ -140,39 +189,71 @@
int apusys_kernel_apusys_rv_disable_wdt_isr(void)
{
+ int ret;
+
+ ret = hw_sema2_acquire(0);
+ if (ret)
+ return ret;
+
spin_lock(&apusys_rv_lock);
mmio_clrbits_32(WDT_CTRL0, WDT_EN);
spin_unlock(&apusys_rv_lock);
- return 0;
+ ret = hw_sema2_release(0);
+
+ return ret;
}
int apusys_kernel_apusys_rv_clear_wdt_isr(void)
{
+ int ret;
+
+ ret = hw_sema2_acquire(HW_SEM_TIMEOUT);
+ if (ret)
+ return ret;
+
spin_lock(&apusys_rv_lock);
mmio_clrbits_32(UP_INT_EN2, DBG_APB_EN);
mmio_write_32(WDT_INT, WDT_INT_W1C);
spin_unlock(&apusys_rv_lock);
- return 0;
+ ret = hw_sema2_release(HW_SEM_TIMEOUT);
+
+ return ret;
}
int apusys_kernel_apusys_rv_cg_gating(void)
{
+ int ret;
+
+ ret = hw_sema2_acquire(HW_SEM_TIMEOUT);
+ if (ret)
+ return ret;
+
spin_lock(&apusys_rv_lock);
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS);
spin_unlock(&apusys_rv_lock);
- return 0;
+ ret = hw_sema2_release(HW_SEM_TIMEOUT);
+
+ return ret;
}
int apusys_kernel_apusys_rv_cg_ungating(void)
{
+ int ret;
+
+ ret = hw_sema2_acquire(HW_SEM_TIMEOUT);
+ if (ret)
+ return ret;
+
spin_lock(&apusys_rv_lock);
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
spin_unlock(&apusys_rv_lock);
- return 0;
+ ret = hw_sema2_release(HW_SEM_TIMEOUT);
+
+ return ret;
}
int apusys_kernel_apusys_rv_setup_apummu(void)
@@ -213,3 +294,195 @@
{
return apusys_rv_pwr_ctrl(op);
}
+
+#ifdef CONFIG_MTK_APUSYS_LOGTOP_SUPPORT
+int apusys_kernel_apusys_logtop_reg_dump(uint32_t op, struct smccc_res *smccc_ret)
+{
+ int ret = 0;
+ uint8_t smc_op;
+ uint32_t reg_addr[MAX_SMC_OP_NUM];
+ uint32_t i;
+
+ if (op == 0) {
+ ERROR("%s empty op = 0x%08x\n", MODULE_TAG, op);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < MAX_SMC_OP_NUM; i++) {
+ smc_op = (op >> (LOGTOP_OP_SHIFT * i)) & LOGTOP_OP_MASK;
+ switch (smc_op) {
+ case SMC_OP_APU_LOG_BUF_NULL:
+ reg_addr[i] = 0x0;
+ break;
+ case SMC_OP_APU_LOG_BUF_T_SIZE:
+ reg_addr[i] = APU_LOG_BUF_T_SIZE;
+ break;
+ case SMC_OP_APU_LOG_BUF_W_PTR:
+ reg_addr[i] = APU_LOG_BUF_W_PTR;
+ break;
+ case SMC_OP_APU_LOG_BUF_R_PTR:
+ reg_addr[i] = APU_LOG_BUF_R_PTR;
+ break;
+ case SMC_OP_APU_LOG_BUF_CON:
+ reg_addr[i] = APU_LOGTOP_CON;
+ break;
+ default:
+ ERROR("%s unknown op = 0x%08x\n", MODULE_TAG, smc_op);
+ return -EINVAL;
+ }
+ }
+
+ ret = apu_hw_sema_ctl(HW_SEMA2, HW_SEMA_LOGGER_USER, 1, 0, 0);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < MAX_SMC_OP_NUM; i++) {
+ if (reg_addr[i] == 0)
+ continue;
+
+ switch (i) {
+ case 0:
+ smccc_ret->a1 = mmio_read_32(reg_addr[i]);
+ break;
+ case 1:
+ smccc_ret->a2 = mmio_read_32(reg_addr[i]);
+ break;
+ case 2:
+ smccc_ret->a3 = mmio_read_32(reg_addr[i]);
+ break;
+ }
+ }
+
+ ret = apu_hw_sema_ctl(HW_SEMA2, HW_SEMA_LOGGER_USER, 0, 0, 0);
+ if (ret)
+ ERROR("%s(%d): sem release timeout\n", __func__, op);
+
+ return ret;
+}
+
+static int apusys_kernel_apusys_logtop_reg_rw(uint32_t op, uint32_t write_val,
+ bool w1c, struct smccc_res *smccc_ret)
+{
+ int ret = 0;
+ uint32_t reg_addr = 0, reg_val = 0;
+
+ switch (op) {
+ case SMC_OP_APU_LOG_BUF_R_PTR:
+ reg_addr = APU_LOG_BUF_R_PTR;
+ break;
+ case SMC_OP_APU_LOG_BUF_CON:
+ reg_addr = APU_LOGTOP_CON;
+ break;
+ default:
+ ERROR("%s unknown or not support op = %x\n", MODULE_TAG, op);
+ return -EINVAL;
+ }
+
+ ret = apu_hw_sema_ctl(HW_SEMA2, HW_SEMA_LOGGER_USER, 1, 0, 0);
+ if (ret)
+ return ret;
+
+ if (w1c) {
+ reg_val = mmio_read_32(reg_addr);
+ mmio_write_32(reg_addr, reg_val);
+ smccc_ret->a1 = reg_val;
+ } else {
+ mmio_write_32(reg_addr, write_val);
+ }
+
+ ret = apu_hw_sema_ctl(HW_SEMA2, HW_SEMA_LOGGER_USER, 0, 0, 0);
+ if (ret)
+ ERROR("%s(%d): sem release timeout\n", __func__, op);
+
+ return ret;
+}
+
+int apusys_kernel_apusys_logtop_reg_write(uint32_t op, uint32_t write_val,
+ struct smccc_res *smccc_ret)
+{
+ return apusys_kernel_apusys_logtop_reg_rw(op, write_val, false, smccc_ret);
+}
+
+int apusys_kernel_apusys_logtop_reg_w1c(uint32_t op, struct smccc_res *smccc_ret)
+{
+ return apusys_kernel_apusys_logtop_reg_rw(op, 0, true, smccc_ret);
+}
+
+#endif /* CONFIG_MTK_APUSYS_LOGTOP_SUPPORT */
+
+int apusys_rv_cold_boot_clr_mbox_dummy(void)
+{
+#ifdef SUPPORT_APU_CLEAR_MBOX_DUMMY
+ mmio_write_32(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_DUMMY, 0);
+#else
+ WARN("Not support clear mbox dummy on this platform\n");
+#endif
+ return 0;
+}
+
+int apusys_rv_setup_ce_bin(void)
+{
+#ifdef CONFIG_MTK_APUSYS_CE_SUPPORT
+ uintptr_t apusys_rv_sec_buf_pa;
+ struct apusys_secure_info_t *apusys_secure_info;
+ struct ce_main_hdr_t *ce_main_hdr;
+ struct ce_sub_hdr_t *ce_sub_hdr;
+ unsigned int cnt, i, reg_val;
+ uint64_t ce_sub_hdr_bin;
+ int ret;
+
+ apusys_rv_sec_buf_pa = APU_RESERVE_MEMORY;
+ /* create mapping */
+ ret = mmap_add_dynamic_region(apusys_rv_sec_buf_pa, apusys_rv_sec_buf_pa,
+ round_up(APU_RESERVE_SIZE, PAGE_SIZE),
+ MT_MEMORY | MT_RW | MT_NS);
+ if (ret) {
+ ERROR("%s: mmap_add_dynamic_region() fail, ret=0x%x\n", __func__, ret);
+ return ret;
+ }
+
+ apusys_secure_info = (struct apusys_secure_info_t *)
+ (apusys_rv_sec_buf_pa + APU_SEC_INFO_OFFSET);
+
+ ce_main_hdr = (struct ce_main_hdr_t *)(apusys_rv_sec_buf_pa +
+ apusys_secure_info->ce_bin_ofs);
+ ce_sub_hdr = (struct ce_sub_hdr_t *)((uintptr_t)ce_main_hdr + ce_main_hdr->hdr_size);
+
+ if (ce_main_hdr->magic != CE_MAIN_MAGIC) {
+ ERROR("%s: invalid header\n", __func__);
+ return -EINVAL;
+ }
+
+ cnt = 0;
+
+ while (ce_sub_hdr->magic == CE_SUB_MAGIC && cnt < ce_main_hdr->bin_count) {
+ VERBOSE("%s: job (%d), magic (0x%x)\n", __func__,
+ ce_sub_hdr->ce_enum, ce_sub_hdr->magic);
+
+ ce_sub_hdr_bin = (uint64_t)ce_sub_hdr + ce_sub_hdr->bin_offset;
+
+ for (i = 0; i < ce_sub_hdr->bin_size; i += sizeof(uint32_t)) {
+ reg_val = *(uint32_t *)(ce_sub_hdr_bin + i);
+ mmio_write_32(ce_sub_hdr->mem_st + i, reg_val);
+ }
+
+ if (ce_sub_hdr->hw_entry) {
+ mmio_clrsetbits_32(ce_sub_hdr->hw_entry,
+ ce_sub_hdr->hw_entry_mask << ce_sub_hdr->hw_entry_bit,
+ (ce_sub_hdr->hw_entry_val & ce_sub_hdr->hw_entry_mask)
+ << ce_sub_hdr->hw_entry_bit);
+ }
+
+ ce_sub_hdr = (struct ce_sub_hdr_t *)(ce_sub_hdr_bin + ce_sub_hdr->bin_size);
+ cnt++;
+ }
+
+ mmap_remove_dynamic_region(apusys_rv_sec_buf_pa,
+ round_up(APU_RESERVE_SIZE, PAGE_SIZE));
+
+ INFO("%s: setup CE binary done\n", __func__);
+#else
+ WARN("Not support CE on this platform\n");
+#endif
+ return 0;
+}
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
index 3700783..506fcee 100644
--- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h
@@ -93,6 +93,28 @@
APU_PWR_ON = 1,
};
+/* APU_LOGTOP */
+#define APU_LOGTOP_CON (APU_LOGTOP + 0x0)
+#define APU_LOG_BUF_T_SIZE (APU_LOGTOP + 0x78)
+#define APU_LOG_BUF_W_PTR (APU_LOGTOP + 0x80)
+#define APU_LOG_BUF_R_PTR (APU_LOGTOP + 0x84)
+#define HW_SEMA2 (APU_ARE_REG_BASE + 0x0E08)
+#define HW_SEMA_USER (0x2)
+#define HW_SEMA_LOGGER_USER (0x3)
+#define MAX_SMC_OP_NUM (0x3)
+#define LOGTOP_OP_MASK (0xFF)
+#define LOGTOP_OP_SHIFT (8)
+enum {
+ SMC_OP_APU_LOG_BUF_NULL = 0,
+ SMC_OP_APU_LOG_BUF_T_SIZE,
+ SMC_OP_APU_LOG_BUF_W_PTR,
+ SMC_OP_APU_LOG_BUF_R_PTR,
+ SMC_OP_APU_LOG_BUF_CON,
+ SMC_OP_APU_LOG_BUF_NUM
+};
+
+struct smccc_res;
+
void apusys_rv_mbox_mpu_init(void);
int apusys_infra_dcm_setup(void);
int apusys_kernel_apusys_rv_setup_reviser(void);
@@ -107,5 +129,11 @@
int apusys_kernel_apusys_rv_cg_ungating(void);
int apusys_kernel_apusys_rv_setup_apummu(void);
int apusys_kernel_apusys_rv_pwr_ctrl(enum APU_PWR_OP op);
+int apusys_kernel_apusys_logtop_reg_dump(uint32_t op, struct smccc_res *smccc_ret);
+int apusys_kernel_apusys_logtop_reg_write(uint32_t op, uint32_t write_val,
+ struct smccc_res *smccc_ret);
+int apusys_kernel_apusys_logtop_reg_w1c(uint32_t op, struct smccc_res *smccc_ret);
+int apusys_rv_cold_boot_clr_mbox_dummy(void);
+int apusys_rv_setup_ce_bin(void);
#endif /* APUSYS_RV_H */
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv_sec_info.h b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv_sec_info.h
new file mode 100644
index 0000000..581ed0a
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv_sec_info.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2024, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_RV_SECURE_INFO_H
+#define APUSYS_RV_SECURE_INFO_H
+
+#define CE_MAIN_MAGIC (0xCEC0DE88)
+#define CE_SUB_MAGIC (0xCEC0DE00)
+
+struct apusys_secure_info_t {
+ unsigned int total_sz;
+ unsigned int up_code_buf_ofs;
+ unsigned int up_code_buf_sz;
+
+ unsigned int up_fw_ofs;
+ unsigned int up_fw_sz;
+ unsigned int up_xfile_ofs;
+ unsigned int up_xfile_sz;
+ unsigned int mdla_fw_boot_ofs;
+ unsigned int mdla_fw_boot_sz;
+ unsigned int mdla_fw_main_ofs;
+ unsigned int mdla_fw_main_sz;
+ unsigned int mdla_xfile_ofs;
+ unsigned int mdla_xfile_sz;
+ unsigned int mvpu_fw_ofs;
+ unsigned int mvpu_fw_sz;
+ unsigned int mvpu_xfile_ofs;
+ unsigned int mvpu_xfile_sz;
+ unsigned int mvpu_sec_fw_ofs;
+ unsigned int mvpu_sec_fw_sz;
+ unsigned int mvpu_sec_xfile_ofs;
+ unsigned int mvpu_sec_xfile_sz;
+
+ unsigned int up_coredump_ofs;
+ unsigned int up_coredump_sz;
+ unsigned int mdla_coredump_ofs;
+ unsigned int mdla_coredump_sz;
+ unsigned int mvpu_coredump_ofs;
+ unsigned int mvpu_coredump_sz;
+ unsigned int mvpu_sec_coredump_ofs;
+ unsigned int mvpu_sec_coredump_sz;
+
+ unsigned int ce_bin_ofs;
+ unsigned int ce_bin_sz;
+};
+
+struct ce_main_hdr_t {
+ unsigned int magic; /* magic number*/
+ unsigned int hdr_size; /* header size */
+ unsigned int img_size; /* img size */
+ unsigned int bin_count; /* bin count */
+};
+
+struct ce_sub_hdr_t {
+ unsigned int magic; /* magic number */
+ unsigned int bin_offset; /* binary offset */
+ unsigned int bin_size; /* binary size */
+ unsigned int ce_enum; /* ce enum */
+ char job_name[8]; /* job name */
+ unsigned int mem_st; /* ce enum */
+ unsigned int hw_entry; /* hw entry */
+ unsigned int hw_entry_bit; /* hw entry bit */
+ unsigned int hw_entry_mask; /* hw entry mask */
+ unsigned int hw_entry_val; /* hw entry val*/
+ unsigned int user_info; /* user_info */
+};
+
+#endif /* APUSYS_RV_SECURE_INFO_H */
diff --git a/plat/mediatek/drivers/apusys/rules.mk b/plat/mediatek/drivers/apusys/rules.mk
index 6197995..6b9e67d 100644
--- a/plat/mediatek/drivers/apusys/rules.mk
+++ b/plat/mediatek/drivers/apusys/rules.mk
@@ -12,8 +12,11 @@
PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC} -I${LOCAL_DIR}/apusys_rv/2.0
+$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_CE_SUPPORT))
$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_EMI_SUPPORT))
+$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_LOGTOP_SUPPORT))
$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT))
+$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT))
$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_SEC_CTRL))
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))