plat/arm/sgi: add support for SGI-Clark.Ares platform
SGI-Clark.Ares platform is a variant of the SGI-Clark platform. It has
two clusters of four Ares CPUs each. Though very similar to the SGI575
platform, there are subtle differences. HW_CONFIG and TB_FW_CONFIG dts
files have been added.
Change-Id: I740a33cbd1c3b1f1984cb56243b46ad379bab3e6
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
diff --git a/plat/arm/board/sgiclarka/fdts/sgiclarka.dts b/plat/arm/board/sgiclarka/fdts/sgiclarka.dts
new file mode 100644
index 0000000..43bd856
--- /dev/null
+++ b/plat/arm/board/sgiclarka/fdts/sgiclarka.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+/ {
+ /* compatible string */
+ compatible = "arm,sgi-clark";
+
+ /*
+ * Place holder for system-id node with default values. The
+ * value of platform-id and config-id will be set to the
+ * correct values during the BL2 stage of boot.
+ */
+ system-id {
+ platform-id = <0x0>;
+ config-id = <0x0>;
+ };
+};
diff --git a/plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts b/plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts
new file mode 100644
index 0000000..315fa69
--- /dev/null
+++ b/plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+ /* Platform Config */
+ compatible = "arm,tb_fw";
+ hw_config_addr = <0x0 0xFEF00000>;
+ hw_config_max_size = <0x0100000>;
+ /*
+ * The following two entries are placeholders for Mbed TLS
+ * heap information. The default values don't matter since
+ * they will be overwritten by BL1.
+ * In case of having shared Mbed TLS heap between BL1 and BL2,
+ * BL1 will populate these two properties with the respective
+ * info about the shared heap. This info will be available for
+ * BL2 in order to locate and re-use the heap.
+ */
+ mbedtls_heap_addr = <0x0 0x0>;
+ mbedtls_heap_size = <0x0>;
+};
diff --git a/plat/arm/board/sgiclarka/include/platform_def.h b/plat/arm/board/sgiclarka/include/platform_def.h
new file mode 100644
index 0000000..abc48d8
--- /dev/null
+++ b/plat/arm/board/sgiclarka/include/platform_def.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <sgi_base_platform_def.h>
+
+#define PLAT_ARM_CLUSTER_COUNT 2
+#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
+#define CSS_SGI_MAX_PE_PER_CPU 1
+
+#define PLAT_CSS_MHU_BASE 0x45400000
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/sgiclarka/platform.mk b/plat/arm/board/sgiclarka/platform.mk
new file mode 100644
index 0000000..fc2f766
--- /dev/null
+++ b/plat/arm/board/sgiclarka/platform.mk
@@ -0,0 +1,38 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/css/sgi/sgi-common.mk
+
+SGICLARKA_BASE = plat/arm/board/sgiclarka
+
+PLAT_INCLUDES += -I${SGICLARKA_BASE}/include/
+
+SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_ares.S
+
+BL1_SOURCES += ${SGI_CPU_SOURCES}
+
+BL2_SOURCES += lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES += ${SGI_CPU_SOURCES} \
+ drivers/cfi/v2m/v2m_flash.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += ${SGICLARKA_BASE}/fdts/${PLAT}_tb_fw_config.dts
+TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
+
+FDT_SOURCES += ${SGICLARKA_BASE}/fdts/${PLAT}.dts
+HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
+
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config))
+
+override CTX_INCLUDE_AARCH32_REGS := 0