| commit | ee51c33714fd7b6c2934286b80bda2198f935960 | [log] [tgz] |
|---|---|---|
| author | Anson Huang <Anson.Huang@nxp.com> | Tue Jan 15 10:22:06 2019 +0800 |
| committer | Anson Huang <Anson.Huang@nxp.com> | Thu Jan 17 10:49:48 2019 +0800 |
| tree | f8236136c6318c665e63b82fac9c685143ff1c07 | |
| parent | bb87f85e671c03399201a066bbe7be6caa4cf371 [diff] |
Support for NXP's i.MX8 SoCs timer IPC NXP's i.MX8 SoCs have system controller (M4 core) which takes control of timer management, including watchdog, srtc and system counter etc., other clusters like Cortex-A35 can send out command via MU (Message Unit) to system controller for timer operation. This patch adds timer IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>