diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
index b6c543a..2f459b0 100644
--- a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
+++ b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
@@ -20,30 +20,27 @@
 		binary_size = <0x80000>;
 	};
 
-	chosen {
-		linux,initrd-start = <0>;
-		linux,initrd-end = <0>;
-	};
-
 	hypervisor {
 		compatible = "hafnium,hafnium";
 		vm1 {
 			is_ffa_partition;
 			debug_name = "cactus-primary";
 			load_address = <0xfe000000>;
+			vcpu_count = <8>;
+			mem_size = <1048576>;
 		};
 		vm2 {
 			is_ffa_partition;
 			debug_name = "cactus-secondary";
 			load_address = <0xfe100000>;
-			vcpu_count = <4>;
+			vcpu_count = <8>;
 			mem_size = <1048576>;
 		};
 		vm3 {
 			is_ffa_partition;
 			debug_name = "cactus-tertiary";
 			load_address = <0xfe200000>;
-			vcpu_count = <4>;
+			vcpu_count = <8>;
 			mem_size = <1048576>;
 		};
 	};
@@ -60,9 +57,37 @@
 		};
 
 		/*
-		 * SPM(Hafnium) requires secondary cpu nodes are declared in
+		 * SPMC (Hafnium) requires secondary cpu nodes are declared in
 		 * descending order
 		 */
+		CPU7:cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+		};
+
+		CPU6:cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+		};
+
+		CPU5:cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+		};
+
+		CPU4:cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+		};
+
 		CPU3:cpu@300 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
index a58b911..221039c 100644
--- a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
@@ -5,13 +5,6 @@
  */
 /dts-v1/;
 
-#define	AFF	00
-
-#include "fvp-defs.dtsi"
-#undef POST
-#define	POST \
-	};
-
 / {
 	compatible = "arm,ffa-core-manifest-1.0";
 	#address-cells = <2>;
@@ -27,21 +20,14 @@
 		binary_size = <0x80000>;
 	};
 
-	/*
-	 * temporary: This entry is added based on v2.4 hafnium and will be
-	 * removed when rebased to upstream master.
-	 */
-	chosen {
-	       linux,initrd-start = <0>;
-	       linux,initrd-end = <0>;
-	};
-
 	hypervisor {
 		compatible = "hafnium,hafnium";
 		vm1 {
 			is_ffa_partition;
 			debug_name = "op-tee";
 			load_address = <0xfd280000>;
+			vcpu_count = <8>;
+			mem_size = <30928896>; /* 32MB TZC DRAM - SPMC region */
 		};
 	};
 
@@ -49,25 +35,65 @@
 		#address-cells = <0x2>;
 		#size-cells = <0x0>;
 
-		CPU_0
+		CPU0:cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
 
 		/*
-		 * SPMC (Hafnium) requires secondary core nodes are declared
-		 * in descending order.
+		 * SPMC (Hafnium) requires secondary cpu nodes are declared in
+		 * descending order
 		 */
-		CPU_3
-		CPU_2
-		CPU_1
-	};
+		CPU7:cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+		};
 
-	/*
-	 * temporary: This device-memory region is added based on v2.4 hafnium
-	 * and will be removed when rebased to upstream master. As first
-	 * Secure Partition no longer maps device memory.
-	 */
-	device-memory@21000000 {
-		device_type = "device-memory";
-		reg = <0x0 0x21000000 0x5f000000>;
+		CPU6:cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+		};
+
+		CPU5:cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+		};
+
+		CPU4:cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+		};
+
+		CPU3:cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+		};
+
+		CPU2:cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+		};
+
+		CPU1:cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+		};
 	};
 
 	/* 32MB of TC0_TZC_DRAM1_BASE */
diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h
index 2ff2699..30b5ab7 100644
--- a/plat/arm/board/tc0/include/platform_def.h
+++ b/plat/arm/board/tc0/include/platform_def.h
@@ -17,7 +17,7 @@
 #include <plat/arm/soc/common/soc_css_def.h>
 #include <plat/common/common_def.h>
 
-#define PLATFORM_CORE_COUNT		4
+#define PLATFORM_CORE_COUNT		8
 
 #define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00080000	/* 512 KB */
 
@@ -202,7 +202,7 @@
 #define PLAT_ARM_SCMI_CHANNEL_COUNT	1
 
 #define PLAT_ARM_CLUSTER_COUNT		U(1)
-#define PLAT_MAX_CPUS_PER_CLUSTER	U(4)
+#define PLAT_MAX_CPUS_PER_CLUSTER	U(8)
 #define PLAT_MAX_PE_PER_CPU		U(1)
 
 #define PLAT_CSS_MHU_BASE		UL(0x45400000)
diff --git a/plat/arm/board/tc0/platform.mk b/plat/arm/board/tc0/platform.mk
index 6cc5f46..393d09c 100644
--- a/plat/arm/board/tc0/platform.mk
+++ b/plat/arm/board/tc0/platform.mk
@@ -43,7 +43,8 @@
 
 PLAT_INCLUDES		+=	-I${TC0_BASE}/include/
 
-TC0_CPU_SOURCES	:=	lib/cpus/aarch64/cortex_matterhorn.S
+TC0_CPU_SOURCES	:=	lib/cpus/aarch64/cortex_klein.S         \
+			lib/cpus/aarch64/cortex_matterhorn.S
 
 INTERCONNECT_SOURCES	:=	${TC0_BASE}/tc0_interconnect.c
 
diff --git a/plat/arm/board/tc0/tc0_topology.c b/plat/arm/board/tc0/tc0_topology.c
index 5478fbc..8cfc3b5 100644
--- a/plat/arm/board/tc0/tc0_topology.c
+++ b/plat/arm/board/tc0/tc0_topology.c
@@ -33,6 +33,9 @@
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
 	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
+	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
+	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
+	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
 };
 
 /*******************************************************************************