| commit | f6186b26b586b09a0fc0f509ca2b109e351309ed | [log] [tgz] |
|---|---|---|
| author | Jit Loon Lim <jit.loon.lim@intel.com> | Wed Sep 27 11:02:45 2023 +0800 |
| committer | Jit Loon Lim <jit.loon.lim@intel.com> | Fri Nov 03 23:39:48 2023 +0800 |
| tree | 465e1b3396b846ca88fcee59bea3a69089b61391 | |
| parent | 1165717bcba28cb0ad85c95bbd03c96771620af1 [diff] |
feat(intel): increase bl2 size limit There are several features included in BL2 causing the size getting bigger for RELEASE mode. When build with DEBUG mode, the size will be bigger thus causing BL2 image has exceeded its limits. Change-Id: I7542f5ea001542450695d48e8126bcca8728d76a Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index a744d09..a01192d 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -65,7 +65,7 @@ #define DEVICE4_SIZE (0x0100000000) #define BL2_BASE (0xffe00000) -#define BL2_LIMIT (0xffe1b000) +#define BL2_LIMIT (0xffe2b000) #define BL31_BASE (0x1000) #define BL31_LIMIT (0x81000)
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h index 8a49d61..ff2b10a 100644 --- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -83,7 +83,7 @@ #define GIC_SIZE (0x00100000) #define BL2_BASE (0x00000000) -#define BL2_LIMIT (0x0001b000) +#define BL2_LIMIT (0x0002b000) #define BL31_BASE (0x80000000) #define BL31_LIMIT (0x82000000)
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h index 7c9f15a..03da8d9 100644 --- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -64,7 +64,7 @@ #define DEVICE4_SIZE (0x0100000000) #define BL2_BASE (0xffe00000) -#define BL2_LIMIT (0xffe1b000) +#define BL2_LIMIT (0xffe2b000) #define BL31_BASE (0x1000) #define BL31_LIMIT (0x81000)