diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index 8b12dcd..559ea2c 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -393,43 +393,6 @@
 #define MC_CLIENT_HOTRESET_STATUS1			0x974
 
 /*******************************************************************************
- * TSA configuration registers
- ******************************************************************************/
-#define TSA_CONFIG_STATIC0_CSW_SESWR			0x4010
-#define  TSA_CONFIG_STATIC0_CSW_SESWR_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_ETRW			0x4038
-#define  TSA_CONFIG_STATIC0_CSW_ETRW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB			0x5010
-#define  TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_AXISW			0x7008
-#define  TSA_CONFIG_STATIC0_CSW_AXISW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_HDAW			0xA008
-#define  TSA_CONFIG_STATIC0_CSW_HDAW_RESET		0x100
-#define TSA_CONFIG_STATIC0_CSW_AONDMAW			0xB018
-#define  TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_SCEDMAW			0xD018
-#define  TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW			0xD028
-#define  TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_APEDMAW			0x12018
-#define  TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_UFSHCW			0x13008
-#define  TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_AFIW			0x13018
-#define  TSA_CONFIG_STATIC0_CSW_AFIW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_SATAW			0x13028
-#define  TSA_CONFIG_STATIC0_CSW_SATAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_EQOSW			0x13038
-#define  TSA_CONFIG_STATIC0_CSW_EQOSW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW		0x15008
-#define  TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW		0x15018
-#define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET	0x1100
-
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK		(0x3 << 11)
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU		(0 << 11)
-
-/*******************************************************************************
  * Memory Controller's PCFIFO client configuration registers
  ******************************************************************************/
 #define MC_PCFIFO_CLIENT_CONFIG1			0xdd4
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 01da884..6bac0d7 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -115,6 +115,43 @@
 #define TEGRA_TSA_BASE			0x02400000
 
 /*******************************************************************************
+ * TSA configuration registers
+ ******************************************************************************/
+#define TSA_CONFIG_STATIC0_CSW_SESWR			0x4010
+#define  TSA_CONFIG_STATIC0_CSW_SESWR_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_ETRW			0x4038
+#define  TSA_CONFIG_STATIC0_CSW_ETRW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB			0x5010
+#define  TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_AXISW			0x7008
+#define  TSA_CONFIG_STATIC0_CSW_AXISW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_HDAW			0xA008
+#define  TSA_CONFIG_STATIC0_CSW_HDAW_RESET		0x100
+#define TSA_CONFIG_STATIC0_CSW_AONDMAW			0xB018
+#define  TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_SCEDMAW			0xD018
+#define  TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW			0xD028
+#define  TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_APEDMAW			0x12018
+#define  TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_UFSHCW			0x13008
+#define  TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_AFIW			0x13018
+#define  TSA_CONFIG_STATIC0_CSW_AFIW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_SATAW			0x13028
+#define  TSA_CONFIG_STATIC0_CSW_SATAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_EQOSW			0x13038
+#define  TSA_CONFIG_STATIC0_CSW_EQOSW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW		0x15008
+#define  TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW		0x15018
+#define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET	0x1100
+
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK		(0x3 << 11)
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU		(0 << 11)
+
+/*******************************************************************************
  * Tegra Memory Controller constants
  ******************************************************************************/
 #define TEGRA_MC_STREAMID_BASE		0x02C00000