Merge "refactor(stm32mp1): use a macro for header size" into integration
diff --git a/.commitlintrc.js b/.commitlintrc.js
index f970481..ed971a3 100644
--- a/.commitlintrc.js
+++ b/.commitlintrc.js
@@ -8,26 +8,44 @@
"use strict";
-const cz = require("./.cz.json");
+const fs = require("fs");
+const yaml = require("js-yaml");
+
const { "trailer-exists": trailerExists } = require("@commitlint/rules").default;
/*
- * Recursively fetch the project's supported scopes from the Commitizen configuration file. We use
- * permit only the blessed scope for each section to encourage developers to use a consistent scope
- * scheme.
+ * The types and scopes accepted by both Commitlint and Commitizen are defined by the changelog
+ * configuration file - `changelog.yaml` - as they decide which section of the changelog commits
+ * with a given type and scope are placed in.
*/
-function getScopes(sections) {
- return sections.flatMap(section => {
- const scopes = section.scopes;
- const subscopes = getScopes(section.sections || []);
+
+let changelog;
- const scope = scopes ? [ scopes[0] ] : []; /* Only use the blessed scope */
+try {
+ const contents = fs.readFileSync("changelog.yaml", "utf8");
+
+ changelog = yaml.load(contents);
+} catch (err) {
+ console.log(err);
+
+ throw err;
+}
+
+function getTypes(sections) {
+ return sections.map(section => section.type)
+}
+
+function getScopes(subsections) {
+ return subsections.flatMap(subsection => {
+ const scope = subsection.scope ? [ subsection.scope ] : [];
+ const subscopes = getScopes(subsection.subsections || []);
return scope.concat(subscopes);
})
};
-const scopes = getScopes(cz.sections); /* Contains every blessed scope */
+const types = getTypes(changelog.sections).sort(); /* Sort alphabetically */
+const scopes = getScopes(changelog.subsections).sort(); /* Sort alphabetically */
module.exports = {
extends: ["@commitlint/config-conventional"],
@@ -40,13 +58,17 @@
},
],
rules: {
- "body-max-line-length": [1, "always", cz.maxLineWidth], /* Warning */
- "header-max-length": [1, "always", cz.maxHeaderWidth], /* Warning */
+ "header-max-length": [1, "always", 50], /* Warning */
+ "body-max-line-length": [1, "always", 72], /* Warning */
"change-id-exists": [1, "always", "Change-Id:"], /* Warning */
"signed-off-by-exists": [1, "always", "Signed-off-by:"], /* Warning */
+ "type-case": [2, "always", "lower-case" ], /* Error */
+ "type-enum": [2, "always", types], /* Error */
+
"scope-case": [2, "always", "lower-case"], /* Error */
+ "scope-empty": [2, "never"], /* Error */
"scope-enum": [1, "always", scopes] /* Warning */
},
};
diff --git a/.cz.json b/.cz.json
index 3c28d3c..556c39f 100644
--- a/.cz.json
+++ b/.cz.json
@@ -1,838 +1,3 @@
{
- "path": "./node_modules/cz-conventional-changelog",
- "maxHeaderWidth": 50,
- "maxLineWidth": 72,
- "types": [
- {
- "type": "feat",
- "title": "New Features",
- "description": "A new feature"
- },
- {
- "type": "fix",
- "title": "Resolved Issues",
- "description": "A bug fix"
- },
- {
- "type": "build",
- "title": "Build System",
- "description": "Changes that affect the build system or external dependencies",
- "hidden": true
- },
- {
- "type": "ci",
- "title": "Continuous Integration",
- "description": "Changes to our CI configuration files and scripts",
- "hidden": true
- },
- {
- "type": "docs",
- "title": "Build System",
- "description": "Documentation-only changes",
- "hidden": true
- },
- {
- "type": "perf",
- "title": "Performance Improvements",
- "description": "A code change that improves performance",
- "hidden": true
- },
- {
- "type": "refactor",
- "title": "Code Refactoring",
- "description": "A code change that neither fixes a bug nor adds a feature",
- "hidden": true
- },
- {
- "type": "revert",
- "title": "Reverted Changes",
- "description": "Changes that revert a previous change",
- "hidden": true
- },
- {
- "type": "style",
- "title": "Style",
- "description": "Changes that do not affect the meaning of the code (white-space, formatting, missing semi-colons, etc.)",
- "hidden": true
- },
- {
- "type": "test",
- "title": "Tests",
- "description": "Adding missing tests or correcting existing tests",
- "hidden": true
- },
- {
- "type": "chore",
- "title": "Miscellaneous",
- "description": "Any other change",
- "hidden": true
- }
- ],
- "sections": [
- {
- "title": "Architecture",
- "sections": [
- {
- "title": "Activity Monitors Extension (FEAT_AMU)",
- "scopes": ["amu"]
- },
- {
- "title": "Support for the `HCRX_EL2` register (FEAT_HCX)",
- "scopes": ["hcx"]
- },
- {
- "title": "Memory Partitioning and Monitoring (MPAM) Extension (FEAT_MPAM)",
- "scopes": ["mpam"]
- },
- {
- "title": "Scalable Matrix Extension (FEAT_SME)",
- "scopes": ["sme"]
- },
- {
- "title": "Scalable Vector Extension (FEAT_SVE)",
- "scopes": ["sve"]
- },
- {
- "title": "System Register Trace Extensions (FEAT_ETMv4, FEAT_ETE and FEAT_ETEv1.1)",
- "scopes": ["sys-reg-trace", "sys_reg_trace"]
- },
- {
- "title": "Trace Buffer Extension (FEAT_TRBE)",
- "scopes": ["trbe"]
- },
- {
- "title": "Self-hosted Trace Extension (FEAT_TRF)",
- "scopes": ["trf"]
- }
- ]
- },
- {
- "title": "Platforms",
- "sections": [
- {
- "title": "Allwinner",
- "scopes": ["allwinner", "plat/allwinner"]
- },
- {
- "title": "Arm",
- "scopes": ["arm", "plat/arm"],
- "sections": [
- {
- "title": "FPGA",
- "scopes": ["fpga", "arm_fgpa", "arm_fpga", "plat/arm_fpga"]
- },
- {
- "title": "FVP",
- "scopes": ["fvp", "plat/fvp"]
- },
- {
- "title": "FVP-R",
- "scopes": ["fvp-r", "fvp_r"]
- },
- {
- "title": "Juno",
- "scopes": ["juno"]
- },
- {
- "title": "Morello",
- "scopes": ["morello"]
- },
- {
- "title": "RD",
- "scopes": ["rd"],
- "sections": [
- {
- "title": "RD-N2",
- "scopes": ["rdn2", "board/rdn2"]
- }
- ]
- },
- {
- "title": "SGI",
- "scopes": ["sgi", "plat/sgi", "plat/arm/sgi" ]
- },
- {
- "title": "TC",
- "scopes": ["tc"],
- "sections": [
- {
- "title": "TC0",
- "scopes": ["tc0", "plat/tc0"]
- }
- ]
- }
- ]
- },
- {
- "title": "Marvell",
- "scopes": ["marvell", "plat/marvell"],
- "sections": [
- {
- "title": "Armada",
- "scopes": ["armada", "plat/marvell/armada"],
- "sections": [
- {
- "title": "A3K",
- "scopes": ["a3k", "plat/marvell/a3k"]
- },
- {
- "title": "A8K",
- "scopes": ["a8k", "plat/marvell/a8k"]
- }
- ]
- }
- ]
- },
- {
- "title": "MediaTek",
- "scopes": ["mediatek", "plat/mediatek/common", "plat/mediatek"],
- "sections": [
- {
- "title": "MT8183",
- "scopes": ["mt8183", "plat/mediatek/mt8183"]
- },
- {
- "title": "MT8192",
- "scopes": ["mt8192", "plat/mdeiatek/mt8192"]
- },
- {
- "title": "MT8195",
- "scopes": ["mt8195", "plat/mediatek/me8195", "plat/mediatek/mt8195", "plat/mdeiatek/mt8195"]
- },
- {
- "title": "MT8186",
- "scopes": ["mt8186", "plat/mediatek/mt8186"]
- }
- ]
- },
- {
- "title": "NVIDIA",
- "scopes": ["nvidia"],
- "sections": [
- {
- "title": "Tegra",
- "scopes": ["tegra", "plat/tegra"],
- "sections": [
- {
- "title": "Tegra 132",
- "scopes": ["tegra132"]
- }
- ]
- }
- ]
- },
- {
- "title": "NXP",
- "scopes": ["nxp", "plat/nxp", "plat/nxp/common"],
- "sections": [
- {
- "title": "i.MX",
- "scopes": ["imx", "plat/imx", "plat/imx/imx"],
- "sections": [
- {
- "title": "i.MX 8M",
- "scopes": ["imx8m", "plat/imx8m", "plat/imx/imx8m"],
- "sections": [
- {
- "title": "i.MX 8M Mini",
- "scopes": ["imx8mm", "plat/imx/imx8m/imx8mm"]
- },
- {
- "title": "i.MX 8M Plus",
- "scopes": ["imx8mp", "plat/imx/imx8m/imx8mp"]
- }
- ]
- }
- ]
- },
- {
- "title": "Layerscape",
- "scopes": ["layerscape", "docs/nxp/layerscape"],
- "sections": [
- {
- "title": "LX2",
- "scopes": ["lx2", "plat/nxp/lx2"],
- "sections": [
- {
- "title": "LX216",
- "scopes": ["lx216", "plat/nxp/lx216x"],
- "sections": [
- {
- "title": "LX2160",
- "scopes": ["lx2160", "plat/soc-lx2160"]
- }
- ]
- },
- {
- "title": "LS1028A",
- "scopes": ["ls1028a", "plat/nxp/ls1028a"],
- "sections": [
- {
- "title": "LS1028ARDB",
- "scopes": ["ls1028ardb", "plat/nxp/ls1028ardb"]
- }
- ]
- }
- ]
- }
- ]
- }
- ]
- },
- {
- "title": "QEMU",
- "scopes": ["qemu", "plat/qemu"]
- },
- {
- "title": "QTI",
- "scopes": ["qti"],
- "sections": [
- {
- "title": "SC1780",
- "scopes": ["sc7180", "plat/qti/sc7180"]
- },
- {
- "title": "SC7280",
- "scopes": ["sc7280", "plat/qti/sc7280"]
- }
- ]
- },
- {
- "title": "Raspberry Pi",
- "scopes": ["rpi"],
- "sections": [
- {
- "title": "Raspberry Pi 4",
- "scopes": ["rpi4"]
- }
- ]
- },
- {
- "title": "Renesas",
- "scopes": ["renesas"],
- "sections": [
- {
- "title": "R-Car",
- "scopes": ["rcar", "plat/rcar"],
- "sections": [
- {
- "title": "R-Car 3",
- "scopes": ["rcar3", "plat/rcar3"]
- }
- ]
- }
- ]
- },
- {
- "title": "Rockchip",
- "scopes": ["rockchip"],
- "sections": [
- {
- "title": "RK3399",
- "scopes": ["rk3399", "rockchip/rk3399", "rk3399/suspend"]
- }
- ]
- },
- {
- "title": "Socionext",
- "scopes": ["socionext"],
- "sections": [
- {
- "title": "Synquacer",
- "scopes": ["synquacer", "plat/synquacer"]
- }
- ]
- },
- {
- "title": "ST",
- "scopes": ["st", "plat/st"],
- "sections": [
- {
- "title": "ST32MP1",
- "scopes": ["stm32mp1", "plat/st/stm32mp1"]
- }
- ]
- },
- {
- "title": "Xilinx",
- "scopes": ["xilinx", "plat/xilinx"],
- "sections": [
- {
- "title": "Versal",
- "scopes": ["versal", "plat/xilinx/versal/include", "plat/xilinx/versal", "plat/versal"]
- },
- {
- "title": "ZynqMP",
- "scopes": ["zynqmp", "plat/zynqmp", "plat/xilinx/zynqmp"]
- }
- ]
- }
- ]
- },
- {
- "title": "Bootloader Images",
- "scopes": ["bl", "bl_common"],
- "sections": [
- {
- "title": "BL1",
- "scopes": ["bl1"]
- },
- {
- "title": "BL2",
- "scopes": ["bl2"]
- }
- ]
- },
- {
- "title": "Services",
- "scopes": ["services"],
- "sections": [
- {
- "title": "FF-A",
- "scopes": ["ffa", "ff-a"]
- },
- {
- "title": "RME",
- "scopes": ["rme"]
- },
- {
- "title": "SPM",
- "scopes": ["spm", "spmc", "spmd", "SPMD", "spm_mm"]
- }
- ]
- },
- {
- "title": "Libraries",
- "sections": [
- {
- "title": "CPU Support",
- "scopes": ["cpus", "cpu", "errata", "errata_report"]
- },
- {
- "title": "EL3 Runtime",
- "scopes": ["el3-runtime", "el3_runtime"]
- },
- {
- "title": "FCONF",
- "scopes": ["fconf"]
- },
- {
- "title": "MPMM",
- "scopes": ["mpmm"]
- },
- {
- "title": "OP-TEE",
- "scopes": ["optee", "lib/optee"]
- },
- {
- "title": "PSCI",
- "scopes": ["psci"]
- },
- {
- "title": "GPT",
- "scopes": ["gpt", "gpt_rme"]
- },
- {
- "title": "SMCCC",
- "scopes": ["smccc"]
- },
- {
- "title": "Translation Tables",
- "scopes": ["xlat"]
- }
- ]
- },
- {
- "title": "Drivers",
- "sections": [
- {
- "title": "Authentication",
- "scopes": ["auth", "driver/auth"],
- "sections": [
- {
- "title": "CryptoCell-713",
- "scopes": ["cc-713"]
- }
- ]
- },
- {
- "title": "FWU",
- "scopes": ["fwu", "fwu_metadata"]
- },
- {
- "title": "I/O",
- "scopes": ["io"],
- "sections": [
- {
- "title": "MTD",
- "scopes": ["mtd", "io_mtd"]
- }
- ]
- },
- {
- "title": "Measured Boot",
- "scopes": ["measured-boot", "measured boot", "measured_boot"]
- },
- {
- "title": "MMC",
- "scopes": ["mmc", "drivers/mmc"]
- },
- {
- "title": "MTD",
- "scopes": ["mtd", "drivers/mtd"],
- "sections": [
- {
- "title": "NAND",
- "scopes": ["nand"],
- "sections": [
- {
- "title": "SPI NAND",
- "scopes": ["spi-nand", "spi_nand"]
- }
- ]
- }
- ]
- },
- {
- "title": "SCMI",
- "scopes": ["scmi", "scmi_common", "drivers/scmi-msg"]
- },
- {
- "title": "UFS",
- "scopes": ["ufs"]
- },
- {
- "title": "Arm",
- "scopes": ["arm-drivers"],
- "sections": [
- {
- "title": "Ethos-N",
- "scopes": ["ethos-n", "drivers/arm/ethosn"]
- },
- {
- "title": "GIC",
- "scopes": ["gic"],
- "sections": [
- {
- "title": "GICv3",
- "scopes": ["gicv3"],
- "sections": [
- {
- "title": "GIC-600AE",
- "scopes": ["gic600ae"]
- }
- ]
- }
- ]
- },
- {
- "title": "TZC",
- "scopes": ["tzc"],
- "sections": [
- {
- "title": "TZC-400",
- "scopes": ["tzc400", "drivers/tzc400"]
- }
- ]
- }
- ]
- },
- {
- "title": "Marvell",
- "scopes": ["marvell-drivers"],
- "sections": [
- {
- "title": "COMPHY",
- "scopes": ["marvell-comphy", "drivers/marvell/comphy"],
- "sections": [
- {
- "title": "Armada 3700",
- "scopes": ["marvell-comphy-3700", "drivers/marvell/comphy-3700"]
- },
- {
- "title": "CP110",
- "scopes": ["marvell-comphy-cp110", "drivers/marvell/comphy-cp110"]
- }
- ]
- },
- {
- "title": "UART",
- "scopes": ["marvell-uart", "plat/marvell/uart"]
- },
- {
- "title": "Armada",
- "scopes": ["armada-drivers"],
- "sections": [
- {
- "title": "A3K",
- "scopes": ["a3k-drivers"],
- "sections": [
- {
- "title": "A3720",
- "scopes": ["a3720-uart", "plat/marvell/a3720/uart"]
- }
- ]
- }
- ]
- }
- ]
- },
- {
- "title": "MediaTek",
- "scopes": ["mediatek-drivers"],
- "sections": [
- {
- "title": "APU",
- "scopes": ["mediatek-apu", "plat/mediatek/apu"]
- },
- {
- "title": "EMI MPU",
- "scopes": ["mediatek-emi-mpu", "plat/mediatek/mpu"]
- },
- {
- "title": "PMIC Wrapper",
- "scopes": ["mediatek-pmic-wrapper", "plat/mediatek/pmic_wrap"]
- },
- {
- "title": "MT8192",
- "scopes": ["mt8192-drivers"],
- "sections": [
- {
- "title": "SPM",
- "scopes": ["mt8192-spm", "mediatek/mt8192/spm"]
- }
- ]
- }
- ]
- },
- {
- "title": "NXP",
- "scopes": ["nxp-drivers"],
- "sections": [
- {
- "title": "DCFG",
- "scopes": ["nxp-dcfg", "driver/nxp/dcfg"]
- },
- {
- "title": "FLEXSPI",
- "scopes": ["flexspi", "include/drivers/flexspi", "driver/nxp/xspi"]
- },
- {
- "title": "SCFG",
- "scopes": ["nxp-scfg", "nxp/scfg"]
- },
- {
- "title": "SFP",
- "scopes": ["nxp-sfp", "drivers/nxp/sfp"]
- }
- ]
- },
- {
- "title": "Renesas",
- "scopes": ["renesas-drivers"],
- "sections": [
- {
- "title": "R-Car3",
- "scopes": ["rcar3-drivers", "drivers/rcar3"]
- }
- ]
- },
- {
- "title": "ST",
- "scopes": ["st-drivers", "drivers/st"],
- "sections": [
- {
- "title": "Clock",
- "scopes": ["st-clock", "stm32mp_clk", "drivers/st/clk", "stm32mp1_clk"]
- },
- {
- "title": "I/O",
- "scopes": ["st-io-drivers"],
- "sections": [
- {
- "title": "STM32 Image",
- "scopes": ["st-io-stm32image", "io-stm32image", "io_stm32image"]
- }
- ]
- },
- {
- "title": "SDMMC2",
- "scopes": ["st-sdmmc2", "stm32_sdmmc2"]
- },
- {
- "title": "ST PMIC",
- "scopes": ["st-pmic", "drivers/st/pmic"]
- },
- {
- "title": "STPMIC1",
- "scopes": ["stpmic1"]
- },
- {
- "title": "UART",
- "scopes": ["st-uart"],
- "sections": [
- {
- "title": "STM32 Console",
- "scopes": ["stm32-console", "stm32_console"]
- }
- ]
- },
- {
- "title": "USB",
- "scopes": ["st-usb", "drivers/st/usb"]
- }
- ]
- },
- {
- "title": "USB",
- "scopes": ["usb", "drivers/usb"]
- }
- ]
- },
- {
- "title": "Miscellaneous",
- "sections": [
- {
- "title": "AArch64",
- "scopes": ["aarch64"]
- },
- {
- "title": "Debug",
- "scopes": ["debug", "common/debug"]
- },
- {
- "title": "CRC32",
- "scopes": ["crc32"],
- "sections": [
- {
- "title": "Hardware CRC32",
- "scopes": ["hw-crc32", "hw_crc", "hw_crc32"]
- },
- {
- "title": "Software CRC32",
- "scopes": ["sw-crc32", "sw_crc32"]
- }
- ]
- },
- {
- "title": "DT Bindings",
- "scopes": ["dt-bindings"]
- },
- {
- "title": "FDT Wrappers",
- "scopes": ["fdt-wrappers"]
- },
- {
- "title": "FDTs",
- "scopes": ["fdts", "fdt"],
- "sections": [
- {
- "title": "Morello",
- "scopes": ["morello-fdts", "fdts/morello"]
- },
- {
- "title": "STM32MP1",
- "scopes": ["stm32mp1-fdts", "fdts stm32mp1"]
- }
- ]
- },
- {
- "title": "PIE",
- "scopes": ["pie"]
- },
- {
- "title": "Security",
- "scopes": ["security"]
- },
- {
- "title": "SDEI",
- "scopes": ["sdei"]
- },
- {
- "title": "TBBR",
- "scopes": ["tbbr"]
- },
- {
- "title": "NXP",
- "sections": [
- {
- "title": "OCRAM",
- "scopes": ["nxp-ocram", "nxp/common/ocram"]
- },
- {
- "title": "PSCI",
- "scopes": ["nxp-psci", "plat/nxp/common/psci"]
- }
- ]
- }
- ]
- },
- {
- "title": "Documentation",
- "scopes": ["docs", "doc"],
- "sections": [
- {
- "title": "Changelog",
- "scopes": ["changelog"]
- },
- {
- "title": "Commit Style",
- "scopes": ["commit-style"]
- },
- {
- "title": "Contribution Guidelines",
- "scopes": ["contributing", "contribution-guidelines", "docs-contributing.rst"]
- },
- {
- "title": "Maintainers",
- "scopes": ["maintainers"]
- },
- {
- "title": "Prerequisites",
- "scopes": ["prerequisites"]
- }
- ]
- },
- {
- "title": "Build System",
- "scopes": ["build", "makefile", "Makefile"],
- "sections": [
- {
- "title": "Git Hooks",
- "scopes": ["hooks"]
- }
- ]
- },
- {
- "title": "Tools",
- "sections": [
- {
- "title": "STM32 Image",
- "scopes": ["stm32image", "tools/stm32image"]
- },
- {
- "title": "fiptool",
- "scopes": ["fiptool"]
- }
- ]
- },
- {
- "title": "Dependencies",
- "scopes": ["deps"],
- "sections": [
- {
- "title": "checkpatch",
- "scopes": ["checkpatch"]
- },
- {
- "title": "libfdt",
- "scopes": ["libfdt"]
- },
- {
- "title": "Node Package Manager (NPM)",
- "scopes": ["npm"]
- }
- ]
- }
- ]
+ "path": "@commitlint/cz-commitlint"
}
diff --git a/.versionrc.js b/.versionrc.js
index 1046b28..f699a07 100644
--- a/.versionrc.js
+++ b/.versionrc.js
@@ -8,40 +8,87 @@
"use strict";
-const cz = require("./.cz.json");
+const fs = require("fs");
+const yaml = require("js-yaml");
/*
- * Convert the Commitizen types array into the format accepted by the Conventional Changelog
- * Conventional Commits plugin (which our own plugin extends).
+ * The types and scopes accepted by both Commitlint and Commitizen are defined by the changelog
+ * configuration file - `changelog.yaml` - as they decide which section of the changelog commits
+ * with a given type and scope are placed in.
*/
-const types = cz.types.map(type => {
- if (!type.hidden) {
- /*
- * Conventional Changelog prevents each section from appearing only if it has no designated
- * title, regardless of the value of the `hidden` flag.
- */
- type.section = type.title;
- }
- delete type.title;
- delete type.description;
+let changelog;
- return type;
-});
+try {
+ const contents = fs.readFileSync("changelog.yaml", "utf8");
+
+ changelog = yaml.load(contents);
+} catch (err) {
+ console.log(err);
+
+ throw err;
+}
+
+/*
+ * The next couple of functions are just used to transform the changelog YAML configuration
+ * structure into one accepted by the Conventional Changelog adapter (conventional-changelog-tf-a).
+ */
+
+function getTypes(sections) {
+ return sections.map(section => {
+ return {
+ "type": section.type,
+ "section": section.hidden ? undefined : section.title,
+ "hidden": section.hidden || false,
+ };
+ })
+}
+
+function getSections(subsections) {
+ return subsections.flatMap(subsection => {
+ const scope = subsection.scope ? [ subsection.scope ] : [];
+
+ return {
+ "title": subsection.title,
+ "sections": getSections(subsection.subsections || []),
+ "scopes": scope.concat(subsection.deprecated || []),
+ };
+ })
+};
+
+const types = getTypes(changelog.sections);
+const sections = getSections(changelog.subsections);
module.exports = {
"header": "# Change Log & Release Notes\n\nThis document contains a summary of the new features, changes, fixes and known\nissues in each release of Trusted Firmware-A.\n",
"preset": {
"name": "tf-a",
"commitUrlFormat": "https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/{{hash}}",
- "compareUrlFormat": "https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/{{previousTag}}..{{currentTag}}",
+ "compareUrlFormat": "https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/{{previousTag}}..refs/tags/{{currentTag}}",
"userUrlFormat": "https://github.com/{{user}}",
"types": types,
- "sections": cz.sections,
+ "sections": sections,
+ },
+ "infile": "docs/change-log.md",
+ "skip": {
+ "commit": true,
+ "tag": true
},
"bumpFiles": [
{
+ "filename": "package.json",
+ "type": "json"
+ },
+ {
+ "filename": "package-lock.json",
+ "type": "json"
+ },
+ {
+ "filename": "tools/conventional-changelog-tf-a/package.json",
+ "type": "json"
+ },
+ {
"filename": "Makefile",
"updater": {
"readVersion": function (contents) {
diff --git a/Makefile b/Makefile
index ed7b076..a238ee4 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -736,6 +736,12 @@
endif
endif
+ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT}),)
+ CRYPTO_SUPPORT := 1
+else
+ CRYPTO_SUPPORT := 0
+endif
+
# SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled.
ifeq ($(SDEI_SUPPORT)-$(SDEI_IN_FCONF),0-1)
$(error "SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled")
@@ -762,15 +768,6 @@
endif
endif
-# Trusted Boot is a prerequisite for Measured Boot. It provides trust that the
-# code taking the measurements and recording them has not been tampered
-# with. This is referred to as the Root of Trust for Measurement.
-ifeq ($(MEASURED_BOOT),1)
- ifneq (${TRUSTED_BOARD_BOOT},1)
- $(error MEASURED_BOOT requires TRUSTED_BOARD_BOOT=1)
- endif
-endif
-
ifeq ($(PSA_FWU_SUPPORT),1)
$(info PSA_FWU_SUPPORT is an experimental feature)
endif
@@ -1022,6 +1019,7 @@
SPM_MM \
SPMD_SPM_AT_SEL2 \
TRUSTED_BOARD_BOOT \
+ CRYPTO_SUPPORT \
USE_COHERENT_MEM \
USE_DEBUGFS \
ARM_IO_IN_DTB \
@@ -1136,6 +1134,7 @@
SPM_MM \
SPMD_SPM_AT_SEL2 \
TRUSTED_BOARD_BOOT \
+ CRYPTO_SUPPORT \
TRNG_SUPPORT \
USE_COHERENT_MEM \
USE_DEBUGFS \
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 663ec64..7399bc8 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,6 +15,7 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/auth/auth_mod.h>
+#include <drivers/auth/crypto_mod.h>
#include <drivers/console.h>
#include <lib/cpus/errata_report.h>
#include <lib/utils.h>
@@ -121,10 +122,10 @@
/* Perform remaining generic architectural setup from EL3 */
bl1_arch_setup();
-#if TRUSTED_BOARD_BOOT
+ crypto_mod_init();
+
/* Initialize authentication module */
auth_mod_init();
-#endif /* TRUSTED_BOARD_BOOT */
/* Initialize the measured boot */
bl1_plat_mboot_init();
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index 90fe39b..5da8037 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,7 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/auth/auth_mod.h>
+#include <drivers/auth/crypto_mod.h>
#include <drivers/console.h>
#include <drivers/fwu/fwu.h>
#include <lib/extensions/pauth.h>
@@ -89,10 +90,10 @@
fwu_init();
#endif /* PSA_FWU_SUPPORT */
-#if TRUSTED_BOARD_BOOT
+ crypto_mod_init();
+
/* Initialize authentication module */
auth_mod_init();
-#endif /* TRUSTED_BOARD_BOOT */
/* Initialize the Measured Boot backend */
bl2_plat_mboot_init();
diff --git a/changelog.yaml b/changelog.yaml
new file mode 100644
index 0000000..4e187ef
--- /dev/null
+++ b/changelog.yaml
@@ -0,0 +1,931 @@
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+#
+# The following block describes the top-level sections of the changelog. Commits are categorized
+# into these top-level sections based on the commit message "type":
+#
+# feat(xyz): add the xyz feature
+# ^^^^
+#
+
+sections:
+ - title: New Features
+ description: A new feature
+ type: feat
+
+ - title: Resolved Issues
+ description: A bug fix
+ type: fix
+
+ - title: Build System
+ description: Changes that affect the build system or external dependencies
+ type: build
+ hidden: true
+
+ - title: Continuous Integration
+ description: Changes to our CI configuration files and scripts
+ type: ci
+ hidden: true
+
+ - title: Build System
+ description: Documentation-only changes
+ type: docs
+ hidden: true
+
+ - title: Performance Improvements
+ description: A code change that improves performance
+ type: perf
+ hidden: true
+
+ - title: Code Refactoring
+ description: A code change that neither fixes a bug nor adds a feature
+ type: refactor
+ hidden: true
+
+ - title: Reverted Changes
+ description: Changes that revert a previous change
+ type: revert
+ hidden: true
+
+ - title: Style
+ description: Changes that do not affect the meaning of the code (white-space, formatting, missing semi-colons, etc.)
+ type: style
+ hidden: true
+
+ - title: Tests
+ description: Adding missing tests or correcting existing tests
+ type: test
+ hidden: true
+
+ - title: Miscellaneous
+ description: Any other change
+ type: chore
+ hidden: true
+
+#
+# The following block describes the sub-sections of the changelog. These sub-sections may appear in
+# any of the top-level sections, and describe the individual components that a change may relate to.
+#
+# Sub-sections have an optional associated commit message "scope":
+#
+# feat(xyz): add the xyz feature
+# ^^^
+#
+# This file also describes deprecated scopes, which are scopes that were used before we introduced
+# scope enforcement. These will not pass CI checks when used, but they will be used to generate the
+# changelog.
+#
+# Please note that new scopes should be kebab-case: https://en.wiktionary.org/wiki/kebab_case
+#
+
+subsections:
+ - title: Architecture
+
+ subsections:
+ - title: Activity Monitors Extension (FEAT_AMU)
+ scope: amu
+
+ - title: Support for the `HCRX_EL2` register (FEAT_HCX)
+ scope: hcx
+
+ - title: Memory Partitioning and Monitoring (MPAM) Extension (FEAT_MPAM)
+ scope: mpam
+
+ - title: Scalable Matrix Extension (FEAT_SME)
+ scope: sme
+
+ - title: Scalable Vector Extension (FEAT_SVE)
+ scope: sve
+
+ - title: System Register Trace Extensions (FEAT_ETMv4, FEAT_ETE and FEAT_ETEv1.1)
+ scope: sys-reg-trace
+
+ deprecated:
+ - sys_reg_trace
+
+ - title: Trace Buffer Extension (FEAT_TRBE)
+ scope: trbe
+
+ - title: Self-hosted Trace Extensions (FEAT_TRF)
+ scope: trf
+
+ - title: Platforms
+
+ subsections:
+ - title: Allwinner
+ scope: allwinner
+
+ deprecated:
+ - plat/allwinner
+
+ - title: Arm
+ scope: arm
+
+ deprecated:
+ - plat/arm
+
+ subsections:
+ - title: FPGA
+ scope: fpga
+
+ deprecated:
+ - arm_fgpa
+ - arm_fpga
+ - plat/arm_fpga
+
+ - title: FVP
+ scope: fvp
+
+ deprecated:
+ - plat/fvp
+
+ - title: FVP-R
+ scope: fvp-r
+
+ deprecated:
+ - fvp_r
+
+ - title: Juno
+ scope: juno
+
+ - title: Morello
+ scope: morello
+
+ - title: RD
+ scope: rd
+
+ subsections:
+ - title: RD-N2
+ scope: rdn2
+
+ deprecated:
+ - board/rdn2
+
+ - title: SGI
+ scope: sgi
+
+ deprecated:
+ - plat/sgi
+ - plat/arm/sgi
+
+ - title: TC
+ scope: tc
+
+ subsections:
+ - title: TC0
+ scope: tc0
+
+ deprecated:
+ - plat/tc0
+
+ - title: Marvell
+ scope: marvell
+
+ deprecated:
+ - plat/marvell
+
+ subsections:
+ - title: Armada
+ scope: armada
+
+ deprecated:
+ - plat/marvell/armada
+
+ subsections:
+ - title: A3K
+ scope: a3k
+
+ deprecated:
+ - plat/marvell/a3k
+
+ - title: A8K
+ scope: a8k
+
+ deprecated:
+ - plat/marvell/a8k
+
+ - title: MediaTek
+ scope: mediatek
+
+ deprecated:
+ - plat/mediatek/common
+ - plat/mediatek
+
+ subsections:
+ - title: MT8183
+ scope: mt8183
+
+ deprecated:
+ - plat/mediatek/mt8183
+
+ - title: MT8192
+ scope: mt8192
+
+ deprecated:
+ - plat/mdeiatek/mt8192
+
+ - title: MT8195
+ scope: mt8195
+
+ deprecated:
+ - plat/mediatek/me8195
+ - plat/mediatek/mt8195
+ - plat/mdeiatek/mt8195
+
+ - title: NVIDIA
+ scope: nvidia
+
+ subsections:
+ - title: Tegra
+ scope: tegra
+
+ deprecated:
+ - plat/tegra
+
+ subsections:
+ - title: Tegra 132
+ scope: tegra132
+
+ - title: NXP
+ scope: nxp
+
+ deprecated:
+ - plat/nxp
+ - plat/nxp/common
+
+ subsections:
+ - title: i.MX
+ scope: imx
+
+ deprecated:
+ - plat/imx
+ - plat/imx/imx
+
+ subsections:
+ - title: i.MX 8M
+ scope: imx8m
+
+ deprecated:
+ - plat/imx8m
+ - plat/imx/imx8m
+
+ subsections:
+ - title: i.MX 8M Mini
+ scope: imx8mm
+
+ deprecated:
+ - plat/imx/imx8m/imx8mm
+
+ - title: i.MX 8M Plus
+ scope: imx8mp
+
+ deprecated:
+ - plat/imx/imx8m/imx8mp
+
+ - title: Layerscape
+ scope: layerscape
+
+ deprecated:
+ - docs/nxp/layerscape
+
+ subsections:
+ - title: LS1028A
+ scope: ls1028a
+
+ deprecated:
+ - plat/nxp/ls1028a
+
+ subsections:
+ - title: LS1028ARDB
+ scope: ls1028ardb
+
+ deprecated:
+ - plat/nxp/ls1028ardb
+
+ - title: LX2
+ scope: lx2
+
+ deprecated:
+ - plat/nxp/lx2
+
+ subsections:
+ - title: LX216
+ scope: lx216
+
+ deprecated:
+ - plat/nxp/lx216x
+
+ subsections:
+ - title: LX2160
+ scope: lx2160
+
+ deprecated:
+ - plat/soc-lx2160
+
+ - title: QEMU
+ scope: qemu
+
+ deprecated:
+ - plat/qemu
+
+ - title: QTI
+ scope: qti
+
+ subsections:
+ - title: SC1780
+ scope: sc7180
+
+ deprecated:
+ - plat/qti/sc7180
+
+ - title: SC7280
+ scope: sc7280
+
+ deprecated:
+ - plat/qti/sc7280
+
+ - title: Raspberry Pi
+ scope: rpi
+
+ subsections:
+ - title: Raspberry Pi 4
+ scope: rpi4
+
+ - title: Renesas
+ scope: renesas
+
+ subsections:
+ - title: R-Car
+ scope: rcar
+
+ deprecated:
+ - plat/rcar
+
+ subsections:
+ - title: R-Car 3
+ scope: rcar3
+
+ deprecated:
+ - plat/rcar3
+
+ - title: Rockchip
+ scope: rockchip
+
+ subsections:
+ - title: RK3399
+ scope: rk3399
+
+ deprecated:
+ - rockchip/rk3399
+ - rk3399/suspend
+
+ - title: Socionext
+ scope: socionext
+
+ subsections:
+ - title: Synquacer
+ scope: synquacer
+
+ deprecated:
+ - plat/synquacer
+
+ - title: ST
+ scope: st
+
+ deprecated:
+ - plat/st
+
+ subsections:
+ - title: ST32MP1
+ scope: stm32mp1
+
+ deprecated:
+ - plat/st/stm32mp1
+
+ - title: Xilinx
+ scope: xilinx
+
+ deprecated:
+ - plat/xilinx
+
+ subsections:
+ - title: Versal
+ scope: versal
+
+ deprecated:
+ - plat/xilinx/versal/include
+ - plat/xilinx/versal
+ - plat/versal
+
+ - title: ZynqMP
+ scope: zynqmp
+
+ deprecated:
+ - plat/zynqmp
+ - plat/xilinx/zynqmp
+
+ - title: Bootloader Images
+ scope: bl
+
+ deprecated:
+ - bl_common
+
+ subsections:
+ - title: BL1
+ scope: bl1
+
+ - title: BL2
+ scope: bl2
+
+ - title: Services
+ scope: services
+
+ subsections:
+ - title: FF-A
+ scope: ffa
+
+ deprecated:
+ - ff-a
+
+ - title: RME
+ scope: rme
+
+ - title: SPM
+ scope: spm
+
+ deprecated:
+ - spmc
+ - spmd
+ - SPMD
+ - spm_mm
+
+ - title: Libraries
+
+ subsections:
+ - title: CPU Support
+ scope: cpus
+
+ deprecated:
+ - cpu
+ - errata
+ - errata_report
+
+ - title: EL3 Runtime
+ scope: el3-runtime
+
+ deprecated:
+ - el3_runtime
+
+ - title: FCONF
+ scope: fconf
+
+ - title: MPMM
+ scope: mpmm
+
+ - title: OP-TEE
+ scope: optee
+
+ deprecated:
+ - lib/optee
+
+ - title: PSCI
+ scope: psci
+
+ - title: GPT
+ scope: gpt
+
+ deprecated:
+ - gpt_rme
+
+ - title: SMCCC
+ scope: smccc
+
+ - title: Translation Tables
+ scope: xlat
+
+ - title: Drivers
+
+ subsections:
+ - title: Authentication
+ scope: auth
+
+ deprecated:
+ - driver/auth
+
+ subsections:
+ - title: CryptoCell-713
+ scope: cc-713
+
+ - title: FWU
+ scope: fwu
+
+ deprecated:
+ - fwu_metadata
+
+ - title: I/O
+ scope: io
+
+ subsections:
+ - title: MTD
+ scope: mtd
+
+ deprecated:
+ - io_mtd
+
+ - title: Measured Boot
+ scope: measured-boot
+
+ deprecated:
+ - measured boot
+ - measured_boot
+
+ - title: MMC
+ scope: mmc
+
+ deprecated:
+ - drivers/mmc
+
+ - title: MTD
+ scope: mtd
+
+ deprecated:
+ - drivers/mtd
+
+ subsections:
+ - title: NAND
+ scope: nand
+
+ subsections:
+ - title: SPI NAND
+ scope: spi-nand
+
+ deprecated:
+ - spi_nand
+
+ - title: SCMI
+ scope: scmi
+
+ deprecated:
+ - scmi_common
+ - drivers/scmi-msg
+
+ - title: UFS
+ scope: ufs
+
+ - title: Arm
+ scope: arm-drivers
+
+ subsections:
+ - title: Ethos-N
+ scope: ethos-n
+
+ deprecated:
+ - drivers/arm/ethosn
+
+ - title: GIC
+ scope: gic
+
+ subsections:
+ - title: GICv3
+ scope: gicv3
+
+ subsections:
+ - title: GIC-600AE
+ scope: gic600ae
+
+ - title: TZC
+ scope: tzc
+
+ subsections:
+ - title: TZC-400
+ scope: tzc400
+
+ deprecated:
+ - drivers/tzc400
+
+ - title: Marvell
+ scope: marvell-drivers
+
+ subsections:
+ - title: COMPHY
+ scope: marvell-comphy
+
+ deprecated:
+ - drivers/marvell/comphy
+
+ subsections:
+ - title: Armada 3700
+ scope: marvell-comphy-3700
+
+ deprecated:
+ - drivers/marvell/comphy-3700
+
+ - title: CP110
+ scope: marvell-comphy-cp110
+
+ deprecated:
+ - drivers/marvell/comphy-cp110
+
+ - title: UART
+ scope: marvell-uart
+
+ deprecated:
+ - plat/marvell/uart
+
+ - title: Armada
+ scope: armada-drivers
+
+ subsections:
+ - title: A3K
+ scope: a3k-drivers
+
+ subsections:
+ - title: A3720
+ scope: a3720-uart
+
+ deprecated:
+ - plat/marvell/a3720/uart
+
+ - title: MediaTek
+ scope: mediatek-drivers
+
+ subsections:
+ - title: APU
+ scope: mediatek-apu
+
+ deprecated:
+ - plat/mediatek/apu
+
+ - title: EMI MPU
+ scope: mediatek-emi-mpu
+
+ deprecated:
+ - plat/mediatek/mpu
+
+ - title: PMIC Wrapper
+ scope: mediatek-pmic-wrapper
+
+ deprecated:
+ - plat/mediatek/pmic_wrap
+
+ - title: MT8192
+ scope: mt8192-drivers
+
+ subsections:
+ - title: SPM
+ scope: mt8192-spm
+
+ deprecated:
+ - mediatek/mt8192/spm
+
+ - title: NXP
+ scope: nxp-drivers
+
+ subsections:
+ - title: DCFG
+ scope: nxp-dcfg
+
+ deprecated:
+ - driver/nxp/dcfg
+
+ - title: FLEXSPI
+ scope: flexspi
+
+ deprecated:
+ - include/drivers/flexspi
+ - driver/nxp/xspi
+
+ - title: SCFG
+ scope: nxp-scfg
+
+ deprecated:
+ - nxp/scfg
+
+ - title: SFP
+ scope: nxp-sfp
+
+ deprecated:
+ - drivers/nxp/sfp
+
+ - title: Renesas
+ scope: renesas-drivers
+
+ subsections:
+ - title: R-Car3
+ scope: rcar3-drivers
+
+ deprecated:
+ - drivers/rcar3
+
+ - title: ST
+ scope: st-drivers
+
+ deprecated:
+ - drivers/st
+
+ subsections:
+ - title: Clock
+ scope: st-clock
+
+ deprecated:
+ - stm32mp_clk
+ - drivers/st/clk
+ - stm32mp1_clk
+
+ - title: I/O
+ scope: st-io-drivers
+
+ subsections:
+ - title: STM32 Image
+ scope: st-io-stm32image
+
+ deprecated:
+ - io-stm32image
+ - io_stm32image
+
+ - title: fiptool
+ scope: fiptool
+
+ - title: SDMMC2
+ scope: st-sdmmc2
+
+ deprecated:
+ - stm32_sdmmc2
+
+ - title: ST PMIC
+ scope: st-pmic
+
+ deprecated:
+ - drivers/st/pmic
+
+ - title: STPMIC1
+ scope: stpmic1
+
+ - title: UART
+ scope: st-uart
+
+ subsections:
+ - title: STM32 Console
+ scope: stm32-console
+
+ deprecated:
+ - stm32_console
+
+ - title: USB
+ scope: st-usb
+
+ deprecated:
+ - drivers/st/usb
+
+ - title: USB
+ scope: usb
+
+ deprecated:
+ - drivers/usb
+
+ - title: Miscellaneous
+
+ subsections:
+ - title: AArch64
+ scope: aarch64
+
+ - title: Debug
+ scope: debug
+
+ deprecated:
+ - common/debug
+
+ - title: CRC32
+ scope: crc32
+
+ subsections:
+ - title: Hardware CRC32
+ scope: hw-crc32
+
+ deprecated:
+ - hw_crc
+ - hw_crc32
+
+ - title: Software CRC32
+ scope: sw-crc32
+
+ deprecated:
+ - sw_crc32
+
+ - title: DT Bindings
+ scope: dt-bindings
+
+ - title: FDT Wrappers
+ scope: fdt-wrappers
+
+ - title: FDTs
+ scope: fdts
+
+ deprecated:
+ - fdt
+
+ subsections:
+ - title: Morello
+ scope: morello-fdts
+
+ deprecated:
+ - fdts/morello
+
+ - title: STM32MP1
+ scope: stm32mp1-fdts
+
+ deprecated:
+ - fdts stm32mp1
+
+ - title: PIE
+ scope: pie
+
+ - title: Security
+ scope: security
+
+ - title: SDEI
+ scope: sdei
+
+ - title: TBBR
+ scope: tbbr
+
+ - title: NXP
+
+ subsections:
+ - title: OCRAM
+ scope: nxp-ocram
+
+ deprecated:
+ - nxp/common/ocram
+
+ - title: PSCI
+ scope: nxp-psci
+
+ deprecated:
+ - plat/nxp/common/psci
+
+ - title: Documentation
+ scope: docs
+
+ deprecated:
+ - doc
+
+ subsections:
+ - title: Changelog
+ scope: changelog
+
+ - title: Commit Style
+ scope: commit-style
+
+ - title: Contribution Guidelines
+ scope: contributing
+
+ deprecated:
+ - contribution-guidelines
+ - docs-contributing.rst
+
+ - title: Maintainers
+ scope: maintainers
+
+ - title: Prerequisites
+ scope: prerequisites
+
+ - title: Build System
+ scope: build
+
+ deprecated:
+ - makefile
+ - Makefile
+
+ subsections:
+ - title: Git Hooks
+ scope: hooks
+
+ - title: Tools
+
+ subsections:
+ - title: STM32 Image
+ scope: stm32image
+
+ deprecated:
+ - tools/stm32image
+
+ - title: Dependencies
+ scope: deps
+
+ subsections:
+ - title: checkpatch
+ scope: checkpatch
+
+ - title: commitlint
+ scope: commitlint
+
+ - title: libfdt
+ scope: libfdt
+
+ - title: Node Package Manager (NPM)
+ scope: npm
diff --git a/common/bl_common.c b/common/bl_common.c
index eb2352a..9bfaafd 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -143,25 +143,6 @@
return io_result;
}
-/*
- * Load an image and flush it out to main memory so that it can be executed
- * later by any CPU, regardless of cache and MMU state.
- */
-static int load_image_flush(unsigned int image_id,
- image_info_t *image_data)
-{
- int rc;
-
- rc = load_image(image_id, image_data);
- if (rc == 0) {
- flush_dcache_range(image_data->image_base,
- image_data->image_size);
- }
-
- return rc;
-}
-
-
#if TRUSTED_BOARD_BOOT
/*
* This function uses recursion to authenticate the parent images up to the root
@@ -202,30 +183,6 @@
return -EAUTH;
}
- if (is_parent_image == 0) {
- /*
- * Measure the image.
- * We do not measure its parents because these only play a role
- * in authentication, which is orthogonal to measured boot.
- *
- * TODO: Change this code if we change our minds about measuring
- * certificates.
- */
- rc = plat_mboot_measure_image(image_id, image_data);
- if (rc != 0) {
- return rc;
- }
-
- /*
- * Flush the image to main memory so that it can be executed
- * later by any CPU, regardless of cache and MMU state. This
- * is only needed for child images, not for the parents
- * (certificates).
- */
- flush_dcache_range(image_data->image_base,
- image_data->image_size);
- }
-
return 0;
}
#endif /* TRUSTED_BOARD_BOOT */
@@ -239,7 +196,7 @@
}
#endif
- return load_image_flush(image_id, image_data);
+ return load_image(image_id, image_data);
}
/*******************************************************************************
@@ -266,6 +223,25 @@
} while ((err != 0) && (plat_try_next_boot_source() != 0));
#endif /* PSA_FWU_SUPPORT */
+ if (err == 0) {
+ /*
+ * If loading of the image gets passed (along with its
+ * authentication in case of Trusted-Boot flow) then measure
+ * it (if MEASURED_BOOT flag is enabled).
+ */
+ err = plat_mboot_measure_image(image_id, image_data);
+ if (err != 0) {
+ return err;
+ }
+
+ /*
+ * Flush the image to main memory so that it can be executed
+ * later by any CPU, regardless of cache and MMU state.
+ */
+ flush_dcache_range(image_data->image_base,
+ image_data->image_size);
+ }
+
return err;
}
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 680683d..e0a7587 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -500,13 +500,6 @@
:|F|: lib/cpus/aarch64/denver.S
:|F|: plat/nvidia/
-NXP QorIQ Layerscape platform ports
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Jiafei Pan <jiafei.pan@nxp.com>
-:|G|: `qoriq-open-source`_
-:|F|: docs/plat/ls1043a.rst
-:|F|: plat/layerscape/
-
NXP i.MX 7 WaRP7 platform port and SoC drivers
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@@ -538,6 +531,8 @@
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
:|G|: `pangupta`_
+:|M|: Jiafei Pan <jiafei.pan@nxp.com>
+:|G|: `JiafeiPan`_
:|F|: docs/plat/nxp/
:|F|: plat/nxp/
:|F|: drivers/nxp/
@@ -552,6 +547,20 @@
:|F|: plat/nxp/soc-lx2160a/lx2160aqds
:|F|: plat/nxp/soc-lx2160a/lx2160ardb
+NXP SoC Part LS1028A and its platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Jiafei Pan <jiafei.pan@nxp.com>
+:|G|: `JiafeiPan`_
+:|F|: plat/nxp/soc-ls1028a
+:|F|: plat/nxp/soc-ls1028a/ls1028ardb
+
+NXP SoC Part LS1043A and its platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Jiafei Pan <jiafei.pan@nxp.com>
+:|G|: `JiafeiPan`_
+:|F|: plat/nxp/soc-ls1043a
+:|F|: plat/nxp/soc-ls1043a/ls1043ardb
+
QEMU platform port
^^^^^^^^^^^^^^^^^^
:|M|: Jens Wiklander <jens.wiklander@linaro.org>
@@ -780,7 +789,6 @@
.. _niej: https://github.com/niej
.. _npoushin: https://github.com/npoushin
.. _prabhakarlad: https://github.com/prabhakarlad
-.. _qoriq-open-source: https://github.com/qoriq-open-source
.. _remi-triplefault: https://github.com/repk
.. _rockchip-linux: https://github.com/rockchip-linux
.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
@@ -820,5 +828,6 @@
.. _arugan02: https://github.com/arugan02
.. _uarif1: https://github.com/uarif1
.. _pangupta: https://github.com/pangupta
+.. _JiafeiPan: https://github.com/JiafeiPan
.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/change-log.md b/docs/change-log.md
index 7f36d01..ab50968 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -3,7 +3,7 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
-## 2.6 (2021-11-22)
+## [2.6.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.5..refs/tags/v2.6) (2021-11-22)
### âš BREAKING CHANGES
@@ -983,7 +983,7 @@
- do not check merge commits ([77a0a7f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77a0a7f1d96b188849d1d8d8884b3c93857d3f69))
-## 2.5.0 (2021-05-17)
+## [2.5.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.4..refs/tags/v2.5) (2021-05-17)
### New Features
@@ -1547,7 +1547,7 @@
- Optimized the code to avoid unnecessary attempts to create non-requested
certificates
-## 2.4.0 (2020-11-17)
+## [2.4.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.3..refs/tags/v2.4) (2020-11-17)
### New Features
@@ -1972,7 +1972,7 @@
being worked around by disabling the warning for the platform until the
underlying issue is resolved in libfdt
-## 2.3 (2020-04-20)
+## [2.3.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.2..refs/tags/v2.3) (2020-04-20)
### New Features
@@ -2347,7 +2347,7 @@
- mediatek/mt6795: This platform does not build in this release
-## 2.2 (2019-10-22)
+## [2.2.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.1..refs/tags/v2.2) (2019-10-22)
### New Features
@@ -2658,7 +2658,7 @@
- mediatek/mt6795: This platform does not build in this release
-## 2.1 (2019-03-29)
+## [2.1.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.0..refs/tags/v2.1) (2019-03-29)
### New Features
@@ -3060,7 +3060,7 @@
- mediatek/mt6795: This platform does not build in this release
-## 2.0 (2018-10-02)
+## [2.0.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.6..refs/tags/v2.0) (2018-10-02)
### New Features
@@ -3091,7 +3091,7 @@
to be working after the removal of the deprecated interfaces although they do
build.
-## 1.6 (2018-09-21)
+## [1.6.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.5..refs/tags/v1.6) (2018-09-21)
### New Features
@@ -3298,7 +3298,7 @@
build process is skipped when running on a Windows host. Known issue from 1.5
version.
-## 1.5 (2018-03-20)
+## [1.5.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.4..refs/tags/v1.5) (2018-03-20)
### New features
@@ -3555,7 +3555,7 @@
- DTB creation not supported when building on a Windows host. This step in the
build process is skipped when running on a Windows host.
-## 1.4 (2017-07-07)
+## [1.4.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.3..refs/tags/v1.4) (2017-07-07)
### New features
@@ -3822,7 +3822,7 @@
platform, please use GCC compiler version of at least 5.0. See [PR#1002] for
more details.
-## 1.3 (2016-10-13)
+## [1.3.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.2..refs/tags/v1.3) (2016-10-13)
### New features
@@ -4021,7 +4021,7 @@
the TF-A build system interprets as errors.
- TBBR is not currently supported when running TF-A in AArch32 state.
-## 1.2 (2015-12-22)
+## [1.2.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.1..refs/tags/v1.2) (2015-12-22)
### New features
@@ -4158,7 +4158,7 @@
incomplete for PSCI, the TSP(D) and the Juno platform.
- Building TF-A with compiler optimisations disabled (`-O0`) fails.
-## 1.1 (2015-02-04)
+## [1.1.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.0..refs/tags/v1.1) (2015-02-04)
### New features
@@ -4297,7 +4297,7 @@
its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
- The Juno-specific firmware design documentation is incomplete.
-## 1.0 (2014-08-28)
+## [1.0.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v0.4..refs/tags/v1.0) (2014-08-28)
### New features
@@ -4443,7 +4443,7 @@
A similar change can be made to the other Cortex-A57-A53 Base FVP variants.
-## 0.4 (2014-06-03)
+## [0.4.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v0.3..refs/tags/v0.4) (2014-06-03)
### New features
@@ -4552,7 +4552,7 @@
- The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
-## 0.3 (2014-02-28)
+## [0.3.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v0.2..refs/tags/v0.3) (2014-02-28)
### New features
@@ -4689,7 +4689,7 @@
- The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
-## 0.2 (2013-10-25)
+## [0.2.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b825dc642cb6eb9a060e54bf8d69288fbee4904..refs/tags/v0.2) (2013-10-25)
### New features
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index d77875e..a34bb3c 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -529,9 +529,9 @@
the build. The default value is 40 in debug builds and 20 in release builds.
- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
- feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well
- in order to provide trust that the code taking the measurements and recording
- them has not been tampered with.
+ feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to
+ provide trust that the code taking the measurements and recording them has
+ not been tampered with.
This option defaults to 0.
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index eadd946..57cc488 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -27,7 +27,6 @@
warp7
imx8
imx8m
- ls1043a
nxp/index
poplar
qemu
diff --git a/docs/plat/ls1043a.rst b/docs/plat/ls1043a.rst
deleted file mode 100644
index 72a51f3..0000000
--- a/docs/plat/ls1043a.rst
+++ /dev/null
@@ -1,91 +0,0 @@
-NXP QorIQ® LS1043A
-==================
-
-The QorIQ® LS1043A processor is NXP's first quad-core, 64-bit Arm®-based
-processor for embedded networking. The LS1023A (two core version) and the
-LS1043A (four core version) deliver greater than 10 Gbps of performance
-in a flexible I/O package supporting fanless designs. This SoC is a
-purpose-built solution for small-form-factor networking and industrial
-applications with BOM optimizations for economic low layer PCB, lower cost
-power supply and single clock design. The new 0.9V versions of the LS1043A
-and LS1023A deliver addition power savings for applications such as Wireless
-LAN and to Power over Ethernet systems.
-
-LS1043ARDB Specification:
--------------------------
-Memory subsystem:
- * 2GByte DDR4 SDRAM (32bit bus)
- * 128 Mbyte NOR flash single-chip memory
- * 512 Mbyte NAND flash
- * 16 Mbyte high-speed SPI flash
- * SD connector to interface with the SD memory card
-
-Ethernet:
- * XFI 10G port
- * QSGMII with 4x 1G ports
- * Two RGMII ports
-
-PCIe:
- * PCIe2 (Lanes C) to mini-PCIe slot
- * PCIe3 (Lanes D) to PCIe slot
-
-USB 3.0: two super speed USB 3.0 type A ports
-
-UART: supports two UARTs up to 115200 bps for console
-
-More information are listed in `ls1043`_.
-
-Boot Sequence
--------------
-
-
-Bootrom --> TF-A BL1 --> TF-A BL2 --> TF-A BL1 --> TF-A BL31
---> BL32(Tee OS) --> TF-A BL31 --> BL33(u-boot) --> Linux kernel
-
-
-How to build
-------------
-
-Build Procedure
-~~~~~~~~~~~~~~~
-
-- Prepare AARCH64 toolchain.
-
-- Build u-boot and OPTee firstly, and get binary images: u-boot.bin and tee.bin
-
-- Build TF-A for Nor boot
-
- Build bl1:
-
- .. code:: shell
-
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 bl1
-
- Build fip:
-
- .. code:: shell
-
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 fip \
- BL33=u-boot.bin NEED_BL32=yes BL32=tee.bin SPD=opteed
-
-Deploy TF-A Images
-~~~~~~~~~~~~~~~~~~
-
-- Deploy TF-A images on Nor flash Alt Bank.
-
- .. code:: shell
-
- => tftp 82000000 bl1.bin
- => pro off all;era 64100000 +$filesize;cp.b 82000000 64100000 $filesize
-
- => tftp 82000000 fip.bin
- => pro off all;era 64120000 +$filesize;cp.b 82000000 64120000 $filesize
-
- Then change to Alt bank and boot up TF-A:
-
- .. code:: shell
-
- => cpld reset altbank
-
-
-.. _ls1043: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/qoriq-layerscape-arm-processors/qoriq-layerscape-1043a-and-1023a-multicore-communications-processors:LS1043A?lang_cd=en
diff --git a/docs/plat/nxp/nxp-layerscape.rst b/docs/plat/nxp/nxp-layerscape.rst
index 9a470e6..bae779c 100644
--- a/docs/plat/nxp/nxp-layerscape.rst
+++ b/docs/plat/nxp/nxp-layerscape.rst
@@ -40,7 +40,7 @@
Details about LS1028A can be found at `ls1028a`_.
-- LS1028ARDB Boards:
+- LS1028ARDB Board:
The LS1028A reference design board (RDB) is a computing, evaluation,
and development platform that supports industrial IoT applications, human
@@ -48,6 +48,51 @@
Details about LS1028A RDB board can be found at `ls1028ardb`_.
+3. LS1043A
+
+- SoC Overview:
+
+The Layerscape LS1043A processor is NXP's first quad-core, 64-bit Arm®-based
+processor for embedded networking. The LS1023A (two core version) and the
+LS1043A (four core version) deliver greater than 10 Gbps of performance
+in a flexible I/O package supporting fanless designs. This SoC is a
+purpose-built solution for small-form-factor networking and industrial
+applications with BOM optimizations for economic low layer PCB, lower cost
+power supply and single clock design. The new 0.9V versions of the LS1043A
+and LS1023A deliver addition power savings for applications such as Wireless
+LAN and to Power over Ethernet systems.
+
+Details about LS1043A can be found at `ls1043a`_.
+
+- LS1043ARDB Board:
+
+The LS1043A reference design board (RDB) is a computing, evaluation, and
+development platform that supports the Layerscape LS1043A architecture
+processor. The LS1043A-RDB can help shorten your time to market by providing
+the following features:
+
+Memory subsystem:
+ * 2GByte DDR4 SDRAM (32bit bus)
+ * 128 Mbyte NOR flash single-chip memory
+ * 512 Mbyte NAND flash
+ * 16 Mbyte high-speed SPI flash
+ * SD connector to interface with the SD memory card
+
+Ethernet:
+ * XFI 10G port
+ * QSGMII with 4x 1G ports
+ * Two RGMII ports
+
+PCIe:
+ * PCIe2 (Lanes C) to mini-PCIe slot
+ * PCIe3 (Lanes D) to PCIe slot
+
+USB 3.0: two super speed USB 3.0 type A ports
+
+UART: supports two UARTs up to 115200 bps for console
+
+Details about LS1043A RDB board can be found at `ls1043ardb`_.
+
Table of supported boot-modes by each platform & platform that needs FIP-DDR:
-----------------------------------------------------------------------------
@@ -60,6 +105,8 @@
+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
| ls1028ardb | yes | | | | yes | yes | | no |
+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
+| ls1043ardb | yes | | yes | yes | | | | no |
++---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
Boot Sequence
@@ -248,6 +295,8 @@
-- Then reset to alternate bank to boot up ATF.
+ Command for lx2160A and ls1028a platforms:
+
.. code:: shell
qixisreset altbank;
@@ -274,10 +323,56 @@
-- Then reset to sd/emmc to boot up ATF from sd/emmc as boot-source.
+ Command for lx2160A and ls1028a platforms:
+
.. code:: shell
qixisreset <sd or emmc>;
+ Command for ls1043a platform:
+
+ .. code:: shell
+
+ cpld reset <sd or emmc>;
+
+- Deploy ATF images on IFC nor flash from U-Boot prompt.
+
+ .. code:: shell
+
+ tftp 82000000 $path/bl2_nor.pbl;
+ protect off 64000000 +$filesize; erase 64000000 +$filesize; cp.b 82000000 64000000 $filesize;
+
+ tftp 82000000 $path/fip.bin;
+ protect off 64100000 +$filesize; erase 64100000 +$filesize; cp.b 82000000 64100000 $filesize;
+
+ -- Then reset to alternate bank to boot up ATF.
+
+ Command for ls1043a platform:
+
+ .. code:: shell
+
+ cpld reset altbank;
+
+- Deploy ATF images on IFC nand flash from U-Boot prompt.
+
+ .. code:: shell
+
+ tftp 82000000 $path/bl2_nand.pbl;
+ nand erase 0x0 $filesize; nand write 82000000 0x0 $filesize;
+
+ tftp 82000000 $path/fip.bin;
+ nand erase 0x100000 $filesize;nand write 82000000 0x100000 $filesize;
+
+ -- Then reset to nand flash to boot up ATF.
+
+ Command for ls1043a platform:
+
+ .. code:: shell
+
+ cpld reset nand;
+
+
+
Trusted Board Boot:
===================
@@ -298,4 +393,6 @@
.. _lx2160ardb: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/layerscape-lx2160a-multicore-communications-processor:LX2160A
.. _ls1028a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1028a-applications-processor:LS1028A
.. _ls1028ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB
+.. _ls1043a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1043a-and-1023a-processors:LS1043A
+.. _ls1043ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1043a-reference-design-board:LS1043A-RDB
.. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst
diff --git a/docs/process/commit-style.rst b/docs/process/commit-style.rst
index e9df5ce..de899ab 100644
--- a/docs/process/commit-style.rst
+++ b/docs/process/commit-style.rst
@@ -79,11 +79,10 @@
+--------------+---------------------------------------------------------------+
The permissible `scopes` are more flexible, and we maintain a list of them in
-our :download:`Commitizen configuration file <../../.cz.json>`. Scopes in this
-file are organized by their changelog section, each of which may have one or
-more accepted scopes, but only the first of which is considered to be "blessed".
-Scopes that are not blessed exist for changes submitted before scope enforcement
-came into effect, and are considered deprecated.
+our :download:`changelog configuration file <../../changelog.yaml>`. Scopes in
+this file are organized by their changelog section, where each changelog section
+has a single scope that is considered to be blessed, and possibly several
+deprecated scopes. Please avoid using deprecated scopes.
While we don't enforce scopes strictly, we do ask that commits use these if they
can, or add their own if no appropriate one exists (see :ref:`Adding Scopes`).
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 917ee4a..a99a2c7 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -339,9 +339,6 @@
/* Check we have a valid CoT registered */
assert(cot_desc_ptr != NULL);
- /* Crypto module */
- crypto_mod_init();
-
/* Image parser module */
img_parser_init();
}
diff --git a/drivers/auth/crypto_mod.c b/drivers/auth/crypto_mod.c
index 127eb0d..eada357 100644
--- a/drivers/auth/crypto_mod.c
+++ b/drivers/auth/crypto_mod.c
@@ -46,8 +46,13 @@
{
assert(crypto_lib_desc.name != NULL);
assert(crypto_lib_desc.init != NULL);
+#if TRUSTED_BOARD_BOOT
assert(crypto_lib_desc.verify_signature != NULL);
assert(crypto_lib_desc.verify_hash != NULL);
+#endif /* TRUSTED_BOARD_BOOT */
+#if MEASURED_BOOT
+ assert(crypto_lib_desc.calc_hash != NULL);
+#endif /* MEASURED_BOOT */
/* Initialize the cryptographic library */
crypto_lib_desc.init();
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c
index 114e6ad..0901d04 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_crypto.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -60,6 +60,7 @@
mbedtls_init();
}
+#if TRUSTED_BOARD_BOOT
/*
* Verify a signature.
*
@@ -218,6 +219,7 @@
return CRYPTO_SUCCESS;
}
+#endif /* TRUSTED_BOARD_BOOT */
#if MEASURED_BOOT
/*
@@ -366,7 +368,7 @@
/*
* Register crypto library descriptor
*/
-#if MEASURED_BOOT
+#if MEASURED_BOOT && TRUSTED_BOARD_BOOT
#if TF_MBEDTLS_USE_AES_GCM
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
auth_decrypt);
@@ -374,11 +376,13 @@
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
NULL);
#endif
-#else /* MEASURED_BOOT */
+#elif TRUSTED_BOARD_BOOT
#if TF_MBEDTLS_USE_AES_GCM
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash,
auth_decrypt);
#else
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL);
#endif
-#endif /* MEASURED_BOOT */
+#elif MEASURED_BOOT
+REGISTER_CRYPTO_LIB(LIB_NAME, init, calc_hash);
+#endif /* MEASURED_BOOT && TRUSTED_BOARD_BOOT */
diff --git a/drivers/nxp/drivers.mk b/drivers/nxp/drivers.mk
index c2db363..d77e985 100644
--- a/drivers/nxp/drivers.mk
+++ b/drivers/nxp/drivers.mk
@@ -89,3 +89,11 @@
ifeq (${GPIO_NEEDED},yes)
include ${PLAT_DRIVERS_PATH}/gpio/gpio.mk
endif
+
+ifeq (${IFC_NOR_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/ifc/nor/ifc_nor.mk
+endif
+
+ifeq (${IFC_NAND_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/ifc/nand/ifc_nand.mk
+endif
diff --git a/drivers/nxp/ifc/nand/ifc.h b/drivers/nxp/ifc/nand/ifc.h
new file mode 100644
index 0000000..56c5f92
--- /dev/null
+++ b/drivers/nxp/ifc/nand/ifc.h
@@ -0,0 +1,329 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IFC_H
+#define IFC_H
+
+#include <endian.h>
+
+#include <mmio.h>
+
+#define NXP_IFC_RUN_TIME_ADDR U(0x1000)
+
+/* CPSR - Chip Select Property Register Offset */
+#define EXT_CSPR(n) (U(0x000C) + (n * 0xC))
+#define CSPR(n) (U(0x0010) + (n * 0xC))
+#define CSOR(n) (U(0x0130) + (n * 0xC))
+#define EXT_CSOR(n) (U(0x0134) + (n * 0xC))
+#define IFC_AMASK_CS0 U(0x00A0)
+
+/* NAND specific Registers Offset */
+#define NCFGR (NXP_IFC_RUN_TIME_ADDR + U(0x0000))
+#define NAND_FCR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0014))
+
+#define ROW0 (NXP_IFC_RUN_TIME_ADDR + U(0x003C))
+#define ROW1 (NXP_IFC_RUN_TIME_ADDR + U(0x004C))
+#define COL0 (NXP_IFC_RUN_TIME_ADDR + U(0x0044))
+#define COL1 (NXP_IFC_RUN_TIME_ADDR + U(0x0054))
+
+#define NAND_BC (NXP_IFC_RUN_TIME_ADDR + U(0x0108))
+#define NAND_FIR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0110))
+#define NAND_FIR1 (NXP_IFC_RUN_TIME_ADDR + U(0x0114))
+#define NAND_FIR2 (NXP_IFC_RUN_TIME_ADDR + U(0x0118))
+#define NAND_CSEL (NXP_IFC_RUN_TIME_ADDR + U(0x015C))
+#define NANDSEQ_STRT (NXP_IFC_RUN_TIME_ADDR + U(0x0164))
+#define NAND_EVTER_STAT (NXP_IFC_RUN_TIME_ADDR + U(0x016C))
+#define NAND_AUTOBOOT_TRGR (NXP_IFC_RUN_TIME_ADDR + U(0x0284))
+
+/* Size of SRAM Buffer */
+#define CSPR_PS U(0x00000180)
+#define CSPR_PS_SHIFT 7
+#define CSPR_PS_8 0x1 // Port Size 8 bit
+#define CSPR_PS_16 0x2 // Port Size 16 bit
+#define CSPR_PS_32 0x3 // Port Size 32 bit
+
+/* Chip Select Option Register NAND Machine */
+#define CSOR_NAND_PGS U(0x00380000)
+#define CSOR_NAND_PGS_SHIFT 19
+#define CSOR_NAND_PGS_512 U(0x00000000)
+#define CSOR_NAND_PGS_2K U(0x00080000)
+#define CSOR_NAND_PGS_4K U(0x00100000)
+#define CSOR_NAND_PGS_8K U(0x00180000)
+#define CSOR_NAND_PGS_16K U(0x00200000)
+
+
+#define CSOR_NAND_PB U(0x00000700)
+#define CSOR_NAND_PB_32 U(0x00000000)
+#define CSOR_NAND_PB_64 U(0x00000100)
+#define CSOR_NAND_PB_128 U(0x00000200)
+#define CSOR_NAND_PB_256 U(0x00000300)
+#define CSOR_NAND_PB_512 U(0x00000400)
+#define CSOR_NAND_PB_1024 U(0x00000500)
+#define CSOR_NAND_PB_2048 U(0x00000600)
+#define CSOR_NAND_PPB_32 32
+#define CSOR_NAND_PPB_64 64
+#define CSOR_NAND_PPB_128 128
+#define CSOR_NAND_PPB_256 256
+#define CSOR_NAND_PPB_512 512
+#define CSOR_NAND_PPB_1024 1024
+#define CSOR_NAND_PPB_2048 2048
+
+/* NAND Chip select register */
+#define NAND_CSEL_SHIFT 26
+#define NAND_COL_MS_SHIFT 31
+
+/* FCR - Flash Command Register */
+#define FCR_CMD0 U(0xFF000000)
+#define FCR_CMD0_SHIFT 24
+#define FCR_CMD1 U(0x00FF0000)
+#define FCR_CMD1_SHIFT 16
+#define FCR_CMD2 U(0x0000FF00)
+#define FCR_CMD2_SHIFT 8
+#define FCR_CMD3 U(0x000000FF)
+#define FCR_CMD3_SHIFT 0
+
+/* FIR - Flash Instruction Register Opcode */
+#define FIR_OP0 U(0xFC000000)
+#define FIR_OP0_SHIFT 26
+#define FIR_OP1 U(0x03F00000)
+#define FIR_OP1_SHIFT 20
+#define FIR_OP2 U(0x000FC000)
+#define FIR_OP2_SHIFT 14
+#define FIR_OP3 U(0x00003F00)
+#define FIR_OP3_SHIFT 8
+#define FIR_OP4 U(0x000000FC)
+#define FIR_OP4_SHIFT 2
+#define FIR_OP5 U(0xFC000000)
+#define FIR_OP5_SHIFT 26
+#define FIR_OP6 U(0x03F00000)
+#define FIR_OP6_SHIFT 20
+
+/* Instruction Opcode - 6 bits */
+#define FIR_OP_NOP 0x00
+#define FIR_OP_CA0 0x01 /* Issue current column address */
+#define FIR_OP_CA1 0x02 /* Issue current column address */
+#define FIR_OP_RA0 0x05 /* Issue current column address */
+#define FIR_OP_RA1 0x06 /* Issue current column address */
+#define FIR_OP_CMD0 0x09 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CMD1 0x0a /* Issue command from FCR[CMD1] */
+#define FIR_OP_CMD2 0x0b /* Issue command from FCR[CMD2] */
+#define FIR_OP_CMD3 0x0c /* Issue command from FCR[CMD3] */
+#define FIR_OP_CW0 0x11 /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1 0x12 /* Wait then issue FCR[CMD1] */
+#define FIR_OP_CW2 0x13 /* Wait then issue FCR[CMD1] */
+#define FIR_OP_CW3 0x14 /* Wait then issue FCR[CMD1] */
+#define FIR_OP_WBCD 0x19 /* Wait then read FBCR bytes */
+#define FIR_OP_RBCD 0x1a /* Wait then read 1 or 2 bytes */
+#define FIR_OP_BTRD 0x1b /* Wait then read 1 or 2 bytes */
+#define FIR_OP_RDSTAT 0x1c /* Wait then read 1 or 2 bytes */
+#define FIR_OP_NWAIT 0x1d /* Wait then read 1 or 2 bytes */
+#define FIR_OP_WFR 0x1e /* Wait then read 1 or 2 bytes */
+
+#define NAND_SEQ_STRT_FIR_STRT U(0x80000000)
+#define NAND_SEQ_STRT_FIR_STRT_SHIFT 31
+
+#define NAND_EVTER_STAT_FTOER U(0x08000000)
+#define NAND_EVTER_STAT_WPER U(0x04000000)
+#define NAND_EVTER_STAT_ECCER U(0x02000000)
+#define NAND_EVTER_STAT_DQSER U(0x01000000)
+#define NAND_EVTER_STAT_RCW_DN U(0x00008000)
+#define NAND_EVTER_STAT_BOOT_DN U(0x00004000)
+#define NAND_EVTER_STAT_RCW_DN U(0x00008000)
+#define NAND_EVTER_STAT_OPC_DN U(0x80000000)
+#define NAND_EVTER_STAT_BBI_SRCH_SEL U(0x00000800)
+#define NCFGR_BOOT U(0x80000000)
+#define NAND_AUTOBOOT_TRGR_RCW_LD U(0x80000000)
+#define NAND_AUTOBOOT_TRGR_BOOT_LD U(0x20000000)
+
+/* ECC ERROR STATUS Registers */
+#define NAND_RCW_LD U(0x80000000)
+#define NAND_BOOT_LD U(0x20000000)
+
+/*Other Temp Defines */
+/*256 bad Blocks supported */
+#define BBT_SIZE 256
+
+/*Standard NAND flash commands */
+#define NAND_CMD_READ0 0
+#define NAND_CMD_READ1 1
+#define NAND_CMD_READOOB 0x50
+
+/*Extended commands for large page devices */
+#define NAND_CMD_READSTART 0x30
+
+#define NAND_TIMEOUT_MS 40
+
+#define EMPTY_VAL_CHECK U(0xFFFFFFFF)
+#define EMPTY_VAL 0xFF
+
+
+#define MAIN 0
+#define SPARE 1
+
+#define GOOD_BLK 1
+#define BAD_BLK 0
+#define DIV_2 2
+
+#define ATTRIBUTE_PGSZ 0xa
+#define ATTRIBUTE_PPB 0xb
+
+#define CSPR_PORT_SIZE_8 (0x1 << 7)
+#define CSPR_PORT_SIZE_16 (0x2 << 7)
+#define CSPR_PORT_SIZE_32 (0x3 << 7)
+
+/* NAND specific */
+#define RCW_SRC_NAND_PORT_MASK U(0x00000080)
+
+#define NAND_DEFAULT_CSPR U(0x00000053)
+#define NAND_DEFAULT_CSOR U(0x0180C00C)
+#define NAND_DEFAULT_EXT_CSPR U(0x00000000)
+#define NAND_DEFAULT_EXT_CSOR U(0x00000000)
+#define NAND_DEFAULT_FTIM0 U(0x181c0c10)
+#define NAND_DEFAULT_FTIM1 U(0x5454141e)
+#define NAND_DEFAULT_FTIM2 U(0x03808034)
+#define NAND_DEFAULT_FTIM3 U(0x2c000000)
+
+#define NAND_CSOR_ECC_MODE_DISABLE U(0x00000000)
+#define NAND_CSOR_ECC_MODE0 U(0x84000000)
+#define NAND_CSOR_ECC_MODE1 U(0x94000000)
+#define NAND_CSOR_ECC_MODE2 U(0xa4000000)
+#define NAND_CSOR_ECC_MODE3 U(0xb4000000)
+#define NAND_CSOR_PAGE_SIZE_2K (0x1 << 19)
+#define NAND_CSOR_PAGE_SIZE_4K (0x2 << 19)
+#define NAND_CSOR_PAGE_SIZE_8K (0x3 << 19)
+#define NAND_CSOR_PAGE_SIZE_16K (0x4 << 19)
+#define NAND_CSOR_PPB_64 (0x1 << 8)
+#define NAND_CSOR_PPB_128 (0x2 << 8)
+#define NAND_CSOR_PPB_256 (0x3 << 8)
+#define NAND_CSOR_PPB_512 (0x4 << 8)
+
+/* BBI INDICATOR for NAND_2K(CFG_RCW_SRC[1]) for
+ * devices greater than 2K page size(CFG_RCW_SRC[3])
+ */
+#define RCW_SRC_NAND_BBI_MASK U(0x00000008)
+#define RCW_SRC_NAND_BBI_MASK_NAND_2K U(0x00000002)
+#define NAND_BBI_ONFI_2K (0x1 << 1)
+#define NAND_BBI_ONFI (0x1 << 3)
+
+#define RCW_SRC_NAND_PAGE_MASK U(0x00000070)
+#define RCW_SRC_NAND_PAGE_MASK_NAND_2K U(0x0000000C)
+#define NAND_2K_XXX 0x00
+#define NAND_2K_64 0x04
+#define NAND_2K_128 0x08
+#define NAND_4K_128 0x10
+#define NAND_4K_256 0x20
+#define NAND_4K_512 0x30
+#define NAND_8K_128 0x40
+#define NAND_8K_256 0x50
+#define NAND_8K_512 0x60
+#define NAND_16K_512 0x70
+#define BLOCK_LEN_2K 2048
+
+#define RCW_SRC_NAND_ECC_MASK U(0x00000007)
+#define RCW_SRC_NAND_ECC_MASK_NAND_2K U(0x00000001)
+#define NAND_ECC_DISABLE 0x0
+#define NAND_ECC_4_520 0x1
+#define NAND_ECC_8_528 0x5
+#define NAND_ECC_24_1K 0x6
+#define NAND_ECC_40_1K 0x7
+
+#define NAND_SPARE_2K U(0x00000040)
+#define NAND_SPARE_4K_ECC_M0 U(0x00000080)
+#define NAND_SPARE_4K_ECC_M1 U(0x000000D2)
+#define NAND_SPARE_4K_ECC_M2 U(0x000000B0)
+#define NAND_SPARE_4K_ECC_M3 U(0x00000120)
+#define NAND_SPARE_8K_ECC_M0 U(0x00000088)
+#define NAND_SPARE_8K_ECC_M1 U(0x00000108)
+#define NAND_SPARE_8K_ECC_M2 U(0x00000158)
+#define NAND_SPARE_8K_ECC_M3 U(0x00000238)
+#define NAND_SPARE_16K_ECC_M0 U(0x00000108)
+#define NAND_SPARE_16K_ECC_M1 U(0x00000208)
+#define NAND_SPARE_16K_ECC_M2 U(0x000002A8)
+#define NAND_SPARE_16K_ECC_M3 U(0x00000468)
+
+struct nand_info {
+ uintptr_t ifc_register_addr;
+ uintptr_t ifc_region_addr;
+ uint32_t page_size;
+ uint32_t port_size;
+ uint32_t blk_size;
+ uint32_t ppb;
+ uint32_t pi_width; /* Bits Required to index a page in block */
+ uint32_t ral;
+ uint32_t ibr_flow;
+ uint32_t bbt[BBT_SIZE];
+ uint32_t lgb; /* Last Good Block */
+ uint32_t bbt_max; /* Total entries in bbt */
+ uint32_t bzero_good;
+ uint8_t bbs;
+ uint8_t bad_marker_loc;
+ uint8_t onfi_dev_flag;
+ uint8_t init_time_boot_flag;
+ uint8_t *buf;
+};
+
+struct ifc_regs {
+ uint32_t ext_cspr;
+ uint32_t cspr;
+ uint32_t csor;
+ uint32_t ext_csor;
+};
+
+struct sec_nand_info {
+ uint32_t cspr_port_size;
+ uint32_t csor_ecc_mode;
+ uint32_t csor_page_size;
+ uint32_t csor_ppb;
+ uint32_t ext_csor_spare_size;
+ uint32_t onfi_flag;
+};
+
+struct sec_nor_info {
+ uint32_t cspr_port_size;
+ uint32_t csor_nor_mode;
+ uint32_t csor_adm_shift;
+ uint32_t port_size;
+ uint32_t addr_bits;
+};
+
+enum ifc_chip_sel {
+ IFC_CS0,
+ IFC_CS1,
+ IFC_CS2,
+ IFC_CS3,
+ IFC_CS4,
+ IFC_CS5,
+ IFC_CS6,
+ IFC_CS7,
+};
+
+enum ifc_ftims {
+ IFC_FTIM0,
+ IFC_FTIM1,
+ IFC_FTIM2,
+ IFC_FTIM3,
+};
+
+#ifdef NXP_IFC_BE
+#define nand_in32(a) bswap32(mmio_read_32((uintptr_t)a))
+#define nand_out32(a, v) mmio_write_32((uintptr_t)a, bswap32(v))
+#else
+#define nand_in32(a) mmio_read_32((uintptr_t)a)
+#define nand_out32(a, v) mmio_write_32((uintptr_t)a, v)
+#endif
+
+/* Read Write on IFC registers */
+static inline void write_reg(struct nand_info *nand, uint32_t reg, uint32_t val)
+{
+ nand_out32(nand->ifc_register_addr + reg, val);
+}
+
+static inline uint32_t read_reg(struct nand_info *nand, uint32_t reg)
+{
+ return nand_in32(nand->ifc_register_addr + reg);
+}
+
+#endif /* IFC_H */
diff --git a/drivers/nxp/ifc/nand/ifc_nand.c b/drivers/nxp/ifc/nand/ifc_nand.c
new file mode 100644
index 0000000..1f7092a
--- /dev/null
+++ b/drivers/nxp/ifc/nand/ifc_nand.c
@@ -0,0 +1,658 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/io/io_block.h>
+#include "ifc.h"
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <nxp_timer.h>
+
+/* Private structure for NAND driver data */
+static struct nand_info nand_drv_data;
+
+static int update_bbt(uint32_t idx, uint32_t blk, uint32_t *updated,
+ struct nand_info *nand);
+
+static int nand_wait(struct nand_info *nand)
+{
+ int timeout = 1;
+ uint32_t neesr;
+ unsigned long start_time;
+
+ start_time = get_timer_val(0);
+
+ while (get_timer_val(start_time) < NAND_TIMEOUT_MS) {
+ /* clear the OPC event */
+ neesr = read_reg(nand, NAND_EVTER_STAT);
+ if (neesr & NAND_EVTER_STAT_OPC_DN) {
+ write_reg(nand, NAND_EVTER_STAT, neesr);
+ timeout = 0;
+
+ /* check for other errors */
+ if (neesr & NAND_EVTER_STAT_FTOER) {
+ ERROR("%s NAND_EVTER_STAT_FTOER occurs\n",
+ __func__);
+ return -1;
+ } else if (neesr & NAND_EVTER_STAT_ECCER) {
+ ERROR("%s NAND_EVTER_STAT_ECCER occurs\n",
+ __func__);
+ return -1;
+ } else if (neesr & NAND_EVTER_STAT_DQSER) {
+ ERROR("%s NAND_EVTER_STAT_DQSER occurs\n",
+ __func__);
+ return -1;
+ }
+
+ break;
+ }
+ }
+
+ if (timeout) {
+ ERROR("%s ERROR_NAND_TIMEOUT occurs\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+static uint32_t nand_get_port_size(struct nand_info *nand)
+{
+ uint32_t port_size = U(0);
+ uint32_t cs_reg;
+ uint32_t cur_cs;
+
+ cur_cs = U(0);
+ cs_reg = CSPR(cur_cs);
+ port_size = (read_reg(nand, cs_reg) & CSPR_PS) >> CSPR_PS_SHIFT;
+ switch (port_size) {
+ case CSPR_PS_8:
+ port_size = U(8);
+ break;
+ case CSPR_PS_16:
+ port_size = U(16);
+ break;
+ case CSPR_PS_32:
+ port_size = U(32);
+ break;
+ default:
+ port_size = U(8);
+ }
+
+ return port_size;
+}
+
+static uint32_t nand_get_page_size(struct nand_info *nand)
+{
+ uint32_t pg_size;
+ uint32_t cs_reg;
+ uint32_t cur_cs;
+
+ cur_cs = 0;
+ cs_reg = CSOR(cur_cs);
+ pg_size = read_reg(nand, cs_reg) & CSOR_NAND_PGS;
+ switch (pg_size) {
+ case CSOR_NAND_PGS_2K:
+ pg_size = U(2048);
+ break;
+ case CSOR_NAND_PGS_4K:
+ pg_size = U(4096);
+ break;
+ case CSOR_NAND_PGS_8K:
+ pg_size = U(8192);
+ break;
+ case CSOR_NAND_PGS_16K:
+ pg_size = U(16384);
+ break;
+ default:
+ pg_size = U(512);
+ }
+
+ return pg_size;
+}
+
+static uint32_t nand_get_pages_per_blk(struct nand_info *nand)
+{
+ uint32_t pages_per_blk;
+ uint32_t cs_reg;
+ uint32_t cur_cs;
+
+ cur_cs = 0;
+ cs_reg = CSOR(cur_cs);
+ pages_per_blk = (read_reg(nand, cs_reg) & CSOR_NAND_PB);
+ switch (pages_per_blk) {
+ case CSOR_NAND_PB_32:
+ pages_per_blk = U(32);
+ break;
+ case CSOR_NAND_PB_64:
+ pages_per_blk = U(64);
+ break;
+ case CSOR_NAND_PB_128:
+ pages_per_blk = U(128);
+ break;
+ case CSOR_NAND_PB_256:
+ pages_per_blk = U(256);
+ break;
+ case CSOR_NAND_PB_512:
+ pages_per_blk = U(512);
+ break;
+ case CSOR_NAND_PB_1024:
+ pages_per_blk = U(1024);
+ break;
+ case CSOR_NAND_PB_2048:
+ pages_per_blk = U(2048);
+ break;
+ default:
+ pages_per_blk = U(0);
+ }
+
+ return pages_per_blk;
+}
+
+static uint32_t get_page_index_width(uint32_t ppb)
+{
+ switch (ppb) {
+ case CSOR_NAND_PPB_32:
+ return U(5);
+ case CSOR_NAND_PPB_64:
+ return U(6);
+ case CSOR_NAND_PPB_128:
+ return U(7);
+ case CSOR_NAND_PPB_256:
+ return U(8);
+ case CSOR_NAND_PPB_512:
+ return U(9);
+ case CSOR_NAND_PPB_1024:
+ return U(10);
+ case CSOR_NAND_PPB_2048:
+ return U(11);
+ default:
+ return U(5);
+ }
+}
+
+static void nand_get_params(struct nand_info *nand)
+{
+ nand->port_size = nand_get_port_size(nand);
+
+ nand->page_size = nand_get_page_size(nand);
+
+ /*
+ * Set Bad marker Location for LP / SP
+ * Small Page : 8 Bit : 0x5
+ * Small Page : 16 Bit : 0xa
+ * Large Page : 8 /16 Bit : 0x0
+ */
+ nand->bad_marker_loc = (nand->page_size == 512) ?
+ ((nand->port_size == 8) ? 0x5 : 0xa) : 0;
+
+ /* check for the device is ONFI compliant or not */
+ nand->onfi_dev_flag =
+ (read_reg(nand, NAND_EVTER_STAT) & NAND_EVTER_STAT_BBI_SRCH_SEL)
+ ? 1 : 0;
+
+ /* NAND Blk serached count for incremental Bad block search cnt */
+ nand->bbs = 0;
+
+ /* pages per Block */
+ nand->ppb = nand_get_pages_per_blk(nand);
+
+ /* Blk size */
+ nand->blk_size = nand->page_size * nand->ppb;
+
+ /* get_page_index_width */
+ nand->pi_width = get_page_index_width(nand->ppb);
+
+ /* bad block table init */
+ nand->lgb = 0;
+ nand->bbt_max = 0;
+ nand->bzero_good = 0;
+ memset(nand->bbt, EMPTY_VAL, BBT_SIZE * sizeof(nand->bbt[0]));
+}
+
+static int nand_init(struct nand_info *nand)
+{
+ uint32_t ncfgr = 0;
+
+ /* Get nand Parameters from IFC */
+ nand_get_params(nand);
+
+ /* Clear all errors */
+ write_reg(nand, NAND_EVTER_STAT, U(0xffffffff));
+
+ /*
+ * Disable autoboot in NCFGR. Mapping will change from
+ * physical to logical for SRAM buffer
+ */
+ ncfgr = read_reg(nand, NCFGR);
+ write_reg(nand, NCFGR, (ncfgr & ~NCFGR_BOOT));
+
+ return 0;
+}
+
+static int nand_read_data(
+ uintptr_t ifc_region_addr,
+ uint32_t row_add,
+ uint32_t col_add,
+ uint32_t byte_cnt,
+ uint8_t *data,
+ uint32_t main_spare,
+ struct nand_info *nand)
+{
+ uint32_t page_size_add_bits = U(0);
+ uint32_t page_add_in_actual, page_add;
+ uintptr_t sram_addr_calc;
+ int ret;
+ uint32_t col_val;
+
+ /* Programming MS bit to read from spare area.*/
+ col_val = (main_spare << NAND_COL_MS_SHIFT) | col_add;
+
+ write_reg(nand, NAND_BC, byte_cnt);
+
+ write_reg(nand, ROW0, row_add);
+ write_reg(nand, COL0, col_val);
+
+ /* Program FCR for small Page */
+ if (nand->page_size == U(512)) {
+ if (byte_cnt == 0 ||
+ (byte_cnt != 0 && main_spare == 0 && col_add <= 255)) {
+ write_reg(nand, NAND_FCR0,
+ (NAND_CMD_READ0 << FCR_CMD0_SHIFT));
+ } else if (main_spare == 0) {
+ write_reg(nand, NAND_FCR0,
+ (NAND_CMD_READ1 << FCR_CMD0_SHIFT));
+ } else {
+ write_reg(nand, NAND_FCR0,
+ (NAND_CMD_READOOB << FCR_CMD0_SHIFT));
+ }
+
+ } else {
+ /* Program FCR for Large Page */
+ write_reg(nand, NAND_FCR0, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
+ (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
+ }
+ if (nand->page_size == U(512)) {
+ write_reg(nand, NAND_FIR0, ((FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CA0 << FIR_OP1_SHIFT) |
+ (FIR_OP_RA0 << FIR_OP2_SHIFT) |
+ (FIR_OP_BTRD << FIR_OP3_SHIFT) |
+ (FIR_OP_NOP << FIR_OP4_SHIFT)));
+ write_reg(nand, NAND_FIR1, U(0x00000000));
+ } else {
+ write_reg(nand, NAND_FIR0, ((FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CA0 << FIR_OP1_SHIFT) |
+ (FIR_OP_RA0 << FIR_OP2_SHIFT) |
+ (FIR_OP_CMD1 << FIR_OP3_SHIFT) |
+ (FIR_OP_BTRD << FIR_OP4_SHIFT)));
+
+ write_reg(nand, NAND_FIR1, (FIR_OP_NOP << FIR_OP5_SHIFT));
+ }
+ write_reg(nand, NANDSEQ_STRT, NAND_SEQ_STRT_FIR_STRT);
+
+ ret = nand_wait(nand);
+ if (ret != 0)
+ return ret;
+
+ /* calculate page_size_add_bits i.e bits
+ * in sram address corresponding to area
+ * within a page for sram
+ */
+ if (nand->page_size == U(512))
+ page_size_add_bits = U(10);
+ else if (nand->page_size == U(2048))
+ page_size_add_bits = U(12);
+ else if (nand->page_size == U(4096))
+ page_size_add_bits = U(13);
+ else if (nand->page_size == U(8192))
+ page_size_add_bits = U(14);
+ else if (nand->page_size == U(16384))
+ page_size_add_bits = U(15);
+
+ page_add = row_add;
+
+ page_add_in_actual = (page_add << page_size_add_bits) & U(0x0000FFFF);
+
+ if (byte_cnt == 0)
+ col_add = U(0);
+
+ /* Calculate SRAM address for main and spare area */
+ if (main_spare == 0)
+ sram_addr_calc = ifc_region_addr | page_add_in_actual | col_add;
+ else
+ sram_addr_calc = ifc_region_addr | page_add_in_actual |
+ (col_add + nand->page_size);
+
+ /* Depending Byte_count copy full page or partial page from SRAM */
+ if (byte_cnt == 0)
+ memcpy(data, (void *)sram_addr_calc,
+ nand->page_size);
+ else
+ memcpy(data, (void *)sram_addr_calc, byte_cnt);
+
+ return 0;
+}
+
+static int nand_read(struct nand_info *nand, int32_t src_addr,
+ uintptr_t dst, uint32_t size)
+{
+ uint32_t log_blk = U(0);
+ uint32_t pg_no = U(0);
+ uint32_t col_off = U(0);
+ uint32_t row_off = U(0);
+ uint32_t byte_cnt = U(0);
+ uint32_t read_cnt = U(0);
+ uint32_t i = U(0);
+ uint32_t updated = U(0);
+
+ int ret = 0;
+ uint8_t *out = (uint8_t *)dst;
+
+ uint32_t pblk;
+
+ /* loop till size */
+ while (size) {
+ log_blk = (src_addr / nand->blk_size);
+ pg_no = ((src_addr - (log_blk * nand->blk_size)) /
+ nand->page_size);
+ pblk = log_blk;
+
+ // iterate the bbt to find the block
+ for (i = 0; i <= nand->bbt_max; i++) {
+ if (nand->bbt[i] == EMPTY_VAL_CHECK) {
+ ret = update_bbt(i, pblk, &updated, nand);
+
+ if (ret != 0)
+ return ret;
+ /*
+ * if table not updated and we reached
+ * end of table
+ */
+ if (!updated)
+ break;
+ }
+
+ if (pblk < nand->bbt[i])
+ break;
+ else if (pblk >= nand->bbt[i])
+ pblk++;
+ }
+
+ col_off = (src_addr % nand->page_size);
+ if (col_off) {
+ if ((col_off + size) < nand->page_size)
+ byte_cnt = size;
+ else
+ byte_cnt = nand->page_size - col_off;
+
+ row_off = (pblk << nand->pi_width) | pg_no;
+
+ ret = nand_read_data(
+ nand->ifc_region_addr,
+ row_off,
+ col_off,
+ byte_cnt, out, MAIN, nand);
+
+ if (ret != 0)
+ return ret;
+ } else {
+ /*
+ * fullpage/Partial Page
+ * if byte_cnt = 0 full page
+ * else partial page
+ */
+ if (size < nand->page_size) {
+ byte_cnt = size;
+ read_cnt = size;
+ } else {
+ byte_cnt = nand->page_size;
+ read_cnt = 0;
+ }
+ row_off = (pblk << nand->pi_width) | pg_no;
+
+ ret = nand_read_data(
+ nand->ifc_region_addr,
+ row_off,
+ 0,
+ read_cnt, out, MAIN, nand);
+
+ if (ret != 0) {
+ ERROR("Error from nand-read_data %d\n", ret);
+ return ret;
+ }
+ }
+ src_addr += byte_cnt;
+ out += byte_cnt;
+ size -= byte_cnt;
+ }
+ return 0;
+}
+
+static int isgoodblock(uint32_t blk, uint32_t *gb, struct nand_info *nand)
+{
+ uint8_t buf[2];
+ int ret;
+ uint32_t row_add;
+
+ *gb = 0;
+
+ /* read Page 0 of blk */
+ ret = nand_read_data(
+ nand->ifc_region_addr,
+ blk << nand->pi_width,
+ nand->bad_marker_loc,
+ 0x2, buf, 1, nand);
+
+ if (ret != 0)
+ return ret;
+
+ /* For ONFI devices check Page 0 and Last page of block for
+ * Bad Marker and for NON-ONFI Page 0 and 1 for Bad Marker
+ */
+ row_add = (blk << nand->pi_width);
+ if (nand->port_size == 8) {
+ /* port size is 8 Bit */
+ /* check if page 0 has 0xff */
+ if (buf[0] == 0xff) {
+ /* check page 1 */
+ if (nand->onfi_dev_flag)
+ ret = nand_read_data(
+ nand->ifc_region_addr,
+ row_add | (nand->ppb - 1),
+ nand->bad_marker_loc,
+ 0x2, buf, SPARE, nand);
+ else
+ ret = nand_read_data(
+ nand->ifc_region_addr,
+ row_add | 1,
+ nand->bad_marker_loc,
+ 0x2, buf, SPARE, nand);
+
+ if (ret != 0)
+ return ret;
+
+ if (buf[0] == 0xff)
+ *gb = GOOD_BLK;
+ else
+ *gb = BAD_BLK;
+ } else {
+ /* no, so it is bad blk */
+ *gb = BAD_BLK;
+ }
+ } else {
+ /* Port size 16-Bit */
+ /* check if page 0 has 0xffff */
+ if ((buf[0] == 0xff) &&
+ (buf[1] == 0xff)) {
+ /* check page 1 for 0xffff */
+ if (nand->onfi_dev_flag) {
+ ret = nand_read_data(
+ nand->ifc_region_addr,
+ row_add | (nand->ppb - 1),
+ nand->bad_marker_loc,
+ 0x2, buf, SPARE, nand);
+ } else {
+ ret = nand_read_data(
+ nand->ifc_region_addr,
+ row_add | 1,
+ nand->bad_marker_loc,
+ 0x2, buf, SPARE, nand);
+ }
+
+ if (ret != 0)
+ return ret;
+
+ if ((buf[0] == 0xff) &&
+ (buf[1] == 0xff)) {
+ *gb = GOOD_BLK;
+ } else {
+ *gb = BAD_BLK;
+ }
+ } else {
+ /* no, so it is bad blk */
+ *gb = BAD_BLK;
+ }
+ }
+ return 0;
+}
+
+static int update_bbt(uint32_t idx, uint32_t blk,
+ uint32_t *updated, struct nand_info *nand)
+{
+ uint32_t sblk;
+ uint32_t lgb;
+ int ret;
+
+ if (nand->bzero_good && blk == 0)
+ return 0;
+
+ /* special case for lgb == 0 */
+ /* if blk <= lgb retrun */
+ if (nand->lgb != 0 && blk <= nand->lgb)
+ return 0;
+
+ *updated = 0;
+
+ /* if blk is more than lgb, iterate from lgb till a good block
+ * is found for blk
+ */
+
+ if (nand->lgb < blk)
+ sblk = nand->lgb;
+ else
+ /* this is when lgb = 0 */
+ sblk = blk;
+
+
+ lgb = nand->lgb;
+
+ /* loop from blk to find a good block */
+ while (1) {
+ while (lgb <= sblk) {
+ uint32_t gb = 0;
+
+ ret = isgoodblock(lgb, &gb, nand);
+ if (ret != 0)
+ return ret;
+
+ /* special case block 0 is good then set this flag */
+ if (lgb == 0 && gb == GOOD_BLK)
+ nand->bzero_good = 1;
+
+ if (gb == BAD_BLK) {
+ if (idx >= BBT_SIZE) {
+ ERROR("NAND BBT Table full\n");
+ return -1;
+ }
+ *updated = 1;
+ nand->bbt[idx] = lgb;
+ idx++;
+ blk++;
+ sblk++;
+ if (idx > nand->bbt_max)
+ nand->bbt_max = idx;
+ }
+ lgb++;
+ }
+ /* the access block found */
+ if (sblk == blk) {
+ /* when good block found update lgb */
+ nand->lgb = blk;
+ break;
+ }
+ sblk++;
+ }
+
+ return 0;
+}
+
+static size_t ifc_nand_read(int lba, uintptr_t buf, size_t size)
+{
+ int ret;
+ uint32_t page_size;
+ uint32_t src_addr;
+ struct nand_info *nand = &nand_drv_data;
+
+ page_size = nand_get_page_size(nand);
+ src_addr = lba * page_size;
+ ret = nand_read(nand, src_addr, buf, size);
+ return ret ? 0 : size;
+}
+
+static struct io_block_dev_spec ifc_nand_spec = {
+ .buffer = {
+ .offset = 0,
+ .length = 0,
+ },
+ .ops = {
+ .read = ifc_nand_read,
+ },
+ /*
+ * Default block size assumed as 2K
+ * Would be updated based on actual size
+ */
+ .block_size = UL(2048),
+};
+
+int ifc_nand_init(uintptr_t *block_dev_spec,
+ uintptr_t ifc_region_addr,
+ uintptr_t ifc_register_addr,
+ size_t ifc_sram_size,
+ uintptr_t ifc_nand_blk_offset,
+ size_t ifc_nand_blk_size)
+{
+ struct nand_info *nand = NULL;
+ int ret;
+
+ nand = &nand_drv_data;
+ memset(nand, 0, sizeof(struct nand_info));
+
+ nand->ifc_region_addr = ifc_region_addr;
+ nand->ifc_register_addr = ifc_register_addr;
+
+ VERBOSE("nand_init\n");
+ ret = nand_init(nand);
+ if (ret) {
+ ERROR("nand init failed\n");
+ return ret;
+ }
+
+ ifc_nand_spec.buffer.offset = ifc_nand_blk_offset;
+ ifc_nand_spec.buffer.length = ifc_nand_blk_size;
+
+ ifc_nand_spec.block_size = nand_get_page_size(nand);
+
+ VERBOSE("Page size is %ld\n", ifc_nand_spec.block_size);
+
+ *block_dev_spec = (uintptr_t)&ifc_nand_spec;
+
+ /* Adding NAND SRAM< Buffer in XLAT Table */
+ mmap_add_region(ifc_region_addr, ifc_region_addr,
+ ifc_sram_size, MT_DEVICE | MT_RW);
+
+ return 0;
+}
diff --git a/drivers/nxp/ifc/nand/ifc_nand.mk b/drivers/nxp/ifc/nand/ifc_nand.mk
new file mode 100644
index 0000000..890fd23
--- /dev/null
+++ b/drivers/nxp/ifc/nand/ifc_nand.mk
@@ -0,0 +1,29 @@
+#
+# Copyright 2022 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${NAND_ADDED},)
+
+NAND_ADDED := 1
+
+NAND_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/ifc/nand
+
+NAND_SOURCES := $(NAND_DRIVERS_PATH)/ifc_nand.c \
+ drivers/io/io_block.c
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/ifc
+
+ifeq (${BL_COMM_IFC_NAND_NEEDED},yes)
+BL_COMMON_SOURCES += ${NAND_SOURCES}
+else
+ifeq (${BL2_IFC_NAND_NEEDED},yes)
+BL2_SOURCES += ${NAND_SOURCES}
+endif
+ifeq (${BL31_IFC_NAND_NEEDED},yes)
+BL31_SOURCES += ${NAND_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/nxp/ifc/nor/ifc_nor.c b/drivers/nxp/ifc/nor/ifc_nor.c
new file mode 100644
index 0000000..24fc308
--- /dev/null
+++ b/drivers/nxp/ifc/nor/ifc_nor.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+int ifc_nor_init(uintptr_t flash_addr, size_t flash_size)
+{
+ /* Adding NOR Memory Map in XLAT Table */
+ mmap_add_region(flash_addr, flash_addr, flash_size, MT_MEMORY | MT_RW);
+
+ return 0;
+}
diff --git a/drivers/nxp/ifc/nor/ifc_nor.mk b/drivers/nxp/ifc/nor/ifc_nor.mk
new file mode 100644
index 0000000..0022a81
--- /dev/null
+++ b/drivers/nxp/ifc/nor/ifc_nor.mk
@@ -0,0 +1,28 @@
+#
+# Copyright 2020-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${NOR_ADDED},)
+
+NOR_ADDED := 1
+
+NOR_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/ifc/nor
+
+NOR_SOURCES := $(NOR_DRIVERS_PATH)/ifc_nor.c
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/ifc
+
+ifeq (${BL_COMM_IFC_NOR_NEEDED},yes)
+BL_COMMON_SOURCES += ${NOR_SOURCES}
+else
+ifeq (${BL2_IFC_NOR_NEEDED},yes)
+BL2_SOURCES += ${NOR_SOURCES}
+endif
+ifeq (${BL31_IFC_NOR_NEEDED},yes)
+BL31_SOURCES += ${NOR_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/nxp/tzc/plat_tzc380.c b/drivers/nxp/tzc/plat_tzc380.c
new file mode 100644
index 0000000..13cf3b9
--- /dev/null
+++ b/drivers/nxp/tzc/plat_tzc380.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <plat_tzc380.h>
+
+#pragma weak populate_tzc380_reg_list
+
+#ifdef DEFAULT_TZASC_CONFIG
+/*
+ * Typical Memory map of DRAM0
+ * |-----------NXP_NS_DRAM_ADDR ( = NXP_DRAM0_ADDR)----------|
+ * | |
+ * | |
+ * | Non-SECURE REGION |
+ * | |
+ * | |
+ * | |
+ * |------- (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE - 1) -------|
+ * |-----------------NXP_SECURE_DRAM_ADDR--------------------|
+ * | |
+ * | |
+ * | |
+ * | SECURE REGION (= 64MB) |
+ * | |
+ * | |
+ * | |
+ * |--- (NXP_SECURE_DRAM_ADDR + NXP_SECURE_DRAM_SIZE - 1)----|
+ * |-----------------NXP_SP_SHRD_DRAM_ADDR-------------------|
+ * | |
+ * | Secure EL1 Payload SHARED REGION (= 2MB) |
+ * | |
+ * |-----------(NXP_DRAM0_ADDR + NXP_DRAM0_SIZE - 1)---------|
+ *
+ *
+ *
+ * Typical Memory map of DRAM1
+ * |---------------------NXP_DRAM1_ADDR----------------------|
+ * | |
+ * | |
+ * | Non-SECURE REGION |
+ * | |
+ * | |
+ * |---(NXP_DRAM1_ADDR + Dynamically calculated Size - 1) ---|
+ *
+ *
+ * Typical Memory map of DRAM2
+ * |---------------------NXP_DRAM2_ADDR----------------------|
+ * | |
+ * | |
+ * | Non-SECURE REGION |
+ * | |
+ * | |
+ * |---(NXP_DRAM2_ADDR + Dynamically calculated Size - 1) ---|
+ */
+
+/*****************************************************************************
+ * This function sets up access permissions on memory regions
+ *
+ * Input:
+ * tzc380_reg_list : TZC380 Region List
+ * dram_idx : DRAM index
+ * list_idx : TZC380 Region List Index
+ * dram_start_addr : Start address of DRAM at dram_idx.
+ * dram_size : Size of DRAM at dram_idx.
+ * secure_dram_sz : Secure DRAM Size
+ * shrd_dram_sz : Shared DRAM Size
+ *
+ * Out:
+ * list_idx : last populated index + 1
+ *
+ ****************************************************************************/
+int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
+ int dram_idx, int list_idx,
+ uint64_t dram_start_addr,
+ uint64_t dram_size,
+ uint32_t secure_dram_sz,
+ uint32_t shrd_dram_sz)
+{
+ /* Region 0: Default region marked as Non-Secure */
+ if (list_idx == 0) {
+ tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_NS_RW;
+ tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE;
+ tzc380_reg_list[list_idx].addr = UL(0x0);
+ tzc380_reg_list[list_idx].size = 0x0;
+ tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
+ list_idx++;
+ }
+ /* Continue with list entries for index > 0 */
+ if (dram_idx == 0) {
+ /* TZC Region 1 on DRAM0 for Secure Memory*/
+ tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
+ tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
+ tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size;
+ tzc380_reg_list[list_idx].size = secure_dram_sz;
+ tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
+ list_idx++;
+
+ /* TZC Region 2 on DRAM0 for Shared Memory*/
+ tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
+ tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
+ tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz;
+ tzc380_reg_list[list_idx].size = shrd_dram_sz;
+ tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
+ list_idx++;
+
+ }
+
+ return list_idx;
+}
+#else
+int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
+ int dram_idx, int list_idx,
+ uint64_t dram_start_addr,
+ uint64_t dram_size,
+ uint32_t secure_dram_sz,
+ uint32_t shrd_dram_sz)
+{
+ ERROR("tzc380_reg_list used is not a default list\n");
+ ERROR("%s needs to be over-written.\n", __func__);
+ return 0;
+}
+#endif /* DEFAULT_TZASC_CONFIG */
+
+
+void mem_access_setup(uintptr_t base, uint32_t total_regions,
+ struct tzc380_reg *tzc380_reg_list)
+{
+ uint32_t indx = 0;
+ unsigned int attr_value;
+
+ VERBOSE("Configuring TrustZone Controller tzc380\n");
+
+ tzc380_init(base);
+
+ tzc380_set_action(TZC_ACTION_NONE);
+
+ for (indx = 0; indx < total_regions; indx++) {
+ attr_value = tzc380_reg_list[indx].secure |
+ TZC_ATTR_SUBREG_DIS(tzc380_reg_list[indx].sub_mask) |
+ TZC_ATTR_REGION_SIZE(tzc380_reg_list[indx].size) |
+ tzc380_reg_list[indx].enabled;
+
+ tzc380_configure_region(indx, tzc380_reg_list[indx].addr,
+ attr_value);
+ }
+
+ tzc380_set_action(TZC_ACTION_ERR);
+}
diff --git a/drivers/nxp/tzc/tzc.mk b/drivers/nxp/tzc/tzc.mk
index 3fba28f..4418bfc 100644
--- a/drivers/nxp/tzc/tzc.mk
+++ b/drivers/nxp/tzc/tzc.mk
@@ -13,11 +13,18 @@
ifeq ($(TZC_ID), TZC400)
TZASC_SOURCES += drivers/arm/tzc/tzc400.c\
$(PLAT_DRIVERS_PATH)/tzc/plat_tzc400.c
-else ifeq ($(TZC_ID), NONE)
+else
+ifeq ($(TZC_ID), TZC380)
+TZASC_SOURCES += drivers/arm/tzc/tzc380.c\
+ $(PLAT_DRIVERS_PATH)/tzc/plat_tzc380.c
+else
+ifeq ($(TZC_ID), NONE)
$(info -> No TZC present on platform)
else
$(error -> TZC type not set!)
endif
+endif
+endif
ifeq (${BL_COMM_TZASC_NEEDED},yes)
BL_COMMON_SOURCES += ${TZASC_SOURCES}
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 684ab1a..3227f1c 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -9,10 +9,6 @@
#include <stdint.h>
#include <stdio.h>
-#include <libfdt.h>
-
-#include <platform_def.h>
-
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
@@ -27,8 +23,11 @@
#include <lib/mmio.h>
#include <lib/spinlock.h>
#include <lib/utils_def.h>
+#include <libfdt.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
+
#define MAX_HSI_HZ 64000000
#define USB_PHY_48_MHZ 48000000
@@ -699,7 +698,7 @@
}
}
- ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id);
+ ERROR("%s: clk id %lu not found\n", __func__, id);
return -EINVAL;
}
@@ -1114,7 +1113,7 @@
i = stm32mp1_clk_get_gated_id(id);
if (i < 0) {
- ERROR("Clock %d can't be enabled\n", (uint32_t)id);
+ ERROR("Clock %lu can't be enabled\n", id);
panic();
}
@@ -1142,7 +1141,7 @@
i = stm32mp1_clk_get_gated_id(id);
if (i < 0) {
- ERROR("Clock %d can't be disabled\n", (uint32_t)id);
+ ERROR("Clock %lu can't be disabled\n", id);
panic();
}
@@ -1351,6 +1350,13 @@
if (css) {
mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
}
+
+#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
+ if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) &&
+ (!(digbyp || bypass))) {
+ panic();
+ }
+#endif
}
static void stm32mp1_csi_set(bool enable)
@@ -1772,15 +1778,50 @@
mmio_clrsetbits_32(address, mask, value);
}
+static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg,
+ uint32_t *fracv, uint32_t *csg,
+ bool *csg_set)
+{
+ void *fdt;
+ int ret;
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB,
+ pllcfg);
+ if (ret < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
+
+ ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB,
+ csg);
+
+ *csg_set = (ret == 0);
+
+ if (ret == -FDT_ERR_NOTFOUND) {
+ ret = 0;
+ }
+
+ return ret;
+}
+
int stm32mp1_clk_init(void)
{
uintptr_t rcc_base = stm32mp_rcc_base();
+ uint32_t pllfracv[_PLL_NB];
+ uint32_t pllcsg[_PLL_NB][PLLCSG_NB];
unsigned int clksrc[CLKSRC_NB];
unsigned int clkdiv[CLKDIV_NB];
unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
int plloff[_PLL_NB];
int ret, len;
enum stm32mp1_pll_id i;
+ bool pllcsg_set[_PLL_NB];
+ bool pllcfg_valid[_PLL_NB];
bool lse_css = false;
bool pll3_preserve = false;
bool pll4_preserve = false;
@@ -1817,14 +1858,16 @@
snprintf(name, sizeof(name), "st,pll@%d", i);
plloff[i] = fdt_rcc_subnode_offset(name);
- if (!fdt_check_node(plloff[i])) {
+ pllcfg_valid[i] = fdt_check_node(plloff[i]);
+ if (!pllcfg_valid[i]) {
continue;
}
- ret = fdt_read_uint32_array(fdt, plloff[i], "cfg",
- (int)PLLCFG_NB, pllcfg[i]);
- if (ret < 0) {
- return -FDT_ERR_NOTFOUND;
+ ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i],
+ &pllfracv[i], pllcsg[i],
+ &pllcsg_set[i]);
+ if (ret != 0) {
+ return ret;
}
}
@@ -1839,22 +1882,24 @@
stm32mp1_lsi_set(true);
}
if (stm32mp1_osc[_LSE] != 0U) {
+ const char *name = stm32mp_osc_node_label[_LSE];
bool bypass, digbyp;
uint32_t lsedrv;
- bypass = fdt_osc_read_bool(_LSE, "st,bypass");
- digbyp = fdt_osc_read_bool(_LSE, "st,digbypass");
- lse_css = fdt_osc_read_bool(_LSE, "st,css");
- lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive",
+ bypass = fdt_clk_read_bool(name, "st,bypass");
+ digbyp = fdt_clk_read_bool(name, "st,digbypass");
+ lse_css = fdt_clk_read_bool(name, "st,css");
+ lsedrv = fdt_clk_read_uint32_default(name, "st,drive",
LSEDRV_MEDIUM_HIGH);
stm32mp1_lse_enable(bypass, digbyp, lsedrv);
}
if (stm32mp1_osc[_HSE] != 0U) {
+ const char *name = stm32mp_osc_node_label[_HSE];
bool bypass, digbyp, css;
- bypass = fdt_osc_read_bool(_HSE, "st,bypass");
- digbyp = fdt_osc_read_bool(_HSE, "st,digbypass");
- css = fdt_osc_read_bool(_HSE, "st,css");
+ bypass = fdt_clk_read_bool(name, "st,bypass");
+ digbyp = fdt_clk_read_bool(name, "st,digbypass");
+ css = fdt_clk_read_bool(name, "st,css");
stm32mp1_hse_enable(bypass, digbyp, css);
}
/*
@@ -1976,15 +2021,12 @@
/* Configure and start PLLs */
for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
- uint32_t fracv;
- uint32_t csg[PLLCSG_NB];
-
if (((i == _PLL3) && pll3_preserve) ||
((i == _PLL4) && pll4_preserve && !pll4_bootrom)) {
continue;
}
- if (!fdt_check_node(plloff[i])) {
+ if (!pllcfg_valid[i]) {
continue;
}
@@ -1994,25 +2036,20 @@
continue;
}
- fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0);
-
- ret = stm32mp1_pll_config(i, pllcfg[i], fracv);
+ ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]);
if (ret != 0) {
return ret;
}
- ret = fdt_read_uint32_array(fdt, plloff[i], "csg",
- (uint32_t)PLLCSG_NB, csg);
- if (ret == 0) {
- stm32mp1_pll_csg(i, csg);
- } else if (ret != -FDT_ERR_NOTFOUND) {
- return ret;
+
+ if (pllcsg_set[i]) {
+ stm32mp1_pll_csg(i, pllcsg[i]);
}
stm32mp1_pll_start(i);
}
/* Wait and start PLLs ouptut when ready */
for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
- if (!fdt_check_node(plloff[i])) {
+ if (!pllcfg_valid[i]) {
continue;
}
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index c83b8ad..5ba64fd 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -1,19 +1,18 @@
/*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
-#include <libfdt.h>
-
-#include <platform_def.h>
-
#include <common/fdt_wrappers.h>
#include <drivers/clk.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
+#include <libfdt.h>
+
+#include <platform_def.h>
#define DT_UART_COMPAT "st,stm32h7-uart"
/*
@@ -45,7 +44,8 @@
return ret;
}
- if (strncmp(cchar, name, (size_t)ret) == 0) {
+ if ((strncmp(cchar, name, (size_t)ret) == 0) &&
+ (fdt_get_status(subnode) != DT_DISABLED)) {
const fdt32_t *cuint;
cuint = fdt_getprop(fdt, subnode, "clock-frequency",
@@ -67,11 +67,11 @@
/*
* Check the presence of an oscillator property from its id.
- * @param osc_id: oscillator ID
+ * @param node_label: clock node name
* @param prop_name: property name
* @return: true/false regarding search result.
*/
-bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
+bool fdt_clk_read_bool(const char *node_label, const char *prop_name)
{
int node, subnode;
void *fdt;
@@ -80,10 +80,6 @@
return false;
}
- if (osc_id >= NB_OSC) {
- return false;
- }
-
node = fdt_path_offset(fdt, "/clocks");
if (node < 0) {
return false;
@@ -98,8 +94,7 @@
return false;
}
- if (strncmp(cchar, stm32mp_osc_node_label[osc_id],
- (size_t)ret) != 0) {
+ if (strncmp(cchar, node_label, (size_t)ret) != 0) {
continue;
}
@@ -112,13 +107,13 @@
}
/*
- * Get the value of a oscillator property from its ID.
- * @param osc_id: oscillator ID
+ * Get the value of a oscillator property from its name.
+ * @param node_label: oscillator name
* @param prop_name: property name
* @param dflt_value: default value
* @return oscillator value on success, default value if property not found.
*/
-uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
+uint32_t fdt_clk_read_uint32_default(const char *node_label,
const char *prop_name, uint32_t dflt_value)
{
int node, subnode;
@@ -128,10 +123,6 @@
return dflt_value;
}
- if (osc_id >= NB_OSC) {
- return dflt_value;
- }
-
node = fdt_path_offset(fdt, "/clocks");
if (node < 0) {
return dflt_value;
@@ -146,8 +137,7 @@
return dflt_value;
}
- if (strncmp(cchar, stm32mp_osc_node_label[osc_id],
- (size_t)ret) != 0) {
+ if (strncmp(cchar, node_label, (size_t)ret) != 0) {
continue;
}
diff --git a/fdts/tc.dts b/fdts/tc.dts
index 13c9e16..6e119ce 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -476,4 +476,48 @@
};
};
+ ete0 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU0>;
+ };
+
+ ete1 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU1>;
+ };
+
+ ete2 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU2>;
+ };
+
+ ete3 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU3>;
+ };
+
+ ete4 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU4>;
+ };
+
+ ete5 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU5>;
+ };
+
+ ete6 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU6>;
+ };
+
+ ete7 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU7>;
+ };
+
+ trbe0 {
+ compatible = "arm,trace-buffer-extension";
+ interrupts = <1 2 4>;
+ };
};
diff --git a/include/drivers/arm/tzc380.h b/include/drivers/arm/tzc380.h
index a8098a2..9bd5f21 100644
--- a/include/drivers/arm/tzc380.h
+++ b/include/drivers/arm/tzc380.h
@@ -121,6 +121,11 @@
#define TZC_REGION_SIZE_8E U(0x3e)
#define TZC_REGION_SIZE_16E U(0x3f)
+#define TZC_SUBREGION_DIS_SHIFT 0x8
+#define TZC_SUBREGION_DIS_MASK U(0xff)
+#define TZC_ATTR_SUBREG_DIS(s) (((s) & TZC_SUBREGION_DIS_MASK) \
+ << TZC_SUBREGION_DIS_SHIFT)
+
#define TZC_REGION_SIZE_SHIFT 0x1
#define TZC_REGION_SIZE_MASK U(0x7e)
#define TZC_ATTR_REGION_SIZE(s) ((s) << TZC_REGION_SIZE_SHIFT)
diff --git a/include/drivers/auth/auth_mod.h b/include/drivers/auth/auth_mod.h
index d1fd52c..94537f6 100644
--- a/include/drivers/auth/auth_mod.h
+++ b/include/drivers/auth/auth_mod.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,6 @@
#ifndef AUTH_MOD_H
#define AUTH_MOD_H
-#if TRUSTED_BOARD_BOOT
-
#include <common/tbbr/cot_def.h>
#include <common/tbbr/tbbr_img_def.h>
#include <drivers/auth/auth_common.h>
@@ -46,7 +44,13 @@
#endif /* COT_DESC_IN_DTB && !IMAGE_BL1 */
/* Public functions */
+#if TRUSTED_BOARD_BOOT
void auth_mod_init(void);
+#else
+static inline void auth_mod_init(void)
+{
+}
+#endif /* TRUSTED_BOARD_BOOT */
int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id);
int auth_mod_verify_img(unsigned int img_id,
void *img_ptr,
@@ -85,6 +89,4 @@
#endif
-#endif /* TRUSTED_BOARD_BOOT */
-
#endif /* AUTH_MOD_H */
diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h
index cdcf504..73b2b99 100644
--- a/include/drivers/auth/crypto_mod.h
+++ b/include/drivers/auth/crypto_mod.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -76,7 +76,14 @@
} crypto_lib_desc_t;
/* Public functions */
+#if CRYPTO_SUPPORT
void crypto_mod_init(void);
+#else
+static inline void crypto_mod_init(void)
+{
+}
+#endif /* CRYPTO_SUPPORT */
+
int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len,
void *sig_ptr, unsigned int sig_len,
void *sig_alg_ptr, unsigned int sig_alg_len,
@@ -93,7 +100,9 @@
int crypto_mod_calc_hash(enum crypto_md_algo alg, void *data_ptr,
unsigned int data_len,
unsigned char output[CRYPTO_MD_MAX_SIZE]);
+#endif /* MEASURED_BOOT */
+#if MEASURED_BOOT && TRUSTED_BOARD_BOOT
/* Macro to register a cryptographic library */
#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \
_calc_hash, _auth_decrypt) \
@@ -105,7 +114,7 @@
.calc_hash = _calc_hash, \
.auth_decrypt = _auth_decrypt \
}
-#else
+#elif TRUSTED_BOARD_BOOT
#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \
_auth_decrypt) \
const crypto_lib_desc_t crypto_lib_desc = { \
@@ -115,7 +124,14 @@
.verify_hash = _verify_hash, \
.auth_decrypt = _auth_decrypt \
}
+#elif MEASURED_BOOT
+#define REGISTER_CRYPTO_LIB(_name, _init, _calc_hash) \
+ const crypto_lib_desc_t crypto_lib_desc = { \
+ .name = _name, \
+ .init = _init, \
+ .calc_hash = _calc_hash, \
+ }
-#endif /* MEASURED_BOOT */
+#endif /* MEASURED_BOOT && TRUSTED_BOARD_BOOT */
extern const crypto_lib_desc_t crypto_lib_desc;
diff --git a/include/drivers/nxp/csu/csu.h b/include/drivers/nxp/csu/csu.h
index 3a43e45..83f1834 100644
--- a/include/drivers/nxp/csu/csu.h
+++ b/include/drivers/nxp/csu/csu.h
@@ -9,6 +9,8 @@
#define CSU_H
#define CSU_SEC_ACCESS_REG_OFFSET (0x0021CU)
+/* Bit mask */
+#define TZASC_BYPASS_MUX_DISABLE (0x4U)
/* Macros defining access permissions to configure
* the regions controlled by Central Security Unit.
diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h
index 1e56729..882ba5a 100644
--- a/include/drivers/nxp/dcfg/dcfg_lsch2.h
+++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h
@@ -11,6 +11,8 @@
/* dcfg block register offsets and bitfields */
#define DCFG_PORSR1_OFFSET 0x00
#define DCFG_DEVDISR1_OFFSET 0x070
+#define DCFG_DEVDISR2_OFFSET 0x074
+#define DCFG_DEVDISR3_OFFSET 0x078
#define DCFG_DEVDISR4_OFFSET 0x07C
#define DCFG_DEVDISR5_OFFSET 0x080
#define DCFG_COREDISR_OFFSET 0x094
@@ -29,6 +31,10 @@
#define DCFG_RSTRQSR1_OFFSET 0x0C8
#define DCFG_RSTRQMR1_OFFSET 0x0C0
+/* PORSR1 bit mask */
+#define PORSR1_RCW_MASK 0xff800000
+#define PORSR1_RCW_SHIFT 23
+
/* DCFG DCSR Macros */
#define DCFG_DCSR_PORCR1_OFFSET 0x0
@@ -43,6 +49,8 @@
#define SVR_MAJ_VER_MASK 0xF0
#define SVR_MAJ_VER_SHIFT 4
#define SVR_MIN_VER_MASK 0xF
+#define SVR_MINOR_VER_0 0x00
+#define SVR_MINOR_VER_1 0x01
#define DISR5_DDRC1_MASK 0x1
#define DISR5_OCRAM_MASK 0x40
diff --git a/include/drivers/nxp/dcfg/scfg.h b/include/drivers/nxp/dcfg/scfg.h
index ef6ed6b..8067de1 100644
--- a/include/drivers/nxp/dcfg/scfg.h
+++ b/include/drivers/nxp/dcfg/scfg.h
@@ -30,7 +30,13 @@
/* SCFG bit fields */
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
-#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
+#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
+
+/* GIC Address Align Register */
+#define SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK 0x80000000
+#define SCFG_GIC400_ADDR_ALIGN_4KMODE_EN 0x80000000
+#define SCFG_GIC400_ADDR_ALIGN_4KMODE_DIS 0x0
+
#endif /* CONFIG_CHASSIS_2 */
#ifndef __ASSEMBLER__
diff --git a/include/drivers/nxp/ifc/ifc_nand.h b/include/drivers/nxp/ifc/ifc_nand.h
new file mode 100644
index 0000000..dbcd762
--- /dev/null
+++ b/include/drivers/nxp/ifc/ifc_nand.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IFC_NAND_H
+#define IFC_NAND_H
+
+#define NXP_IFC_SRAM_BUFFER_SIZE UL(0x100000) /* 1M */
+
+int ifc_nand_init(uintptr_t *block_dev_spec,
+ uintptr_t ifc_region_addr,
+ uintptr_t ifc_register_addr,
+ size_t ifc_sram_size,
+ uintptr_t ifc_nand_blk_offset,
+ size_t ifc_nand_blk_size);
+
+#endif /*IFC_NAND_H*/
diff --git a/include/drivers/nxp/ifc/ifc_nor.h b/include/drivers/nxp/ifc/ifc_nor.h
new file mode 100644
index 0000000..ee14460
--- /dev/null
+++ b/include/drivers/nxp/ifc/ifc_nor.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef IFC_NOR_H
+#define IFC_NOR_H
+
+
+int ifc_nor_init(uintptr_t flash_addr, size_t flash_size);
+
+#endif /*IFC_NOR_H*/
diff --git a/include/drivers/nxp/tzc/plat_tzc380.h b/include/drivers/nxp/tzc/plat_tzc380.h
new file mode 100644
index 0000000..08d2148
--- /dev/null
+++ b/include/drivers/nxp/tzc/plat_tzc380.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !defined(PLAT_TZC380_H) && defined(IMAGE_BL2)
+#define PLAT_TZC380_H
+
+#include <tzc380.h>
+
+/* Number of DRAM regions to be configured
+ * for the platform can be over-written.
+ *
+ * Array tzc400_reg_list too, needs be over-written
+ * if there is any changes to default DRAM region
+ * configuration.
+ */
+#ifndef MAX_NUM_TZC_REGION
+/* 3 regions:
+ * Region 0(default),
+ * Region 1 (DRAM0, Secure Memory),
+ * Region 2 (DRAM0, Shared memory)
+ */
+#define MAX_NUM_TZC_REGION 3
+#define DEFAULT_TZASC_CONFIG 1
+#endif
+
+struct tzc380_reg {
+ unsigned int secure;
+ unsigned int enabled;
+ uint64_t addr;
+ uint64_t size;
+ unsigned int sub_mask;
+};
+
+void mem_access_setup(uintptr_t base, uint32_t total_regions,
+ struct tzc380_reg *tzc380_reg_list);
+
+int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
+ int dram_idx, int list_idx,
+ uint64_t dram_start_addr,
+ uint64_t dram_size,
+ uint32_t secure_dram_sz,
+ uint32_t shrd_dram_sz);
+
+#endif /* PLAT_TZC380_H */
diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h
index a282035..4876213 100644
--- a/include/drivers/st/stm32mp_clkfunc.h
+++ b/include/drivers/st/stm32mp_clkfunc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,8 +14,8 @@
#include <platform_def.h>
int fdt_osc_read_freq(const char *name, uint32_t *freq);
-bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name);
-uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
+bool fdt_clk_read_bool(const char *node_label, const char *prop_name);
+uint32_t fdt_clk_read_uint32_default(const char *node_label,
const char *prop_name,
uint32_t dflt_value);
diff --git a/package-lock.json b/package-lock.json
index 1d95ac9..469c5f5 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -1,22 +1,26 @@
{
"name": "trusted-firmware-a",
- "version": "2.5.0",
+ "version": "2.6.0",
"lockfileVersion": 2,
"requires": true,
"packages": {
"": {
"name": "trusted-firmware-a",
- "version": "2.5.0",
+ "version": "2.6.0",
"hasInstallScript": true,
"license": "BSD-3-Clause",
"devDependencies": {
- "@commitlint/cli": "^14.1.0",
- "@commitlint/config-conventional": "^14.1.0",
+ "@commitlint/cli": "^16.1.0",
+ "@commitlint/config-conventional": "^16.0.0",
+ "@commitlint/cz-commitlint": "^16.1.0",
"commitizen": "^4.2.4",
"conventional-changelog-tf-a": "file:tools/conventional-changelog-tf-a",
- "cz-conventional-changelog": "^3.3.0",
"husky": "^7.0.4",
+ "js-yaml": "^4.1.0",
"standard-version": "^9.3.2"
+ },
+ "engines": {
+ "node": ">=16.0.0"
}
},
"node_modules/@babel/code-frame": {
@@ -108,16 +112,16 @@
}
},
"node_modules/@commitlint/cli": {
- "version": "14.1.0",
- "resolved": "https://registry.npmjs.org/@commitlint/cli/-/cli-14.1.0.tgz",
- "integrity": "sha512-Orq62jkl9qAGvjFqhehtAqjGY/duJ8hIRPPIHmGR2jIB96D4VTmazS3ZvqJz2Q9kKr61mLAk/171zm0FVzQCYA==",
+ "version": "16.1.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/cli/-/cli-16.1.0.tgz",
+ "integrity": "sha512-x5L1knvA3isRWBRVQx+Q6D45pA9139a2aZQYpxkljMG0dj4UHZkCnsYWpnGalxPxASI7nrI0KedKfS2YeQ55cQ==",
"dev": true,
"dependencies": {
- "@commitlint/format": "^14.1.0",
- "@commitlint/lint": "^14.1.0",
- "@commitlint/load": "^14.1.0",
- "@commitlint/read": "^14.0.0",
- "@commitlint/types": "^14.0.0",
+ "@commitlint/format": "^16.0.0",
+ "@commitlint/lint": "^16.0.0",
+ "@commitlint/load": "^16.1.0",
+ "@commitlint/read": "^16.0.0",
+ "@commitlint/types": "^16.0.0",
"lodash": "^4.17.19",
"resolve-from": "5.0.0",
"resolve-global": "1.0.0",
@@ -131,9 +135,9 @@
}
},
"node_modules/@commitlint/config-conventional": {
- "version": "14.1.0",
- "resolved": "https://registry.npmjs.org/@commitlint/config-conventional/-/config-conventional-14.1.0.tgz",
- "integrity": "sha512-JuhCqkEv8jyqmd54EpXPsQFpYc/8k7sfP1UziRdEvZSJUCLxz+8Pk4cNS0oF1BtjaWO7ITgXPlIZg47PyApGmg==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/config-conventional/-/config-conventional-16.0.0.tgz",
+ "integrity": "sha512-mN7J8KlKFn0kROd+q9PB01sfDx/8K/R25yITspL1No8PB4oj9M1p77xWjP80hPydqZG9OvQq+anXK3ZWeR7s3g==",
"dev": true,
"dependencies": {
"conventional-changelog-conventionalcommits": "^4.3.1"
@@ -142,13 +146,47 @@
"node": ">=v12"
}
},
+ "node_modules/@commitlint/config-validator": {
+ "version": "16.1.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/config-validator/-/config-validator-16.1.0.tgz",
+ "integrity": "sha512-2cHeZPNTuf1JWbMqyA46MkExor5HMSgv8JrdmzEakUbJHUreh35/wN00FJf57qGs134exQW2thiSQ1IJUsVx2Q==",
+ "dev": true,
+ "dependencies": {
+ "@commitlint/types": "^16.0.0",
+ "ajv": "^6.12.6"
+ },
+ "engines": {
+ "node": ">=v12"
+ }
+ },
+ "node_modules/@commitlint/cz-commitlint": {
+ "version": "16.1.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/cz-commitlint/-/cz-commitlint-16.1.0.tgz",
+ "integrity": "sha512-TThglfXEBW8TZ99dvaeto1c6hU25ONqL9qkENle2+1OFI64NgbICjLsJq7SVzJd4Jn/yZDp4xNqoV53WJPJ9aA==",
+ "dev": true,
+ "dependencies": {
+ "@commitlint/ensure": "^16.0.0",
+ "@commitlint/load": "^16.1.0",
+ "@commitlint/types": "^16.0.0",
+ "chalk": "^4.1.0",
+ "lodash": "^4.17.21",
+ "word-wrap": "^1.2.3"
+ },
+ "engines": {
+ "node": ">= 10"
+ },
+ "peerDependencies": {
+ "commitizen": "^4.0.3",
+ "inquirer": "^8.0.0"
+ }
+ },
"node_modules/@commitlint/ensure": {
- "version": "14.1.0",
- "resolved": "https://registry.npmjs.org/@commitlint/ensure/-/ensure-14.1.0.tgz",
- "integrity": "sha512-xrYvFdqVepT3XA1BmSh88eKbvYKtLuQu98QLfgxVmwS99Kj3yW0sT3D7jGvNsynbIx2dhbXofDyubf/DKkpFrQ==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/ensure/-/ensure-16.0.0.tgz",
+ "integrity": "sha512-WdMySU8DCTaq3JPf0tZFCKIUhqxaL54mjduNhu8v4D2AMUVIIQKYMGyvXn94k8begeW6iJkTf9cXBArayskE7Q==",
"dev": true,
"dependencies": {
- "@commitlint/types": "^14.0.0",
+ "@commitlint/types": "^16.0.0",
"lodash": "^4.17.19"
},
"engines": {
@@ -156,21 +194,21 @@
}
},
"node_modules/@commitlint/execute-rule": {
- "version": "14.0.0",
- "resolved": "https://registry.npmjs.org/@commitlint/execute-rule/-/execute-rule-14.0.0.tgz",
- "integrity": "sha512-Hh/HLpCBDlrD3Rx2x2pDBx6CU+OtVqGXh7mbFpNihAVx6B0zyZqm/vv0cdwdhfGW5OEn1BhCqHf1ZOvL/DwdWA==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/execute-rule/-/execute-rule-16.0.0.tgz",
+ "integrity": "sha512-8edcCibmBb386x5JTHSPHINwA5L0xPkHQFY8TAuDEt5QyRZY/o5DF8OPHSa5Hx2xJvGaxxuIz4UtAT6IiRDYkw==",
"dev": true,
"engines": {
"node": ">=v12"
}
},
"node_modules/@commitlint/format": {
- "version": "14.1.0",
- "resolved": "https://registry.npmjs.org/@commitlint/format/-/format-14.1.0.tgz",
- "integrity": "sha512-sF6engqqHjvxGctWRKjFs/HQeNowlpbVmmoP481b2UMQnVQnjjfXJvQsoLpaqFUvgc2sHM4L85F8BmAw+iHG1w==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/format/-/format-16.0.0.tgz",
+ "integrity": "sha512-9yp5NCquXL1jVMKL0ZkRwJf/UHdebvCcMvICuZV00NQGYSAL89O398nhqrqxlbjBhM5EZVq0VGcV5+7r3D4zAA==",
"dev": true,
"dependencies": {
- "@commitlint/types": "^14.0.0",
+ "@commitlint/types": "^16.0.0",
"chalk": "^4.0.0"
},
"engines": {
@@ -178,12 +216,12 @@
}
},
"node_modules/@commitlint/is-ignored": {
- "version": "14.0.0",
- "resolved": "https://registry.npmjs.org/@commitlint/is-ignored/-/is-ignored-14.0.0.tgz",
- "integrity": "sha512-nJltYjXTa+mk+6SPe35nOZCCvt3Gh5mbDz008KQ4OPcn1GX1NG+pEgz1Kx3agDp/pc+JGnsrr5GV00gygIoloA==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/is-ignored/-/is-ignored-16.0.0.tgz",
+ "integrity": "sha512-gmAQcwIGC/R/Lp0CEb2b5bfGC7MT5rPe09N8kOGjO/NcdNmfFSZMquwrvNJsq9hnAP0skRdHIsqwlkENkN4Lag==",
"dev": true,
"dependencies": {
- "@commitlint/types": "^14.0.0",
+ "@commitlint/types": "^16.0.0",
"semver": "7.3.5"
},
"engines": {
@@ -191,32 +229,33 @@
}
},
"node_modules/@commitlint/lint": {
- "version": "14.1.0",
- "resolved": "https://registry.npmjs.org/@commitlint/lint/-/lint-14.1.0.tgz",
- "integrity": "sha512-CApGJEOtWU/CcuPD8HkOR1jdUYpjKutGPaeby9nSFzJhwl/UQOjxc4Nd+2g2ygsMi5l3N4j2sWQYEgccpFC3lA==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/lint/-/lint-16.0.0.tgz",
+ "integrity": "sha512-HNl15bRC0h+pLzbMzQC3tM0j1aESXsLYhElqKnXcf5mnCBkBkHzu6WwJW8rZbfxX+YwJmNljN62cPhmdBo8x0A==",
"dev": true,
"dependencies": {
- "@commitlint/is-ignored": "^14.0.0",
- "@commitlint/parse": "^14.0.0",
- "@commitlint/rules": "^14.1.0",
- "@commitlint/types": "^14.0.0"
+ "@commitlint/is-ignored": "^16.0.0",
+ "@commitlint/parse": "^16.0.0",
+ "@commitlint/rules": "^16.0.0",
+ "@commitlint/types": "^16.0.0"
},
"engines": {
"node": ">=v12"
}
},
"node_modules/@commitlint/load": {
- "version": "14.1.0",
- "resolved": "https://registry.npmjs.org/@commitlint/load/-/load-14.1.0.tgz",
- "integrity": "sha512-p+HbgjhkqLsnxyjOUdEYHztHCp8n2oLVUJTmRPuP5FXLNevh6Gwmxf+NYC2J0sgD084aV2CFi3qu1W4yHWIknA==",
+ "version": "16.1.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/load/-/load-16.1.0.tgz",
+ "integrity": "sha512-MtlEhKjP8jAF85jjX4mw8DUUwCxKsCgAc865hhpnwxjrfBcmGP7Up2AFE/M3ZMGDmSl1X1TMybQk/zohj8Cqdg==",
"dev": true,
"dependencies": {
- "@commitlint/execute-rule": "^14.0.0",
- "@commitlint/resolve-extends": "^14.1.0",
- "@commitlint/types": "^14.0.0",
- "@endemolshinegroup/cosmiconfig-typescript-loader": "^3.0.2",
+ "@commitlint/config-validator": "^16.1.0",
+ "@commitlint/execute-rule": "^16.0.0",
+ "@commitlint/resolve-extends": "^16.1.0",
+ "@commitlint/types": "^16.0.0",
"chalk": "^4.0.0",
"cosmiconfig": "^7.0.0",
+ "cosmiconfig-typescript-loader": "^1.0.0",
"lodash": "^4.17.19",
"resolve-from": "^5.0.0",
"typescript": "^4.4.3"
@@ -226,21 +265,21 @@
}
},
"node_modules/@commitlint/message": {
- "version": "14.0.0",
- "resolved": "https://registry.npmjs.org/@commitlint/message/-/message-14.0.0.tgz",
- "integrity": "sha512-316Pum+bwDcZamOQw0DXSY17Dq9EjvL1zKdYIZqneu4lnXN6uFfi53Y/sP5crW6zlLdnuTHe1MnuewXPLHfH1Q==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/message/-/message-16.0.0.tgz",
+ "integrity": "sha512-CmK2074SH1Ws6kFMEKOKH/7hMekGVbOD6vb4alCOo2+33ZSLUIX8iNkDYyrw38Jwg6yWUhLjyQLUxREeV+QIUA==",
"dev": true,
"engines": {
"node": ">=v12"
}
},
"node_modules/@commitlint/parse": {
- "version": "14.0.0",
- "resolved": "https://registry.npmjs.org/@commitlint/parse/-/parse-14.0.0.tgz",
- "integrity": "sha512-49qkk0TcwdxJPZUX8MElEzMlRFIL/cg64P4pk8HotFEm2HYdbxxZp6v3cbVw5WOsnRA0frrs+NNoOcIT83ccMQ==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/parse/-/parse-16.0.0.tgz",
+ "integrity": "sha512-F9EjFlMw4MYgBEqoRrWZZKQBzdiJzPBI0qFDFqwUvfQsMmXEREZ242T4R5bFwLINWaALFLHEIa/FXEPa6QxCag==",
"dev": true,
"dependencies": {
- "@commitlint/types": "^14.0.0",
+ "@commitlint/types": "^16.0.0",
"conventional-changelog-angular": "^5.0.11",
"conventional-commits-parser": "^3.2.2"
},
@@ -249,13 +288,13 @@
}
},
"node_modules/@commitlint/read": {
- "version": "14.0.0",
- "resolved": "https://registry.npmjs.org/@commitlint/read/-/read-14.0.0.tgz",
- "integrity": "sha512-WXXcSLBqwXTqnEmB0lbU2TrayDJ2G3qI/lxy1ianVmpQol8p9BjodAA6bYxtYYHdQFVXUrIsclzFP/naWG+hlQ==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/read/-/read-16.0.0.tgz",
+ "integrity": "sha512-H4T2zsfmYQK9B+JtoQaCXWBHUhgIJyOzWZjSfuIV9Ce69/OgHoffNpLZPF2lX6yKuDrS1SQFhI/kUCjVc/e4ew==",
"dev": true,
"dependencies": {
- "@commitlint/top-level": "^14.0.0",
- "@commitlint/types": "^14.0.0",
+ "@commitlint/top-level": "^16.0.0",
+ "@commitlint/types": "^16.0.0",
"fs-extra": "^10.0.0",
"git-raw-commits": "^2.0.0"
},
@@ -264,11 +303,13 @@
}
},
"node_modules/@commitlint/resolve-extends": {
- "version": "14.1.0",
- "resolved": "https://registry.npmjs.org/@commitlint/resolve-extends/-/resolve-extends-14.1.0.tgz",
- "integrity": "sha512-ko80k6QB6E6/OvGNWy4u7gzzWyluDT3VDNL2kfZaDywsnrYntUKyT4Do97gQ7orttITzj2GRtk3KWClVz4rUUQ==",
+ "version": "16.1.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/resolve-extends/-/resolve-extends-16.1.0.tgz",
+ "integrity": "sha512-8182s6AFoUFX6+FT1PgQDt15nO2ogdR/EN8SYVAdhNXw1rLz8kT5saB/ICw567GuRAUgFTUMGCXy3ctMOXPEDg==",
"dev": true,
"dependencies": {
+ "@commitlint/config-validator": "^16.1.0",
+ "@commitlint/types": "^16.0.0",
"import-fresh": "^3.0.0",
"lodash": "^4.17.19",
"resolve-from": "^5.0.0",
@@ -279,15 +320,15 @@
}
},
"node_modules/@commitlint/rules": {
- "version": "14.1.0",
- "resolved": "https://registry.npmjs.org/@commitlint/rules/-/rules-14.1.0.tgz",
- "integrity": "sha512-6jmv414/1JzGzDI/DS+snAMhcL6roQKPdg0WB3kWTWN52EvWXBFm0HIMGt2H/FlRKxozwVXlQN60/1fNIl98xA==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/rules/-/rules-16.0.0.tgz",
+ "integrity": "sha512-AOl0y2SBTdJ1bvIv8nwHvQKRT/jC1xb09C5VZwzHoT8sE8F54KDeEzPCwHQFgUcWdGLyS10kkOTAH2MyA8EIlg==",
"dev": true,
"dependencies": {
- "@commitlint/ensure": "^14.1.0",
- "@commitlint/message": "^14.0.0",
- "@commitlint/to-lines": "^14.0.0",
- "@commitlint/types": "^14.0.0",
+ "@commitlint/ensure": "^16.0.0",
+ "@commitlint/message": "^16.0.0",
+ "@commitlint/to-lines": "^16.0.0",
+ "@commitlint/types": "^16.0.0",
"execa": "^5.0.0"
},
"engines": {
@@ -295,18 +336,18 @@
}
},
"node_modules/@commitlint/to-lines": {
- "version": "14.0.0",
- "resolved": "https://registry.npmjs.org/@commitlint/to-lines/-/to-lines-14.0.0.tgz",
- "integrity": "sha512-uIXk54oJDuYyLpI208s3+cGmJ323yvSJ9LB7yUDMWUeJi2LgRxE2EBZL995kLQdnoAsBBXcLq+VDyppg5bV/cg==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/to-lines/-/to-lines-16.0.0.tgz",
+ "integrity": "sha512-iN/qU38TCKU7uKOg6RXLpD49wNiuI0TqMqybHbjefUeP/Jmzxa8ishryj0uLyVdrAl1ZjGeD1ukXGMTtvqz8iA==",
"dev": true,
"engines": {
"node": ">=v12"
}
},
"node_modules/@commitlint/top-level": {
- "version": "14.0.0",
- "resolved": "https://registry.npmjs.org/@commitlint/top-level/-/top-level-14.0.0.tgz",
- "integrity": "sha512-MZDKZfWfl9g4KozgWBGTCrI2cXkMHnBFlhwvEfrAu5G8wd5aL1f2uWEUMnBMjUikmhVj99i1pzge4XFWHQ29wQ==",
+ "version": "16.0.0",
+ "resolved": "https://registry.npmjs.org/@commitlint/top-level/-/top-level-16.0.0.tgz",
+ "integrity": "sha512-/Jt6NLxyFkpjL5O0jxurZPCHURZAm7cQCqikgPCwqPAH0TLgwqdHjnYipl8J+AGnAMGDip4FNLoYrtgIpZGBYw==",
"dev": true,
"dependencies": {
"find-up": "^5.0.0"
@@ -316,9 +357,9 @@
}
},
"node_modules/@commitlint/types": {
- "version": "14.0.0",
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@@ -641,6 +877,24 @@
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@@ -3163,15 +3491,13 @@
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+ "resolved": "https://registry.npmjs.org/rxjs/-/rxjs-7.4.0.tgz",
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- },
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+ "tslib": "~2.1.0"
}
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@@ -3251,16 +3577,6 @@
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"dev": true,
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},
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+ "ts-node-cwd": "dist/bin-cwd.js",
"ts-node-script": "dist/bin-script.js",
"ts-node-transpile-only": "dist/bin-transpile.js",
"ts-script": "dist/bin-script-deprecated.js"
},
- "engines": {
- "node": ">=10.0.0"
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+ "@swc/wasm": ">=1.2.50",
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+ "peerDependenciesMeta": {
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- "dev": true
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@@ -3638,9 +3955,9 @@
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@@ -3672,6 +3989,15 @@
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"resolved": "https://registry.npmjs.org/util-deprecate/-/util-deprecate-1.0.2.tgz",
@@ -3688,6 +4014,16 @@
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@@ -3820,8 +4156,9 @@
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"dev": true,
+ "license": "BSD-3-Clause",
"dependencies": {
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@@ -3910,16 +4247,16 @@
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"dev": true,
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}
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@@ -4042,60 +4406,55 @@
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"resolved": "https://registry.npmjs.org/is-utf8/-/is-utf8-0.2.1.tgz",
@@ -5696,6 +6189,15 @@
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"dev": true
},
+ "js-yaml": {
+ "version": "4.1.0",
+ "resolved": "https://registry.npmjs.org/js-yaml/-/js-yaml-4.1.0.tgz",
+ "integrity": "sha512-wpxZs9NoxZaJESJGIZTyDEaYpl0FKSA+FB9aJiyemKhMwkxQg63h4T1KJgUGHpTqPDNRcmmYLugrRjJlBtWvRA==",
+ "dev": true,
+ "requires": {
+ "argparse": "^2.0.1"
+ }
+ },
"json-parse-better-errors": {
"version": "1.0.2",
"resolved": "https://registry.npmjs.org/json-parse-better-errors/-/json-parse-better-errors-1.0.2.tgz",
@@ -5708,6 +6210,12 @@
"integrity": "sha512-xyFwyhro/JEof6Ghe2iz2NcXoj2sloNsWr/XsERDK/oiPCfaNhl5ONfp+jQdAZRQQ0IJWNzH9zIZF7li91kh2w==",
"dev": true
},
+ "json-schema-traverse": {
+ "version": "0.4.1",
+ "resolved": "https://registry.npmjs.org/json-schema-traverse/-/json-schema-traverse-0.4.1.tgz",
+ "integrity": "sha512-xbbCH5dCYU5T8LcEhhuh7HJ88HXuW3qsI3Y0zOZFKfZEHcpWiHU/Jxzk629Brsab/mMiHQti9wMP+845RPe3Vg==",
+ "dev": true
+ },
"json-stringify-safe": {
"version": "5.0.1",
"resolved": "https://registry.npmjs.org/json-stringify-safe/-/json-stringify-safe-5.0.1.tgz",
@@ -5803,12 +6311,6 @@
"integrity": "sha512-v2kDEe57lecTulaDIuNTPy3Ry4gLGJ6Z1O3vE1krgXZNrsQ+LFTGHVxVjcXPs17LhbZVGedAJv8XZ1tvj5FvSg==",
"dev": true
},
- "lodash.get": {
- "version": "4.4.2",
- "resolved": "https://registry.npmjs.org/lodash.get/-/lodash.get-4.4.2.tgz",
- "integrity": "sha1-LRd/ZS+jHpObRDjVNBSZ36OCXpk=",
- "dev": true
- },
"lodash.ismatch": {
"version": "4.4.0",
"resolved": "https://registry.npmjs.org/lodash.ismatch/-/lodash.ismatch-4.4.0.tgz",
@@ -5821,6 +6323,17 @@
"integrity": "sha1-dx7Hg540c9nEzeKLGTlMNWL09tM=",
"dev": true
},
+ "log-symbols": {
+ "version": "4.1.0",
+ "resolved": "https://registry.npmjs.org/log-symbols/-/log-symbols-4.1.0.tgz",
+ "integrity": "sha512-8XPvpAA8uyhfteu8pIvQxpJZ7SYYdpUivZpGy6sFsBuKRY/7rQGavedeB8aK+Zkyq6upMFVL/9AW6vOYzfRyLg==",
+ "dev": true,
+ "peer": true,
+ "requires": {
+ "chalk": "^4.1.0",
+ "is-unicode-supported": "^0.1.0"
+ }
+ },
"longest": {
"version": "2.0.1",
"resolved": "https://registry.npmjs.org/longest/-/longest-2.0.1.tgz",
@@ -5890,9 +6403,9 @@
}
},
"mimic-fn": {
- "version": "1.2.0",
- "resolved": "https://registry.npmjs.org/mimic-fn/-/mimic-fn-1.2.0.tgz",
- "integrity": "sha512-jf84uxzwiuiIVKiOLpfYk7N46TSy8ubTonmneY9vrpHNAnp0QBt2BxWV9dO3/j+BoVAb+a5G6YDPW3M5HOdMWQ==",
+ "version": "2.1.0",
+ "resolved": "https://registry.npmjs.org/mimic-fn/-/mimic-fn-2.1.0.tgz",
+ "integrity": "sha512-OqbOk5oEQeAZ8WXWydlu9HJjz9WVdEIvamMCcXmuqUYjTknH/sqsWvhQ3vgwKFRR1HpjvNBKQ37nbJgYzGqGcg==",
"dev": true
},
"min-indent": {
@@ -5934,10 +6447,11 @@
"dev": true
},
"mute-stream": {
- "version": "0.0.7",
- "resolved": "https://registry.npmjs.org/mute-stream/-/mute-stream-0.0.7.tgz",
- "integrity": "sha1-MHXOk7whuPq0PhvE2n6BFe0ee6s=",
- "dev": true
+ "version": "0.0.8",
+ "resolved": "https://registry.npmjs.org/mute-stream/-/mute-stream-0.0.8.tgz",
+ "integrity": "sha512-nnbWWOkoWyUsTjKrhgD0dcz22mdkSnpYqbEjIm2nhwhuxlSkpywJmBo8h0ZqJdkp73mb90SssHkN4rsRaBAfAA==",
+ "dev": true,
+ "peer": true
},
"neo-async": {
"version": "2.6.2",
@@ -5982,12 +6496,30 @@
}
},
"onetime": {
- "version": "2.0.1",
- "resolved": "https://registry.npmjs.org/onetime/-/onetime-2.0.1.tgz",
- "integrity": "sha1-BnQoIw/WdEOyeUsiu6UotoZ5YtQ=",
+ "version": "5.1.2",
+ "resolved": "https://registry.npmjs.org/onetime/-/onetime-5.1.2.tgz",
+ "integrity": "sha512-kbpaSSGJTWdAY5KPVeMOKXSrPtr8C8C7wodJbcsd51jRnmD+GZu8Y0VoU6Dm5Z4vWr0Ig/1NKuWRKf7j5aaYSg==",
"dev": true,
"requires": {
- "mimic-fn": "^1.0.0"
+ "mimic-fn": "^2.1.0"
+ }
+ },
+ "ora": {
+ "version": "5.4.1",
+ "resolved": "https://registry.npmjs.org/ora/-/ora-5.4.1.tgz",
+ "integrity": "sha512-5b6Y85tPxZZ7QytO+BQzysW31HJku27cRIlkbAXaNx+BdcVi+LlRFmVXzeF6a7JCwJpyw5c4b+YSVImQIrBpuQ==",
+ "dev": true,
+ "peer": true,
+ "requires": {
+ "bl": "^4.1.0",
+ "chalk": "^4.1.0",
+ "cli-cursor": "^3.1.0",
+ "cli-spinners": "^2.5.0",
+ "is-interactive": "^1.0.0",
+ "is-unicode-supported": "^0.1.0",
+ "log-symbols": "^4.1.0",
+ "strip-ansi": "^6.0.0",
+ "wcwidth": "^1.0.1"
}
},
"os-tmpdir": {
@@ -6095,6 +6627,12 @@
"integrity": "sha512-3ouUOpQhtgrbOa17J7+uxOTpITYWaGP7/AhoR3+A+/1e9skrzelGi/dXzEYyvbxubEF6Wn2ypscTKiKJFFn1ag==",
"dev": true
},
+ "punycode": {
+ "version": "2.1.1",
+ "resolved": "https://registry.npmjs.org/punycode/-/punycode-2.1.1.tgz",
+ "integrity": "sha512-XRsRjdf+j5ml+y/6GKHPZbrF/8p2Yga0JPtdqTIY2Xe5ohJPD9saDJJLPvp9+NSBprVvevdXZybnj2cv8OEd0A==",
+ "dev": true
+ },
"q": {
"version": "1.5.1",
"resolved": "https://registry.npmjs.org/q/-/q-1.5.1.tgz",
@@ -6270,12 +6808,13 @@
}
},
"restore-cursor": {
- "version": "2.0.0",
- "resolved": "https://registry.npmjs.org/restore-cursor/-/restore-cursor-2.0.0.tgz",
- "integrity": "sha1-n37ih/gv0ybU/RYpI9YhKe7g368=",
+ "version": "3.1.0",
+ "resolved": "https://registry.npmjs.org/restore-cursor/-/restore-cursor-3.1.0.tgz",
+ "integrity": "sha512-l+sSefzHpj5qimhFSE5a8nufZYAM3sBSVMAPtYkmC+4EH2anSGaEMXSD0izRQbu9nfyQ9y5JrVmp7E8oZrUjvA==",
"dev": true,
+ "peer": true,
"requires": {
- "onetime": "^2.0.0",
+ "onetime": "^5.1.0",
"signal-exit": "^3.0.2"
}
},
@@ -6286,12 +6825,13 @@
"dev": true
},
"rxjs": {
- "version": "6.6.7",
- "resolved": "https://registry.npmjs.org/rxjs/-/rxjs-6.6.7.tgz",
- "integrity": "sha512-hTdwr+7yYNIT5n4AMYp85KA6yw2Va0FLa3Rguvbpa4W3I5xynaBZo41cM3XM+4Q6fRMj3sBYIR1VAmZMXYJvRQ==",
+ "version": "7.4.0",
+ "resolved": "https://registry.npmjs.org/rxjs/-/rxjs-7.4.0.tgz",
+ "integrity": "sha512-7SQDi7xeTMCJpqViXh8gL/lebcwlp3d831F05+9B44A4B0WfsEwUQHR64gsH1kvJ+Ep/J9K2+n1hVl1CsGN23w==",
"dev": true,
+ "peer": true,
"requires": {
- "tslib": "^1.9.0"
+ "tslib": "~2.1.0"
}
},
"safe-buffer": {
@@ -6342,16 +6882,6 @@
"integrity": "sha512-UjgapumWlbMhkBgzT7Ykc5YXUT46F0iKu8SGXq0bcwP5dz/h0Plj6enJqjz1Zbq2l5WaqYnrVbwWOWMyF3F47g==",
"dev": true
},
- "source-map-support": {
- "version": "0.5.20",
- "resolved": "https://registry.npmjs.org/source-map-support/-/source-map-support-0.5.20.tgz",
- "integrity": "sha512-n1lZZ8Ve4ksRqizaBQgxXDgKwttHDhyfQjA6YZZn8+AroHbsIz+JjwxQDxbp+7y5OYCI8t1Yk7etjD9CRd2hIw==",
- "dev": true,
- "requires": {
- "buffer-from": "^1.0.0",
- "source-map": "^0.6.0"
- }
- },
"spdx-correct": {
"version": "3.1.1",
"resolved": "https://registry.npmjs.org/spdx-correct/-/spdx-correct-3.1.1.tgz",
@@ -6460,15 +6990,6 @@
"integrity": "sha1-p9BVi9icQveV3UIyj3QIMcpTvCU=",
"dev": true
},
- "figures": {
- "version": "3.2.0",
- "resolved": "https://registry.npmjs.org/figures/-/figures-3.2.0.tgz",
- "integrity": "sha512-yaduQFRKLXYOGgEn6AZau90j3ggSOyiqXU0F9JZfeXYhNa+Jk4X+s45A2zg5jns87GAFa34BBm2kXw4XpNcbdg==",
- "dev": true,
- "requires": {
- "escape-string-regexp": "^1.0.5"
- }
- },
"has-flag": {
"version": "3.0.0",
"resolved": "https://registry.npmjs.org/has-flag/-/has-flag-3.0.0.tgz",
@@ -6618,24 +7139,31 @@
"dev": true
},
"ts-node": {
- "version": "9.1.1",
- "resolved": "https://registry.npmjs.org/ts-node/-/ts-node-9.1.1.tgz",
- "integrity": "sha512-hPlt7ZACERQGf03M253ytLY3dHbGNGrAq9qIHWUY9XHYl1z7wYngSr3OQ5xmui8o2AaxsONxIzjafLUiWBo1Fg==",
+ "version": "10.4.0",
+ "resolved": "https://registry.npmjs.org/ts-node/-/ts-node-10.4.0.tgz",
+ "integrity": "sha512-g0FlPvvCXSIO1JDF6S232P5jPYqBkRL9qly81ZgAOSU7rwI0stphCgd2kLiCrU9DjQCrJMWEqcNSjQL02s6d8A==",
"dev": true,
"requires": {
+ "@cspotcode/source-map-support": "0.7.0",
+ "@tsconfig/node10": "^1.0.7",
+ "@tsconfig/node12": "^1.0.7",
+ "@tsconfig/node14": "^1.0.0",
+ "@tsconfig/node16": "^1.0.2",
+ "acorn": "^8.4.1",
+ "acorn-walk": "^8.1.1",
"arg": "^4.1.0",
"create-require": "^1.1.0",
"diff": "^4.0.1",
"make-error": "^1.1.1",
- "source-map-support": "^0.5.17",
"yn": "3.1.1"
}
},
"tslib": {
- "version": "1.14.1",
- "resolved": "https://registry.npmjs.org/tslib/-/tslib-1.14.1.tgz",
- "integrity": "sha512-Xni35NKzjgMrwevysHTCArtLDpPvye8zV/0E4EyYn43P7/7qvQwPh9BGkHewbMulVntbigmcT7rdX3BNo9wRJg==",
- "dev": true
+ "version": "2.1.0",
+ "resolved": "https://registry.npmjs.org/tslib/-/tslib-2.1.0.tgz",
+ "integrity": "sha512-hcVC3wYEziELGGmEEXue7D75zbwIIVUMWAVbHItGPx0ziyXxrOMQx4rQEVEV45Ut/1IotuEvwqPopzIOkDMf0A==",
+ "dev": true,
+ "peer": true
},
"type-fest": {
"version": "0.18.1",
@@ -6650,9 +7178,9 @@
"dev": true
},
"typescript": {
- "version": "4.4.4",
- "resolved": "https://registry.npmjs.org/typescript/-/typescript-4.4.4.tgz",
- "integrity": "sha512-DqGhF5IKoBl8WNf8C1gu8q0xZSInh9j1kJJMqT3a94w1JzVaBU4EXOSMrz9yDqMT0xt3selp83fuFMQ0uzv6qA==",
+ "version": "4.5.5",
+ "resolved": "https://registry.npmjs.org/typescript/-/typescript-4.5.5.tgz",
+ "integrity": "sha512-TCTIul70LyWe6IJWT8QSYeA54WQe8EjQFU4wY52Fasj5UKx88LNYKCgBEHcOMOrFF1rKGbD8v/xcNWVUq9SymA==",
"dev": true
},
"uglify-js": {
@@ -6668,6 +7196,15 @@
"integrity": "sha512-hAZsKq7Yy11Zu1DE0OzWjw7nnLZmJZYTDZZyEFHZdUhV8FkH5MCfoU1XMaxXovpyW5nq5scPqq0ZDP9Zyl04oQ==",
"dev": true
},
+ "uri-js": {
+ "version": "4.4.1",
+ "resolved": "https://registry.npmjs.org/uri-js/-/uri-js-4.4.1.tgz",
+ "integrity": "sha512-7rKUyy33Q1yc98pQ1DAmLtwX109F7TIfWlW1Ydo8Wl1ii1SeHieeh0HHfPeL2fMXK6z0s8ecKs9frCuLJvndBg==",
+ "dev": true,
+ "requires": {
+ "punycode": "^2.1.0"
+ }
+ },
"util-deprecate": {
"version": "1.0.2",
"resolved": "https://registry.npmjs.org/util-deprecate/-/util-deprecate-1.0.2.tgz",
@@ -6684,6 +7221,16 @@
"spdx-expression-parse": "^3.0.0"
}
},
+ "wcwidth": {
+ "version": "1.0.1",
+ "resolved": "https://registry.npmjs.org/wcwidth/-/wcwidth-1.0.1.tgz",
+ "integrity": "sha1-8LDc+RW8X/FSivrbLA4XtTLaL+g=",
+ "dev": true,
+ "peer": true,
+ "requires": {
+ "defaults": "^1.0.3"
+ }
+ },
"which": {
"version": "1.3.1",
"resolved": "https://registry.npmjs.org/which/-/which-1.3.1.tgz",
diff --git a/package.json b/package.json
index 50053c6..e5cd924 100644
--- a/package.json
+++ b/package.json
@@ -1,19 +1,23 @@
{
"name": "trusted-firmware-a",
- "version": "2.5.0",
+ "version": "2.6.0",
"license": "BSD-3-Clause",
"private": true,
"scripts": {
"postinstall": "husky install",
- "release": "standard-version -i docs/change-log.md"
+ "release": "standard-version"
+ },
+ "engines": {
+ "node": ">=16.0.0"
},
"devDependencies": {
- "@commitlint/cli": "^14.1.0",
- "@commitlint/config-conventional": "^14.1.0",
+ "@commitlint/cli": "^16.1.0",
+ "@commitlint/config-conventional": "^16.0.0",
+ "@commitlint/cz-commitlint": "^16.1.0",
"commitizen": "^4.2.4",
"conventional-changelog-tf-a": "file:tools/conventional-changelog-tf-a",
- "cz-conventional-changelog": "^3.3.0",
"husky": "^7.0.4",
+ "js-yaml": "^4.1.0",
"standard-version": "^9.3.2"
}
}
diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
index 4943e58..af43065 100644
--- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -87,6 +87,7 @@
return 0;
}
+#if TRUSTED_BOARD_BOOT
static int fvp_populate_critical_data(struct fvp_critical_data *critical_data)
{
char *nv_ctr_oids[MAX_NV_CTR_IDS] = {
@@ -104,17 +105,26 @@
return 0;
}
+#endif /* TRUSTED_BOARD_BOOT */
static int fvp_populate_and_measure_critical_data(void)
{
+ int rc = 0;
+
+/*
+ * FVP platform only measures 'platform NV-counter' and hence its
+ * measurement makes sense during Trusted-Boot flow only.
+ */
+#if TRUSTED_BOARD_BOOT
struct fvp_critical_data populate_critical_data;
- int rc = fvp_populate_critical_data(&populate_critical_data);
+ rc = fvp_populate_critical_data(&populate_critical_data);
if (rc == 0) {
rc = plat_mboot_measure_critical_data(CRITICAL_DATA_ID,
&populate_critical_data,
sizeof(populate_critical_data));
}
+#endif /* TRUSTED_BOARD_BOOT */
return rc;
}
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index e7a28ac..d8d19de 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -117,10 +117,15 @@
#if TRUSTED_BOARD_BOOT
/* To access the Root of Trust Public Key registers. */
MAP_DEVICE2,
-#if !BL2_AT_EL3
- ARM_MAP_BL1_RW,
-#endif
#endif /* TRUSTED_BOARD_BOOT */
+
+#if CRYPTO_SUPPORT && !BL2_AT_EL3
+ /*
+ * To access shared the Mbed TLS heap while booting the
+ * system with Crypto support
+ */
+ ARM_MAP_BL1_RW,
+#endif /* CRYPTO_SUPPORT && !BL2_AT_EL3 */
#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
@@ -444,7 +449,7 @@
#endif
}
-#if TRUSTED_BOARD_BOOT
+#if CRYPTO_SUPPORT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
assert(heap_addr != NULL);
@@ -452,7 +457,7 @@
return arm_get_mbedtls_heap(heap_addr, heap_size);
}
-#endif
+#endif /* CRYPTO_SUPPORT */
void fvp_timer_init(void)
{
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index d89e122..fcc4a0a 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -144,12 +144,10 @@
* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
* little space for growth.
*/
-#if TRUSTED_BOARD_BOOT
-#if COT_DESC_IN_DTB
+#if TRUSTED_BOARD_BOOT && COT_DESC_IN_DTB
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION)
-#else
+#elif CRYPTO_SUPPORT
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION)
-#endif
#else
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION)
#endif
@@ -187,17 +185,17 @@
* Size of cacheable stacks
*/
#if defined(IMAGE_BL1)
-# if TRUSTED_BOARD_BOOT
+# if CRYPTO_SUPPORT
# define PLATFORM_STACK_SIZE UL(0x1000)
# else
# define PLATFORM_STACK_SIZE UL(0x500)
-# endif
+# endif /* CRYPTO_SUPPORT */
#elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
+# if CRYPTO_SUPPORT
# define PLATFORM_STACK_SIZE UL(0x1000)
# else
# define PLATFORM_STACK_SIZE UL(0x600)
-# endif
+# endif /* CRYPTO_SUPPORT */
#elif defined(IMAGE_BL2U)
# define PLATFORM_STACK_SIZE UL(0x400)
#elif defined(IMAGE_BL31)
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index b7f9c61..e184c3f 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -376,10 +376,6 @@
include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
-BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
-
ifeq (${MEASURED_BOOT},1)
BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \
plat/arm/board/fvp/fvp_bl1_measured_boot.c
@@ -387,6 +383,10 @@
plat/arm/board/fvp/fvp_bl2_measured_boot.c
endif
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
+BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
+
# FVP being a development platform, enable capability to disable Authentication
# dynamically if TRUSTED_BOARD_BOOT is set.
DYN_DISABLE_AUTH := 1
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 8765fa2..3acd88e 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -37,6 +37,15 @@
ENABLE_SVE_FOR_NS := 1
ENABLE_SVE_FOR_SWD := 1
+# enable trace buffer control registers access to NS by default
+ENABLE_TRBE_FOR_NS := 1
+
+# enable trace system registers access to NS by default
+ENABLE_SYS_REG_TRACE_FOR_NS := 1
+
+# enable trace filter control registers access to NS by default
+ENABLE_TRF_FOR_NS := 1
+
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 320bb82..73338cb 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -202,10 +202,10 @@
assert(desc != NULL);
desc->ep_info.args.arg0 = fw_config_info->config_addr;
-#if TRUSTED_BOARD_BOOT
+#if CRYPTO_SUPPORT
/* Share the Mbed TLS heap info with other images */
arm_bl1_set_mbedtls_heap();
-#endif /* TRUSTED_BOARD_BOOT */
+#endif /* CRYPTO_SUPPORT */
/*
* Allow access to the System counter timer module and program
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 064ed57..711ed03 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -358,10 +358,8 @@
ifneq (${TRUSTED_BOARD_BOOT},0)
# Include common TBB sources
- AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- lib/fconf/fconf_tbbr_getter.c
+ AUTH_SOURCES := drivers/auth/auth_mod.c \
+ drivers/auth/img_parser_mod.c
# Include the selected chain of trust sources.
ifeq (${COT},tbbr)
@@ -389,6 +387,12 @@
$(eval $(call TOOL_ADD_IMG,ns_bl2u,--fwu,FWU_))
+ IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk
+
+ $(info Including ${IMG_PARSER_LIB_MK})
+ include ${IMG_PARSER_LIB_MK}
+endif
+
# Include Measured Boot makefile before any Crypto library makefile.
# Crypto library makefile may need default definitions of Measured Boot build
# flags present in Measured Boot makefile.
@@ -398,20 +402,21 @@
include ${MEASURED_BOOT_MK}
endif
+ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT}),)
+ CRYPTO_SOURCES := drivers/auth/crypto_mod.c \
+ lib/fconf/fconf_tbbr_getter.c
+ BL1_SOURCES += ${CRYPTO_SOURCES}
+ BL2_SOURCES += ${CRYPTO_SOURCES}
+
# We expect to locate the *.mk files under the directories specified below
-ifeq (${ARM_CRYPTOCELL_INTEG},0)
- CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk
-else
- CRYPTO_LIB_MK := drivers/auth/cryptocell/cryptocell_crypto.mk
-endif
- IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk
+ ifeq (${ARM_CRYPTOCELL_INTEG},0)
+ CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk
+ else
+ CRYPTO_LIB_MK := drivers/auth/cryptocell/cryptocell_crypto.mk
+ endif
$(info Including ${CRYPTO_LIB_MK})
include ${CRYPTO_LIB_MK}
-
- $(info Including ${IMG_PARSER_LIB_MK})
- include ${IMG_PARSER_LIB_MK}
-
endif
ifeq (${RECLAIM_INIT_CODE}, 1)
@@ -419,4 +424,3 @@
$(error "To reclaim init code xlat tables v2 must be used")
endif
endif
-
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index 6aae9ae..7abd1cd 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,9 +13,9 @@
#include <common/debug.h>
#include <common/desc_image_load.h>
#include <common/tbbr/tbbr_img_def.h>
-#if TRUSTED_BOARD_BOOT
+#if CRYPTO_SUPPORT
#include <drivers/auth/mbedtls/mbedtls_config.h>
-#endif
+#endif /* CRYPTO_SUPPORT */
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <lib/fconf/fconf_tbbr_getter.h>
@@ -23,7 +23,7 @@
#include <plat/arm/common/arm_dyn_cfg_helpers.h>
#include <plat/arm/common/plat_arm.h>
-#if TRUSTED_BOARD_BOOT
+#if CRYPTO_SUPPORT
static void *mbedtls_heap_addr;
static size_t mbedtls_heap_size;
@@ -118,7 +118,7 @@
#endif /* !MEASURED_BOOT */
}
}
-#endif /* TRUSTED_BOARD_BOOT */
+#endif /* CRYPTO_SUPPORT */
/*
* BL2 utility function to initialize dynamic configuration specified by
diff --git a/plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S b/plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S
deleted file mode 100644
index 80524fc..0000000
--- a/plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <platform_def.h>
-
- .globl plat_reset_handler
- .globl plat_my_core_pos
- .globl platform_mem_init
-
-func plat_my_core_pos
- mrs x0, mpidr_el1
- and x1, x0, #MPIDR_CPU_MASK //reserve the last 8 bits
- and x0, x0, #MPIDR_CLUSTER_MASK
- add x0, x1, x0, LSR #4 //4 cores
- ret
-endfunc plat_my_core_pos
-
-func platform_mem_init
- mov x29, x30
- bl inv_dcache_range
-
-//SDRAM_CFG
- ldr w0, =0x1080000
- ldr w1, =0x0c000c45
- str w1, [x0, #0x110]
-//CS0_BNDS
- ldr w1, =0x7f000000
- str w1, [x0, #0x000]
-//CS0_CONFIG
- ldr w1, =0x22030480
- str w1, [x0, #0x080]
-//TIMING_CFG_0
- ldr w1, =0x18005591
- str w1, [x0, #0x104]
-//TIMING_CFG_1
- ldr w1, =0x428cb4bb
- str w1, [x0, #0x108]
-//TIMING_CFG_2
- ldr w1, =0x11c14800
- str w1, [x0, #0x10C]
-//TIMING_CFG_3
- ldr w1, =0x00100c01
- str w1, [x0, #0x100]
-//TIMING_CFG_4
- ldr w1, =0x02000000
- str w1, [x0, #0x160]
-//TIMING_CFG_5
- ldr w1, =0x00144003
- str w1, [x0, #0x164]
-//TIMING_CFG_7
- ldr w1, =0x00003013
- str w1, [x0, #0x16C]
-//TIMING_CFG_8
- ldr w1, =0x00561102
- str w1, [x0, #0x250]
-//SDRAM_CFG_2
- ldr w1, =0x00114000
- str w1, [x0, #0x114]
-//SDRAM_MODE
- ldr w1, =0x10020103
- str w1, [x0, #0x118]
-//SDRAM_MODE_2
- ldr w1, =0x0
- str w1, [x0, #0x11C]
-//SDRAM_INTERVAL
- ldr w1, =0x18066018
- str w1, [x0, #0x124]
-//DDR_WRLVL_CNTL
- ldr w1, =0x07f675c6
- str w1, [x0, #0x174]
-//DDR_WRLVL_CNTL_2
- ldr w1, =0x00080907
- str w1, [x0, #0x190]
-//DDR_WRLVL_CNTL_3
- ldr w1, =0x0
- str w1, [x0, #0x194]
-//DDR_CDR1
- ldr w1, =0x00000480
- str w1, [x0, #0xB28]
-//DDR_CDR2
- ldr w1, =0x81a10000
- str w1, [x0, #0xB2C]
-//SDRAM_CLK_CNTL
- ldr w1, =0x00000003
- str w1, [x0, #0x130]
-//DDR_ZQ_CNTL
- ldr w1, =0x0507098a
- str w1, [x0, #0x170]
-//SDRAM_MODE_9
- ldr w1, =0x00050000
- str w1, [x0, #0x220]
-//SDRAM_MODE_10
- ldr w1, =0x00000004
- str w1, [x0, #0x224]
-//CS0_CONFIG_2
- ldr w1, =0x0
- str w1, [x0, #0x0C0]
-//SDRAM_CFG
- ldr w1, =0x08000cc5
- str w1, [x0, #0x110]
-
- mov w3,#0
- ldr w4,=0xffffff01
-z_loop:
-delay_loop1:
- sub w4, w4, #1
- cmp w4, #0
- b.gt delay_loop1
-
- ldr w1, [x0, #0x114]
- add w3, w3, #1
- cmp w1, #0 //'\n'
- b.eq 1f
- cmp w3, #20
- b.gt 1f
- b z_loop
-
-1:
- ldr w4,=0xffffff02
-delay_loop2:
- sub w4, w4, #1
- cmp w4, #0
- b.gt delay_loop2
-
- ldr w1, =0x00000000
- str w1, [x0]
-
- ret x29
-endfunc platform_mem_init
-
-func apply_platform_errata
- /*TODO if needed*/
- ret
-endfunc apply_platform_errata
-
-func plat_reset_handler
- mov x29, x30
- bl apply_platform_errata
-
- mov x30, x29
- ret
-endfunc plat_reset_handler
diff --git a/plat/layerscape/board/ls1043/include/ls_def.h b/plat/layerscape/board/ls1043/include/ls_def.h
deleted file mode 100644
index d8c66e3..0000000
--- a/plat/layerscape/board/ls1043/include/ls_def.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef LS_DEF_H
-#define LS_DEF_H
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <common/tbbr/tbbr_img_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/utils_def.h>
-#include <plat/common/common_def.h>
-
-/******************************************************************************
- * Definitions common to all ARM standard platforms
- *****************************************************************************/
-/* Special value used to verify platform parameters from BL2 to BL31 */
-#define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
-
-#define LS_CACHE_WRITEBACK_SHIFT 6
-
-/*
- * Macros mapping the MPIDR Affinity levels to Layerscape Platform Power levels. The
- * power levels have a 1:1 mapping with the MPIDR affinity levels.
- */
-#define LS_PWR_LVL0 MPIDR_AFFLVL0
-#define LS_PWR_LVL1 MPIDR_AFFLVL1
-#define LS_PWR_LVL2 MPIDR_AFFLVL2
-
-/*
- * Macros for local power states in Layerscape platforms encoded by State-ID field
- * within the power-state parameter.
- */
-/* Local power state for power domains in Run state. */
-#define LS_LOCAL_STATE_RUN U(0)
-/* Local power state for retention. Valid only for CPU power domains */
-#define LS_LOCAL_STATE_RET U(1)
-/*
- * Local power state for OFF/power-down. Valid for CPU and cluster power
- * domains
- */
-#define LS_LOCAL_STATE_OFF U(2)
-
-#define LS_MAP_NS_DRAM MAP_REGION_FLAT( \
- (LS_NS_DRAM_BASE), \
- LS_DRAM1_SIZE, \
- MT_DEVICE | MT_RW | MT_NS)
-
-#define LS_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
- TSP_SEC_MEM_BASE, \
- TSP_SEC_MEM_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-
-#define LS_MAP_FLASH0_RW MAP_REGION_FLAT(PLAT_LS_FLASH_BASE,\
- PLAT_LS_FLASH_SIZE, \
- MT_DEVICE | MT_RW)
-
-#define LS_MAP_CCSR MAP_REGION_FLAT(PLAT_LS_CCSR_BASE, \
- PLAT_LS_CCSR_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-
-#define LS_MAP_CONSOLE MAP_REGION_FLAT(PLAT_LS1043_DUART1_BASE, \
- PLAT_LS1043_DUART_SIZE, \
- MT_DEVICE | MT_RW | MT_NS)
-
-/*
- * The number of regions like RO(code), coherent and data required by
- * different BL stages which need to be mapped in the MMU.
- */
-/******************************************************************************
- * Required platform porting definitions common to all ARM standard platforms
- *****************************************************************************/
-
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
-
-/*
- * This macro defines the deepest retention state possible. A higher state
- * id will represent an invalid or a power down state.
- */
-#define PLAT_MAX_RET_STATE LS_LOCAL_STATE_RET
-
-/*
- * This macro defines the deepest power down states possible. Any state ID
- * higher than this is invalid.
- */
-#define PLAT_MAX_OFF_STATE LS_LOCAL_STATE_OFF
-
-/*
- * Some data must be aligned on the biggest cache line size in the platform.
- * This is known only to the platform as it might have a combination of
- * integrated and external caches.
- */
-#define CACHE_WRITEBACK_GRANULE (1 << LS_CACHE_WRITEBACK_SHIFT)
-
-/*
- * One cache line needed for bakery locks on Layerscape platforms
- */
-#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
-
-#endif /* LS_DEF_H */
diff --git a/plat/layerscape/board/ls1043/include/plat_macros.S b/plat/layerscape/board/ls1043/include/plat_macros.S
deleted file mode 100644
index 1ae43ef..0000000
--- a/plat/layerscape/board/ls1043/include/plat_macros.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_MACROS_S
-#define PLAT_MACROS_S
-
- /* ---------------------------------------------
- * The below required platform porting macro
- * prints out relevant GIC and CCI registers
- * whenever an unhandled exception is taken in
- * BL31.
- * Clobbers: x0 - x10, x16, x17, sp
- * ---------------------------------------------
- */
- .macro plat_crash_print_regs
- .endm
-
-#endif /* PLAT_MACROS_S */
diff --git a/plat/layerscape/board/ls1043/include/platform_def.h b/plat/layerscape/board/ls1043/include/platform_def.h
deleted file mode 100644
index 8b0a94a..0000000
--- a/plat/layerscape/board/ls1043/include/platform_def.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <drivers/arm/tzc400.h>
-#include <lib/utils.h>
-#include <plat/common/common_def.h>
-
-#include "ls_def.h"
-
-#define FIRMWARE_WELCOME_STR_LS1043 "Welcome to LS1043 BL1 Phase\n"
-#define FIRMWARE_WELCOME_STR_LS1043_BL2 "Welcome to LS1043 BL2 Phase\n"
-#define FIRMWARE_WELCOME_STR_LS1043_BL31 "Welcome to LS1043 BL31 Phase\n"
-#define FIRMWARE_WELCOME_STR_LS1043_BL32 "Welcome to LS1043 BL32 Phase, TSP\n"
-
-/* Required platform porting definitions */
-#define PLAT_PRIMARY_CPU U(0x0)
-#define PLAT_MAX_PWR_LVL LS_PWR_LVL1
-#define PLATFORM_CORE_COUNT U(4)
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-
-/*
- * Required LS standard platform porting definitions
- */
-#define PLAT_LS_CLUSTER_COUNT U(1)
-#define PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX U(4)
-#define LS1043_CLUSTER_COUNT U(1)
-#define LS1043_MAX_CPUS_PER_CLUSTER U(4)
-
-#define LS_DRAM1_BASE 0x80000000
-#define LS_DRAM2_BASE 0x880000000
-#define LS_DRAM2_SIZE 0x780000000 /* 30G */
-#define LS_DRAM1_SIZE 0x80000000 /* 2G */
-#define LS_NS_DRAM_BASE LS_DRAM1_BASE
-/* 64M Secure Memory, in fact there a 2M non-secure hole on top of it */
-#define LS_SECURE_DRAM_SIZE (64 * 1024 * 1024)
-#define LS_SECURE_DRAM_BASE (LS_NS_DRAM_BASE + LS_DRAM1_SIZE - \
- LS_SECURE_DRAM_SIZE)
-#define LS_NS_DRAM_SIZE (LS_DRAM1_SIZE - LS_SECURE_DRAM_SIZE)
-
-/*
- * By default, BL2 is in DDR memory.
- * If LS_BL2_IN_OCRAM is defined, BL2 will in OCRAM
- */
-/* #define LS_BL2_IN_OCRAM */
-
-#ifndef LS_BL2_IN_OCRAM
-/*
- * on top of SECURE memory is 2M non-secure hole for OPTee,
- * 1M secure memory below this hole will be used for BL2.
- */
-#define LS_BL2_DDR_BASE (LS_SECURE_DRAM_BASE + \
- LS_SECURE_DRAM_SIZE \
- - 3 * 1024 * 1024)
-#endif
-
-#define PLAT_LS_CCSR_BASE 0x1000000
-#define PLAT_LS_CCSR_SIZE 0xF000000
-
-/* Flash base address, currently ROM is not used for TF-A images on LS platforms */
-#define PLAT_LS_TRUSTED_ROM_BASE 0x60100000
-#define PLAT_LS_TRUSTED_ROM_SIZE 0x20000000 /* Flash size */
-#define PLAT_LS_FLASH_SIZE 0x20000000
-#define PLAT_LS_FLASH_BASE 0x60000000
-
-#define LS_SRAM_BASE 0x10000000
-#define LS_SRAM_LIMIT 0x10020000 /* 128K */
-#define LS_SRAM_SHARED_SIZE 0x1000 /* 4K */
-#define LS_SRAM_SIZE (LS_SRAM_LIMIT - LS_SRAM_BASE)
-#define LS_BL_RAM_BASE (LS_SRAM_BASE + LS_SRAM_SHARED_SIZE)
-
-#define PLAT_LS_FIP_MAX_SIZE 0x4000000
-
-/* Memory Layout */
-
-#define BL1_RO_BASE PLAT_LS_TRUSTED_ROM_BASE
-#define BL1_RO_LIMIT (PLAT_LS_TRUSTED_ROM_BASE \
- + PLAT_LS_TRUSTED_ROM_SIZE)
-#define PLAT_LS_FIP_BASE 0x60120000
-
-#ifdef LS_BL2_IN_OCRAM
-/* BL2 is in OCRAM */
-#define PLAT_LS_MAX_BL1_RW_SIZE (52 * 1024) /* 52K */
-#define PLAT_LS_MAX_BL31_SIZE (64 * 1024) /* 64K */
-#define PLAT_LS_MAX_BL2_SIZE (44 * 1024) /* 44K */
-/* Reserve memory in OCRAM for BL31 Text and ROData segment */
-#define BL31_TEXT_RODATA_SIZE (32 * 1024) /* 32K */
-#else /* LS_BL2_IN_OCRAM */
-/* BL2 in DDR */
-#define PLAT_LS_MAX_BL1_RW_SIZE (64 * 1024) /* 64K */
-#define PLAT_LS_MAX_BL31_SIZE (64 * 1024) /* 64K */
-#define PLAT_LS_MAX_BL2_SIZE (1 * 1024 * 1024) /* 1M */
-#endif /* LS_BL2_IN_OCRAM */
-/*
- * Put BL31 at the start of OCRAM.
- */
-#define BL31_BASE LS_SRAM_BASE
-#define BL31_LIMIT (LS_SRAM_BASE + PLAT_LS_MAX_BL31_SIZE)
-
-#ifdef LS_BL2_IN_OCRAM
-/*
- * BL2 follow BL31 Text and ROData region.
- */
-#define BL2_BASE (BL31_BASE + BL31_TEXT_RODATA_SIZE)
-#define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
-
-#else
-/*
- * BL2 in DDR memory.
- */
-#define BL2_BASE LS_BL2_DDR_BASE
-#define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
-
-#endif
-
-/*
- * Put BL1 RW at the top of the Trusted SRAM.
- */
-#ifdef LS_BL2_IN_OCRAM
-#define BL1_RW_BASE BL2_LIMIT
-#else
-#define BL1_RW_BASE BL31_LIMIT
-#endif
-#define BL1_RW_LIMIT LS_SRAM_LIMIT
-
-/* Put BL32 in secure memory */
-#define BL32_BASE LS_SECURE_DRAM_BASE
-#define BL32_LIMIT (LS_SECURE_DRAM_BASE + LS_SECURE_DRAM_SIZE)
-/* BL33 memory region */
-#define BL33_BASE 0x82000000
-#define BL33_LIMIT (LS_NS_DRAM_BASE + LS_NS_DRAM_SIZE)
-
-/*******************************************************************************
- * BL32 specific defines.
- ******************************************************************************/
-/*
- * On ARM standard platforms, the TSP can execute from Trusted SRAM,
- * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
- * controller.
- */
-
-#define TSP_SEC_MEM_BASE BL32_BASE
-#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE)
-
-/*
- * ID of the secure physical generic timer interrupt used by the TSP.
- */
-#define TSP_IRQ_SEC_PHY_TIMER 29
-
-
-/*
- * GIC related constants
- */
-#define PLAT_LS1043_CCI_BASE 0x01180000
-#define GICD_BASE 0x01401000
-#define GICC_BASE 0x01402000
-#define GICD_BASE_64K 0x01410000
-#define GICC_BASE_64K 0x01420000
-
-#define DCFG_CCSR_SVR 0x1ee00a4
-#define REV1_0 0x10
-#define REV1_1 0x11
-#define GIC_ADDR_BIT 31
-#define SCFG_GIC400_ALIGN 0x1570188
-
-/* UART related definition */
-
-#define PLAT_LS1043_DUART1_BASE 0x021c0000
-#define PLAT_LS1043_DUART2_BASE 0x021d0000
-#define PLAT_LS1043_DUART_SIZE 0x10000
-
-#define PLAT_LS1043_UART_BASE 0x21c0500
-#define PLAT_LS1043_UART2_BASE 0x21c0600
-#define PLAT_LS1043_UART_CLOCK 400000000
-#define PLAT_LS1043_UART_BAUDRATE 115200
-/* Define UART to be used by TF-A log */
-#define LS_TF_UART_BASE PLAT_LS1043_UART_BASE
-#define LS_TF_UART_CLOCK PLAT_LS1043_UART_CLOCK
-#define LS_TF_UART_BAUDRATE PLAT_LS1043_UART_BAUDRATE
-
-#define LS1043_SYS_CNTCTL_BASE 0x2B00000
-
-#define CONFIG_SYS_IMMR 0x01000000
-#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
-
-/* Size of cacheable stacks */
-#if defined(IMAGE_BL1)
-#define PLATFORM_STACK_SIZE 0x440
-#define MAX_MMAP_REGIONS 6
-#define MAX_XLAT_TABLES 4
-#elif defined(IMAGE_BL2)
-#define PLATFORM_STACK_SIZE 0x400
-#define MAX_MMAP_REGIONS 8
-#define MAX_XLAT_TABLES 6
-#elif defined(IMAGE_BL31)
-#define PLATFORM_STACK_SIZE 0x400
-#define MAX_MMAP_REGIONS 8
-#define MAX_XLAT_TABLES 4
-#elif defined(IMAGE_BL32)
-#define PLATFORM_STACK_SIZE 0x440
-#define MAX_MMAP_REGIONS 8
-#define MAX_XLAT_TABLES 9
-#endif
-
-#define MAX_IO_DEVICES 3
-#define MAX_IO_HANDLES 4
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/layerscape/board/ls1043/include/soc_tzasc.h b/plat/layerscape/board/ls1043/include/soc_tzasc.h
deleted file mode 100644
index 46dfba0..0000000
--- a/plat/layerscape/board/ls1043/include/soc_tzasc.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SOC_TZASC_H
-#define SOC_TZASC_H
-
-#define MAX_NUM_TZC_REGION 3
-
-/* TZASC related constants */
-#define TZASC_CONFIGURATION_REG 0x000
-#define TZASC_SECURITY_INV_REG 0x034
-#define TZASC_SECURITY_INV_EN 0x1
-#define TZASC_REGIONS_REG 0x100
-/* As region address should address atleast 32KB memory. */
-#define TZASC_REGION_LOWADDR_MASK 0xFFFF8000
-#define TZASC_REGION_LOWADDR_OFFSET 0x0
-#define TZASC_REGION_HIGHADDR_OFFSET 0x4
-#define TZASC_REGION_ATTR_OFFSET 0x8
-#define TZASC_REGION_ENABLED 1
-#define TZASC_REGION_DISABLED 0
-#define TZASC_REGION_SIZE_32KB 0xE
-#define TZASC_REGION_SIZE_64KB 0xF
-#define TZASC_REGION_SIZE_128KB 0x10
-#define TZASC_REGION_SIZE_256KB 0x11
-#define TZASC_REGION_SIZE_512KB 0x12
-#define TZASC_REGION_SIZE_1MB 0x13
-#define TZASC_REGION_SIZE_2MB 0x14
-#define TZASC_REGION_SIZE_4MB 0x15
-#define TZASC_REGION_SIZE_8MB 0x16
-#define TZASC_REGION_SIZE_16MB 0x17
-#define TZASC_REGION_SIZE_32MB 0x18
-#define TZASC_REGION_SIZE_64MB 0x19
-#define TZASC_REGION_SIZE_128MB 0x1A
-#define TZASC_REGION_SIZE_256MB 0x1B
-#define TZASC_REGION_SIZE_512MB 0x1C
-#define TZASC_REGION_SIZE_1GB 0x1D
-#define TZASC_REGION_SIZE_2GB 0x1E
-#define TZASC_REGION_SIZE_4GB 0x1F
-#define TZASC_REGION_SIZE_8GB 0x20
-#define TZASC_REGION_SIZE_16GB 0x21
-#define TZASC_REGION_SIZE_32GB 0x22
-#define TZASC_REGION_SECURITY_SR (1 << 3)
-#define TZASC_REGION_SECURITY_SW (1 << 2)
-#define TZASC_REGION_SECURITY_SRW (TZASC_REGION_SECURITY_SR| \
- TZASC_REGION_SECURITY_SW)
-#define TZASC_REGION_SECURITY_NSR (1 << 1)
-#define TZASC_REGION_SECURITY_NSW 1
-#define TZASC_REGION_SECURITY_NSRW (TZASC_REGION_SECURITY_NSR| \
- TZASC_REGION_SECURITY_NSW)
-
-#define CSU_SEC_ACCESS_REG_OFFSET 0x21C
-#define TZASC_BYPASS_MUX_DISABLE 0x4
-#define CCI_TERMINATE_BARRIER_TX 0x8
-#define CONFIG_SYS_FSL_TZASC_ADDR 0x1500000
-
-struct tzc380_reg {
- unsigned int secure;
- unsigned int enabled;
- unsigned int low_addr;
- unsigned int high_addr;
- unsigned int size;
- unsigned int sub_mask;
-};
-
-/* List of MAX_NUM_TZC_REGION TZC regions' boundaries and configurations. */
-
-static const struct tzc380_reg tzc380_reg_list[] = {
- {
- TZASC_REGION_SECURITY_NSRW, /* .secure attr */
- 0x0, /* .enabled */
- 0x0, /* .lowaddr */
- 0x0, /* .highaddr */
- 0x0, /* .size */
- 0x0, /* .submask */
- },
- {
- TZASC_REGION_SECURITY_SRW,
- TZASC_REGION_ENABLED,
- 0xFC000000,
- 0x0,
- TZASC_REGION_SIZE_64MB,
- 0x80, /* Disable region 7 */
- },
- /* reserve 2M non-scure memory for OPTEE public memory */
- {
- TZASC_REGION_SECURITY_SRW,
- TZASC_REGION_ENABLED,
- 0xFF800000,
- 0x0,
- TZASC_REGION_SIZE_8MB,
- 0xC0, /* Disable region 6 & 7 */
- },
-
- {}
-};
-
-#endif /* SOC_TZASC_H */
diff --git a/plat/layerscape/board/ls1043/ls1043_bl1_setup.c b/plat/layerscape/board/ls1043/ls1043_bl1_setup.c
deleted file mode 100644
index dfa4725..0000000
--- a/plat/layerscape/board/ls1043/ls1043_bl1_setup.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/cci.h>
-#include <lib/mmio.h>
-
-#include "plat_ls.h"
-
-static const int cci_map[] = {
- PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX
-};
-
-void bl1_platform_setup(void)
-{
- NOTICE(FIRMWARE_WELCOME_STR_LS1043);
-
- ls_bl1_platform_setup();
-
- /*
- * Initialize system level generic timer for Layerscape Socs.
- */
- ls_delay_timer_init();
-
- /* TODO: remove these DDR code */
- VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
- mmio_write_32(0x1080000 + 0x000, 0x7f000000);
- VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
-}
-
-/*******************************************************************************
- * Perform any BL1 specific platform actions.
- ******************************************************************************/
-void bl1_early_platform_setup(void)
-{
- ls_bl1_early_platform_setup();
-
- /*
- * Initialize Interconnect for this cluster during cold boot.
- * No need for locks as no other CPU is active.
- */
- cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
-
- /*
- * Enable coherency in Interconnect for the primary CPU's cluster.
- */
- cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-
-}
-
-unsigned int bl1_plat_get_next_image_id(void)
-{
- return BL2_IMAGE_ID;
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_bl2_setup.c b/plat/layerscape/board/ls1043/ls1043_bl2_setup.c
deleted file mode 100644
index c9db814..0000000
--- a/plat/layerscape/board/ls1043/ls1043_bl2_setup.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "plat_ls.h"
-
-void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
- u_register_t arg2, u_register_t arg3)
-{
- ls_bl2_early_platform_setup((meminfo_t *)arg1);
-
- /*
- * Initialize system level generic timer for Layerscape Socs.
- */
- ls_delay_timer_init();
-}
-
-void bl2_platform_setup(void)
-{
- NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL2);
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_bl31_setup.c b/plat/layerscape/board/ls1043/ls1043_bl31_setup.c
deleted file mode 100644
index 6d15c11..0000000
--- a/plat/layerscape/board/ls1043/ls1043_bl31_setup.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/cci.h>
-
-#include "plat_ls.h"
-#include "fsl_csu.h"
-
-/* slave interfaces according to the RM */
-static const int cci_map[] = {
- 4,
-};
-
-void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
- u_register_t arg2, u_register_t arg3)
-{
-#ifdef LS_BL2_IN_OCRAM
- unsigned long romem_base = (unsigned long)(&__TEXT_START__);
- unsigned long romem_size = (unsigned long)(&__RODATA_END__)
- - romem_base;
-
- /* Check the Text and RO-Data region size */
- if (romem_size > BL31_TEXT_RODATA_SIZE) {
- ERROR("BL31 Text and RO-Data region size exceed reserved memory size\n");
- panic();
- }
-#endif
-
- /*
- * Initialize system level generic timer for Layerscape Socs.
- */
- ls_delay_timer_init();
-
- ls_bl31_early_platform_setup((void *)arg0, (void *)arg3);
-
- /*
- * Initialize the correct interconnect for this cluster during cold
- * boot. No need for locks as no other CPU is active.
- */
- cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
-
- /*
- * Enable coherency in interconnect for the primary CPU's cluster.
- * Earlier bootloader stages might already do this (e.g. Trusted
- * Firmware's BL1 does it) but we can't assume so. There is no harm in
- * executing this code twice anyway.
- */
- cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-
- /* Init CSU to enable non-secure access to peripherals */
- enable_layerscape_ns_access();
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_err.c b/plat/layerscape/board/ls1043/ls1043_err.c
deleted file mode 100644
index 37077d4..0000000
--- a/plat/layerscape/board/ls1043/ls1043_err.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <errno.h>
-#include <stdint.h>
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-
-/*
- * Error handler
- */
-void plat_error_handler(int err)
-{
- switch (err) {
- case -ENOENT:
- case -EAUTH:
- /* ToDo */
- break;
- default:
- /* Unexpected error */
- break;
- }
-
- /* Loop until the watchdog resets the system */
- for (;;)
- wfi();
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_psci.c b/plat/layerscape/board/ls1043/ls1043_psci.c
deleted file mode 100644
index 8e282cb..0000000
--- a/plat/layerscape/board/ls1043/ls1043_psci.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <endian.h>
-#include <errno.h>
-
-#include <platform_def.h>
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/delay_timer.h>
-#include <lib/mmio.h>
-#include <lib/psci/psci.h>
-#include <plat/common/platform.h>
-
-#define LS_SCFG_BASE 0x01570000
-/* register to store warm boot entry, big endian, higher 32bit */
-#define LS_SCFG_SCRATCHRW0_OFFSET 0x600
-/* register to store warm boot entry, big endian, lower 32bit */
-#define LS_SCFG_SCRATCHRW1_OFFSET 0x604
-#define LS_SCFG_COREBCR_OFFSET 0x680
-
-#define LS_DCFG_BASE 0x01EE0000
-#define LS_DCFG_RSTCR_OFFSET 0x0B0
-#define LS_DCFG_RSTRQMR1_OFFSET 0x0C0
-#define LS_DCFG_BRR_OFFSET 0x0E4
-
-#define LS_SCFG_CORE0_SFT_RST_OFFSET 0x130
-#define LS_SCFG_CORE1_SFT_RST_OFFSET 0x134
-#define LS_SCFG_CORE2_SFT_RST_OFFSET 0x138
-#define LS_SCFG_CORE3_SFT_RST_OFFSET 0x13C
-
-#define LS_SCFG_CORESRENCR_OFFSET 0x204
-
-#define LS_SCFG_RVBAR0_0_OFFSET 0x220
-#define LS_SCFG_RVBAR0_1_OFFSET 0x224
-
-#define LS_SCFG_RVBAR1_0_OFFSET 0x228
-#define LS_SCFG_RVBAR1_1_OFFSET 0x22C
-
-#define LS_SCFG_RVBAR2_0_OFFSET 0x230
-#define LS_SCFG_RVBAR2_1_OFFSET 0x234
-
-#define LS_SCFG_RVBAR3_0_OFFSET 0x238
-#define LS_SCFG_RVBAR3_1_OFFSET 0x23C
-
-/* the entry for core warm boot */
-static uintptr_t warmboot_entry;
-
-/* warm reset single core */
-static void ls1043_reset_core(int core_pos)
-{
- assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
-
- /* set 0 in RVBAR, boot from bootrom at 0x0 */
- mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_0_OFFSET + core_pos * 8,
- 0);
- mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_1_OFFSET + core_pos * 8,
- 0);
-
- dsb();
- /* enable core soft reset */
- mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORESRENCR_OFFSET,
- htobe32(1U << 31));
- dsb();
- isb();
- /* reset core */
- mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORE0_SFT_RST_OFFSET +
- core_pos * 4, htobe32(1U << 31));
- mdelay(10);
-}
-
-static void __dead2 ls1043_system_reset(void)
-{
- /* clear reset request mask bits */
- mmio_write_32(LS_DCFG_BASE + LS_DCFG_RSTRQMR1_OFFSET, 0);
-
- /* set reset request bit */
- mmio_write_32(LS_DCFG_BASE + LS_DCFG_RSTCR_OFFSET,
- htobe32((uint32_t)0x2));
-
- /* system will reset; if fail, enter wfi */
- dsb();
- isb();
- wfi();
-
- panic();
-}
-
-
-static int ls1043_pwr_domain_on(u_register_t mpidr)
-{
- int core_pos = plat_core_pos_by_mpidr(mpidr);
- uint32_t core_mask, brr;
-
- assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
- core_mask = 1 << core_pos;
-
- /* set warm boot entry */
- mmio_write_32(LS_SCFG_BASE + LS_SCFG_SCRATCHRW0_OFFSET,
- htobe32((uint32_t)(warmboot_entry >> 32)));
-
- mmio_write_32(LS_SCFG_BASE + LS_SCFG_SCRATCHRW1_OFFSET,
- htobe32((uint32_t)warmboot_entry));
-
- dsb();
-
- brr = be32toh(mmio_read_32(LS_DCFG_BASE + LS_DCFG_BRR_OFFSET));
- if (brr & core_mask) {
- /* core has been released, must reset it to restart */
- ls1043_reset_core(core_pos);
-
- /* set bit in core boot control register to enable boot */
- mmio_write_32(LS_SCFG_BASE + LS_SCFG_COREBCR_OFFSET,
- htobe32(core_mask));
-
- } else {
- /* set bit in core boot control register to enable boot */
- mmio_write_32(LS_SCFG_BASE + LS_SCFG_COREBCR_OFFSET,
- htobe32(core_mask));
-
- /* release core */
- mmio_write_32(LS_DCFG_BASE + LS_DCFG_BRR_OFFSET,
- htobe32(brr | core_mask));
- }
-
- mdelay(20);
-
- /* wake core in case it is in wfe */
- dsb();
- isb();
- sev();
-
- return PSCI_E_SUCCESS;
-}
-
-static void ls1043_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
- /* Per cpu gic distributor setup */
- gicv2_pcpu_distif_init();
-
- /* Enable the gic CPU interface */
- gicv2_cpuif_enable();
-}
-
-static void ls1043_pwr_domain_off(const psci_power_state_t *target_state)
-{
- /* Disable the gic CPU interface */
- gicv2_cpuif_disable();
-}
-
-static plat_psci_ops_t ls1043_psci_pm_ops = {
- .system_reset = ls1043_system_reset,
- .pwr_domain_on = ls1043_pwr_domain_on,
- .pwr_domain_on_finish = ls1043_pwr_domain_on_finish,
- .pwr_domain_off = ls1043_pwr_domain_off,
-};
-
-int plat_setup_psci_ops(uintptr_t sec_entrypoint,
- const plat_psci_ops_t **psci_ops)
-{
- warmboot_entry = sec_entrypoint;
- *psci_ops = &ls1043_psci_pm_ops;
- return 0;
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_security.c b/plat/layerscape/board/ls1043/ls1043_security.c
deleted file mode 100644
index 18ae56e..0000000
--- a/plat/layerscape/board/ls1043/ls1043_security.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "plat_ls.h"
-
-/*
- * We assume that all security programming is done by the primary core.
- */
-void plat_ls_security_setup(void)
-{
- tzc380_setup();
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_stack_protector.c b/plat/layerscape/board/ls1043/ls1043_stack_protector.c
deleted file mode 100644
index 8a1a4e5..0000000
--- a/plat/layerscape/board/ls1043/ls1043_stack_protector.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <arch_helpers.h>
-
-#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
-
-u_register_t plat_get_stack_protector_canary(void)
-{
- /*
- * Ideally, a random number should be returned instead of the
- * combination of a timer's value and a compile-time constant. As the
- * FVP does not have any random number generator, this is better than
- * nothing but not necessarily really secure.
- */
- return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_topology.c b/plat/layerscape/board/ls1043/ls1043_topology.c
deleted file mode 100644
index c9c6a9c..0000000
--- a/plat/layerscape/board/ls1043/ls1043_topology.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-
-#include <lib/cassert.h>
-
-#include "plat_ls.h"
-#include "platform_def.h"
-
-unsigned char ls1043_power_domain_tree_desc[LS1043_CLUSTER_COUNT + 1];
-
-
-CASSERT(LS1043_CLUSTER_COUNT && LS1043_CLUSTER_COUNT <= 256,
- assert_invalid_ls1043_cluster_count);
-
-/*******************************************************************************
- * This function dynamically constructs the topology according to
- * LS1043_CLUSTER_COUNT and returns it.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- int i;
-
- ls1043_power_domain_tree_desc[0] = LS1043_CLUSTER_COUNT;
-
- for (i = 0; i < LS1043_CLUSTER_COUNT; i++)
- ls1043_power_domain_tree_desc[i + 1] =
- LS1043_MAX_CPUS_PER_CLUSTER;
-
- return ls1043_power_domain_tree_desc;
-}
-
-/*******************************************************************************
- * This function returns the core count within the cluster corresponding to
- * `mpidr`.
- ******************************************************************************/
-unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
-{
- return LS1043_MAX_CPUS_PER_CLUSTER;
-}
-
-/*******************************************************************************
- * This function implements a part of the critical interface between the psci
- * generic layer and the platform that allows the former to query the platform
- * to convert an MPIDR to a unique linear index. An error code (-1) is returned
- * in case the MPIDR is invalid.
- ******************************************************************************/
-int plat_core_pos_by_mpidr(u_register_t mpidr)
-{
- if (ls_check_mpidr(mpidr) == -1)
- return -1;
-
- return plat_ls_calc_core_pos(mpidr);
-}
diff --git a/plat/layerscape/board/ls1043/ls_gic.c b/plat/layerscape/board/ls1043/ls_gic.c
deleted file mode 100644
index cba55ca..0000000
--- a/plat/layerscape/board/ls1043/ls_gic.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <endian.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "soc.h"
-
-/*
- * Get GIC offset
- * For LS1043a rev1.0, GIC base address align with 4k.
- * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
- * is set, GIC base address align with 4K, or else align
- * with 64k.
- */
-void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
-{
-
- uint32_t *ccsr_svr = (uint32_t *)DCFG_CCSR_SVR;
- uint32_t *gic_align = (uint32_t *)SCFG_GIC400_ALIGN;
- uint32_t val;
- uint32_t soc_dev_id;
-
- val = be32toh(mmio_read_32((uintptr_t)ccsr_svr));
- soc_dev_id = val & (SVR_WO_E << 8);
-
- if ((soc_dev_id == (SVR_LS1043A << 8) ||
- soc_dev_id == (SVR_LS1043AE << 8)) &&
- ((val & 0xff) == REV1_1)) {
- val = be32toh(mmio_read_32((uintptr_t)gic_align));
- if (val & (1U << GIC_ADDR_BIT)) {
- *gicc_base = GICC_BASE;
- *gicd_base = GICD_BASE;
- } else {
- *gicc_base = GICC_BASE_64K;
- *gicd_base = GICD_BASE_64K;
- }
- } else {
- *gicc_base = GICC_BASE;
- *gicd_base = GICD_BASE;
- }
-}
diff --git a/plat/layerscape/board/ls1043/platform.mk b/plat/layerscape/board/ls1043/platform.mk
deleted file mode 100644
index d716c61..0000000
--- a/plat/layerscape/board/ls1043/platform.mk
+++ /dev/null
@@ -1,70 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# indicate the reset vector address can be programmed
-PROGRAMMABLE_RESET_ADDRESS := 1
-USE_COHERENT_MEM := 0
-RESET_TO_BL31 := 0
-ENABLE_STACK_PROTECTOR := 0
-LS1043_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
- plat/common/plat_gicv2.c \
- plat/layerscape/board/ls1043/ls_gic.c
-
-
-LS1043_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c
-
-LS1043_SECURITY_SOURCES := plat/layerscape/common/ls_tzc380.c \
- plat/layerscape/board/ls1043/ls1043_security.c
-
-PLAT_INCLUDES := -Iplat/layerscape/board/ls1043/include \
- -Iplat/layerscape/common/include \
-
-PLAT_BL_COMMON_SOURCES := plat/layerscape/common/aarch64/ls_console.S
-
-LS1043_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
-
-LS1043_CPU_LIBS += lib/cpus/aarch64/cortex_a53.S
-
-BL1_SOURCES += plat/layerscape/board/ls1043/ls1043_bl1_setup.c \
- plat/layerscape/board/ls1043/ls1043_err.c \
- drivers/delay_timer/delay_timer.c \
-
-BL1_SOURCES += plat/layerscape/board/ls1043/${ARCH}/ls1043_helpers.S \
- ${LS1043_CPU_LIBS} \
- ${LS1043_INTERCONNECT_SOURCES} \
- $(LS1043_SECURITY_SOURCES)
-
-
-BL2_SOURCES += drivers/delay_timer/delay_timer.c \
- plat/layerscape/board/ls1043/ls1043_bl2_setup.c \
- plat/layerscape/board/ls1043/ls1043_err.c \
- ${LS1043_SECURITY_SOURCES}
-
-
-BL31_SOURCES += plat/layerscape/board/ls1043/ls1043_bl31_setup.c \
- plat/layerscape/board/ls1043/ls1043_topology.c \
- plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S \
- plat/layerscape/board/ls1043/ls1043_psci.c \
- drivers/delay_timer/delay_timer.c \
- ${LS1043_CPU_LIBS} \
- ${LS1043_GIC_SOURCES} \
- ${LS1043_INTERCONNECT_SOURCES} \
- ${LS1043_SECURITY_SOURCES}
-
-# Enable workarounds for selected Cortex-A53 erratas.
-ERRATA_A53_855873 := 1
-
-ifneq (${ENABLE_STACK_PROTECTOR},0)
-PLAT_BL_COMMON_SOURCES += plat/layerscape/board/ls1043/ls1043_stack_protector.c
-endif
-
-ifeq (${ARCH},aarch32)
- NEED_BL32 := yes
-endif
-
-include plat/layerscape/common/ls_common.mk
diff --git a/plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c b/plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c
deleted file mode 100644
index 4fc019c..0000000
--- a/plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "plat_ls.h"
-
-void tsp_early_platform_setup(void)
-{
- ls_tsp_early_platform_setup();
-
- /*Todo: Initialize the platform config for future decision making */
-}
diff --git a/plat/layerscape/board/ls1043/tsp/tsp-ls1043.mk b/plat/layerscape/board/ls1043/tsp/tsp-ls1043.mk
deleted file mode 100644
index 3941427..0000000
--- a/plat/layerscape/board/ls1043/tsp/tsp-ls1043.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# TSP source files specific to FVP platform
-BL32_SOURCES += plat/layerscape/board/ls1043/ls1043_topology.c \
- plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c \
- ${LS1043_GIC_SOURCES}
-
-include plat/layerscape/common/tsp/ls_tsp.mk
diff --git a/plat/layerscape/common/aarch64/ls_bl2_mem_params_desc.c b/plat/layerscape/common/aarch64/ls_bl2_mem_params_desc.c
deleted file mode 100644
index 9410740..0000000
--- a/plat/layerscape/common/aarch64/ls_bl2_mem_params_desc.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <common/desc_image_load.h>
-#include <plat/common/platform.h>
-
-#include <ls_def.h>
-
-/*******************************************************************************
- * Following descriptor provides BL image/ep information that gets used
- * by BL2 to load the images and also subset of this information is
- * passed to next BL image. The image loading sequence is managed by
- * populating the images in required loading order. The image execution
- * sequence is managed by populating the `next_handoff_image_id` with
- * the next executable image id.
- ******************************************************************************/
-static bl_mem_params_node_t bl2_mem_params_descs[] = {
-#ifdef EL3_PAYLOAD_BASE
- /* Fill EL3 payload related information (BL31 is EL3 payload)*/
- {
- .image_id = BL31_IMAGE_ID,
-
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t,
- SECURE | EXECUTABLE | EP_FIRST_EXE),
- .ep_info.pc = EL3_PAYLOAD_BASE,
- .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS),
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t,
- IMAGE_ATTRIB_PLAT_SETUP |
- IMAGE_ATTRIB_SKIP_LOADING),
-
- .next_handoff_image_id = INVALID_IMAGE_ID,
- },
-
-#else /* EL3_PAYLOAD_BASE */
-
- /* Fill BL31 related information */
- {
- .image_id = BL31_IMAGE_ID,
-
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t,
- SECURE | EXECUTABLE | EP_FIRST_EXE),
- .ep_info.pc = BL31_BASE,
- .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS),
-#if DEBUG
- .ep_info.args.arg1 = LS_BL31_PLAT_PARAM_VAL,
-#endif
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
- .image_info.image_base = BL31_BASE,
- .image_info.image_max_size = (BL31_LIMIT - BL31_BASE),
-
-# ifdef BL32_BASE
- .next_handoff_image_id = BL32_IMAGE_ID,
-# else
- .next_handoff_image_id = BL33_IMAGE_ID,
-# endif
- },
-# ifdef BL32_BASE
- /* Fill BL32 related information */
- {
- .image_id = BL32_IMAGE_ID,
-
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
- .ep_info.pc = BL32_BASE,
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t, 0),
- .image_info.image_base = BL32_BASE,
- .image_info.image_max_size = (BL32_LIMIT - BL32_BASE),
-
- .next_handoff_image_id = BL33_IMAGE_ID,
- },
-# endif /* BL32_BASE */
-
- /* Fill BL33 related information */
- {
- .image_id = BL33_IMAGE_ID,
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
-# ifdef PRELOADED_BL33_BASE
- .ep_info.pc = PRELOADED_BL33_BASE,
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t,
- IMAGE_ATTRIB_SKIP_LOADING),
-# else
- .ep_info.pc = BL33_BASE,
-
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t, 0),
- .image_info.image_base = BL33_BASE,
- .image_info.image_max_size = LS_NS_DRAM_SIZE,
-# endif /* PRELOADED_BL33_BASE */
-
- .next_handoff_image_id = INVALID_IMAGE_ID,
- }
-#endif /* EL3_PAYLOAD_BASE */
-};
-
-REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/layerscape/common/aarch64/ls_console.S b/plat/layerscape/common/aarch64/ls_console.S
deleted file mode 100644
index fb8267b..0000000
--- a/plat/layerscape/common/aarch64/ls_console.S
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <console_macros.S>
-#include <assert_macros.S>
-#include "ls_16550.h"
-
- /*
- * "core" functions are low-level implementations that don't require
- * writable memory and are thus safe to call in BL1 crash context.
- */
- .globl console_ls_16550_core_init
- .globl console_ls_16550_core_putc
- .globl console_ls_16550_core_getc
-
- .globl console_ls_16550_putc
- .globl console_ls_16550_getc
- .globl console_ls_16550_flush
-
- /* -----------------------------------------------
- * int console_ls_16550_core_init(uintptr_t base_addr,
- * unsigned int uart_clk, unsigned int baud_rate)
- * Function to initialize the console without a
- * C Runtime to print debug information. This
- * function will be accessed by console_init and
- * crash reporting.
- * In: x0 - console base address
- * w1 - Uart clock in Hz
- * w2 - Baud rate
- * Out: return 1 on success, 0 on error
- * Clobber list : x1, x2, x3
- * -----------------------------------------------
- */
-func console_ls_16550_core_init
- /* Check the input base address */
- cbz x0, init_fail
- /* Check baud rate and uart clock for sanity */
- cbz w1, init_fail
- cbz w2, init_fail
-
- /* Program the baudrate */
- /* Divisor = Uart clock / (16 * baudrate) */
- lsl w2, w2, #4
- udiv w2, w1, w2
- and w1, w2, #0xff /* w1 = DLL */
- lsr w2, w2, #8
- and w2, w2, #0xff /* w2 = DLLM */
- ldrb w3, [x0, #UARTLCR]
- orr w3, w3, #UARTLCR_DLAB
- strb w3, [x0, #UARTLCR] /* enable DLL, DLLM programming */
- strb w1, [x0, #UARTDLL] /* program DLL */
- strb w2, [x0, #UARTDLLM] /* program DLLM */
- mov w2, #~UARTLCR_DLAB
- and w3, w3, w2
- strb w3, [x0, #UARTLCR] /* disable DLL, DLLM programming */
-
- /* 8n1 */
- mov w3, #3
- strb w3, [x0, #UARTLCR]
- /* no interrupt */
- mov w3, #0
- strb w3, [x0, #UARTIER]
- /* enable fifo, DMA */
- mov w3, #(UARTFCR_FIFOEN |UARTFCR_TXCLR | UARTFCR_RXCLR)
- strb w3, [x0, #UARTFCR]
- /* DTR + RTS */
- mov w3, #3
- str w3, [x0, #UARTMCR]
- mov w0, #1
- ret
-init_fail:
- mov w0, #0
- ret
-endfunc console_ls_16550_core_init
-
- .globl console_ls_16550_register
-
- /* -----------------------------------------------
- * int console_ls_16550_register(console_t *console,
- * uintptr_t base, uint32_t clk, uint32_t baud)
- * Function to initialize and register a new 16550
- * console. Storage passed in for the console struct
- * *must* be persistent (i.e. not from the stack).
- * In: x0 - UART register base address
- * w1 - UART clock in Hz
- * w2 - Baud rate
- * x3 - pointer to empty console_t struct
- * Out: return 1 on success, 0 on error
- * Clobber list : x0, x1, x2, x6, x7, x14
- * -----------------------------------------------
- */
-func console_ls_16550_register
- mov x7, x30
- mov x6, x3
- cbz x6, register_fail
- str x0, [x6, #CONSOLE_T_BASE]
-
- bl console_ls_16550_core_init
- cbz x0, register_fail
-
- mov x0, x6
- mov x30, x7
- finish_console_register ls_16550 putc=1, getc=1, flush=1
-
-register_fail:
- ret x7
-endfunc console_ls_16550_register
-
- /* --------------------------------------------------------
- * int console_ls_16550_core_putc(int c, uintptr_t base_addr)
- * Function to output a character over the console. It
- * returns the character printed on success or -1 on error.
- * In : w0 - character to be printed
- * x1 - console base address
- * Out : return -1 on error else return character.
- * Clobber list : x2
- * --------------------------------------------------------
- */
-func console_ls_16550_core_putc
-#if ENABLE_ASSERTIONS
- cmp x1, #0
- ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
-
- /* Prepend '\r' to '\n' */
- cmp w0, #0xA //'\n'
- b.ne 2f
- /* Check if the transmit FIFO is full */
-1: ldrb w2, [x1, #UARTLSR]
- and w2, w2, #UARTLSR_THRE /* #(UARTLSR_TEMT | UARTLSR_THRE)*/
- cmp w2, #(UARTLSR_THRE)
- b.ne 1b
- mov w2, #0xD /* '\r' */
- strb w2, [x1, #UARTTX]
- ldrb w2, [x1, #UARTFCR]
- orr w2, w2, #UARTFCR_TXCLR
-
- /* Check if the transmit FIFO is full */
-2: ldrb w2, [x1, #UARTLSR]
- and w2, w2, #(UARTLSR_THRE)
- cmp w2, #(UARTLSR_THRE)
- b.ne 2b
- strb w0, [x1, #UARTTX]
- ret
-endfunc console_ls_16550_core_putc
-
- /* --------------------------------------------------------
- * int console_16550_putc(int c, console_t *console)
- * Function to output a character over the console. It
- * returns the character printed on success or -1 on error.
- * In : w0 - character to be printed
- * x1 - pointer to console_t structure
- * Out : return -1 on error else return character.
- * Clobber list : x2
- * --------------------------------------------------------
- */
-func console_ls_16550_putc
-#if ENABLE_ASSERTIONS
- cmp x1, #0
- ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
- ldr x1, [x1, #CONSOLE_T_BASE]
- b console_ls_16550_core_putc
-endfunc console_ls_16550_putc
-
- /* ---------------------------------------------
- * int console_ls_16550_core_getc(uintptr_t base_addr)
- * Function to get a character from the console.
- * It returns the character grabbed on success
- * or -1 on if no character is available.
- * In : x0 - console base address
- * Out : w0 - character if available, else -1
- * Clobber list : x0, x1
- * ---------------------------------------------
- */
-func console_ls_16550_core_getc
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
-
- /* Check if the receive FIFO is empty */
-1: ldrb w1, [x0, #UARTLSR]
- tbz w1, #UARTLSR_RDR, 1b
- ldrb w0, [x0, #UARTRX]
- ret
-no_char:
- mov w0, #ERROR_NO_PENDING_CHAR
- ret
-endfunc console_ls_16550_core_getc
-
- /* ---------------------------------------------
- * int console_ls_16550_getc(console_t *console)
- * Function to get a character from the console.
- * It returns the character grabbed on success
- * or -1 on if no character is available.
- * In : x0 - pointer to console_t structure
- * Out : w0 - character if available, else -1
- * Clobber list : x0, x1
- * ---------------------------------------------
- */
-func console_ls_16550_getc
-#if ENABLE_ASSERTIONS
- cmp x1, #0
- ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
- ldr x0, [x0, #CONSOLE_T_BASE]
- b console_ls_16550_core_getc
-endfunc console_ls_16550_getc
-
- /* ---------------------------------------------
- * void console_ls_16550_core_flush(uintptr_t base_addr)
- * Function to force a write of all buffered
- * data that hasn't been output.
- * In : x0 - console base address
- * Out : void
- * Clobber list : x0, x1
- * ---------------------------------------------
- */
-func console_ls_16550_core_flush
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
-
- /* Loop until the transmit FIFO is empty */
-1: ldrb w1, [x0, #UARTLSR]
- and w1, w1, #(UARTLSR_TEMT | UARTLSR_THRE)
- cmp w1, #(UARTLSR_TEMT | UARTLSR_THRE)
- b.ne 1b
-
- ret
-endfunc console_ls_16550_core_flush
-
- /* ---------------------------------------------
- * void console_ls_16550_flush(console_t *console)
- * Function to force a write of all buffered
- * data that hasn't been output.
- * In : x0 - pointer to console_t structure
- * Out : void
- * Clobber list : x0, x1
- * ---------------------------------------------
- */
-func console_ls_16550_flush
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
- ldr x0, [x0, #CONSOLE_T_BASE]
- b console_ls_16550_core_flush
-endfunc console_ls_16550_flush
diff --git a/plat/layerscape/common/aarch64/ls_helpers.S b/plat/layerscape/common/aarch64/ls_helpers.S
deleted file mode 100644
index 5aa5497..0000000
--- a/plat/layerscape/common/aarch64/ls_helpers.S
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <drivers/console.h>
-#include <platform_def.h>
-
- .weak plat_my_core_pos
- .globl plat_crash_console_init
- .globl plat_crash_console_putc
- .globl plat_crash_console_flush
- .weak platform_mem_init
- .globl plat_ls_calc_core_pos
-
-
- /* -----------------------------------------------------
- * unsigned int plat_my_core_pos(void)
- * This function uses the plat_ls_calc_core_pos()
- * definition to get the index of the calling CPU.
- * -----------------------------------------------------
- */
-func plat_my_core_pos
- mrs x0, mpidr_el1
- b plat_ls_calc_core_pos
-endfunc plat_my_core_pos
-
- /* -----------------------------------------------------
- * unsigned int plat_ls_calc_core_pos(u_register_t mpidr)
- * Helper function to calculate the core position.
- * With this function: CorePos = (ClusterId * 4) +
- * CoreId
- * -----------------------------------------------------
- */
-func plat_ls_calc_core_pos
- and x1, x0, #MPIDR_CPU_MASK
- and x0, x0, #MPIDR_CLUSTER_MASK
- add x0, x1, x0, LSR #6
- ret
-endfunc plat_ls_calc_core_pos
-
- /* ---------------------------------------------
- * int plat_crash_console_init(void)
- * Function to initialize the crash console
- * without a C Runtime to print crash report.
- * Clobber list : x0 - x4
- * ---------------------------------------------
- */
-
- /* -----------------------------------------------------
- * int plat_crash_console_init(void)
- * Use normal console by default. Switch it to crash
- * mode so serial consoles become active again.
- * NOTE: This default implementation will only work for
- * crashes that occur after a normal console (marked
- * valid for the crash state) has been registered with
- * the console framework. To debug crashes that occur
- * earlier, the platform has to override these functions
- * with an implementation that initializes a console
- * driver with hardcoded parameters. See
- * docs/porting-guide.rst for more information.
- * -----------------------------------------------------
- */
-func plat_crash_console_init
-#if defined(IMAGE_BL1)
- /*
- * BL1 code can possibly crash so early that the data segment is not yet
- * accessible. Don't risk undefined behavior by trying to run the normal
- * console framework. Platforms that want to debug BL1 will need to
- * override this with custom functions that can run from registers only.
- */
- mov x0, #0
- ret
-#else /* IMAGE_BL1 */
- mov x3, x30
- mov x0, #CONSOLE_FLAG_CRASH
- bl console_switch_state
- mov x0, #1
- ret x3
-#endif
-endfunc plat_crash_console_init
-
- /* -----------------------------------------------------
- * void plat_crash_console_putc(int character)
- * Output through the normal console by default.
- * -----------------------------------------------------
- */
-func plat_crash_console_putc
- b console_putc
-endfunc plat_crash_console_putc
-
- /* -----------------------------------------------------
- * void plat_crash_console_flush(void)
- * Flush normal console by default.
- * -----------------------------------------------------
- */
-func plat_crash_console_flush
- b console_flush
-endfunc plat_crash_console_flush
-
- /* ---------------------------------------------------------------------
- * We don't need to carry out any memory initialization on LS
- * platforms. The Secure SRAM is accessible straight away.
- * ---------------------------------------------------------------------
- */
-func platform_mem_init
- ret
-endfunc platform_mem_init
diff --git a/plat/layerscape/common/include/fsl_csu.h b/plat/layerscape/common/include/fsl_csu.h
deleted file mode 100644
index 5cc88b1..0000000
--- a/plat/layerscape/common/include/fsl_csu.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef FSL_CSU_H
-#define FSL_CSU_H
-
-enum csu_cslx_access {
- CSU_NS_SUP_R = 0x08,
- CSU_NS_SUP_W = 0x80,
- CSU_NS_SUP_RW = 0x88,
- CSU_NS_USER_R = 0x04,
- CSU_NS_USER_W = 0x40,
- CSU_NS_USER_RW = 0x44,
- CSU_S_SUP_R = 0x02,
- CSU_S_SUP_W = 0x20,
- CSU_S_SUP_RW = 0x22,
- CSU_S_USER_R = 0x01,
- CSU_S_USER_W = 0x10,
- CSU_S_USER_RW = 0x11,
- CSU_ALL_RW = 0xff,
-};
-
-struct csu_ns_dev {
- uintptr_t ind;
- uint32_t val;
-};
-
-void enable_layerscape_ns_access(void);
-
-#endif /* FSL_CSU_H */
diff --git a/plat/layerscape/common/include/ls_16550.h b/plat/layerscape/common/include/ls_16550.h
deleted file mode 100644
index 95a64ad..0000000
--- a/plat/layerscape/common/include/ls_16550.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef LS_16550_H
-#define LS_16550_H
-
-#include <drivers/console.h>
-
-/* UART16550 Registers */
-#define UARTTX 0x0
-#define UARTRX 0x0
-#define UARTDLL 0x0
-#define UARTIER 0x1
-#define UARTDLLM 0x1
-#define UARTFCR 0x2
-#define UARTLCR 0x3
-#define UARTLSR 0x5
-#define UARTMCR 0x4
-
-/* FIFO Control Register bits */
-#define UARTFCR_FIFOMD_16450 (0 << 6)
-#define UARTFCR_FIFOMD_16550 (1 << 6)
-#define UARTFCR_RXTRIG_1 (0 << 6)
-#define UARTFCR_RXTRIG_4 (1 << 6)
-#define UARTFCR_RXTRIG_8 (2 << 6)
-#define UARTFCR_RXTRIG_16 (3 << 6)
-#define UARTFCR_TXTRIG_1 (0 << 4)
-#define UARTFCR_TXTRIG_4 (1 << 4)
-#define UARTFCR_TXTRIG_8 (2 << 4)
-#define UARTFCR_TXTRIG_16 (3 << 4)
-#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */
-#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */
-#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */
-#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */
-#define UARTFCR_64FIFO (1 << 5)
-
-/* Line Control Register bits */
-#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */
-#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */
-#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */
-#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */
-#define UARTLCR_PAR (1 << 3) /* Parity */
-#define UARTLCR_STOP (1 << 2) /* Stop Bit */
-#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */
-#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */
-#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */
-#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */
-
-/* Line Status Register bits */
-#define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */
-#define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */
-#define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */
-#define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */
-#define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */
-#define UARTLSR_BRK (1 << 4) /* Break Condition Detected */
-#define UARTLSR_FERR (1 << 3) /* Framing Error */
-#define UARTLSR_PERR (1 << 3) /* Parity Error */
-#define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */
-#define UARTLSR_RDR (1 << 2) /* Rx Data Ready */
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-/*
- * Initialize a new 16550 console instance and register it with the console
- * framework. The |console| pointer must point to storage that will be valid
- * for the lifetime of the console, such as a global or static local variable.
- * Its contents will be reinitialized from scratch.
- */
-int console_ls_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
- console_t *console);
-
-#endif /*__ASSEMBLER__*/
-
-#endif /* LS_16550_H */
diff --git a/plat/layerscape/common/include/plat_ls.h b/plat/layerscape/common/include/plat_ls.h
deleted file mode 100644
index e56670b..0000000
--- a/plat/layerscape/common/include/plat_ls.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_LS_H
-#define PLAT_LS_H
-
-#include <stdint.h>
-
-#include <lib/el3_runtime/cpu_data.h>
-
-/* BL1 utility functions */
-void ls_bl1_platform_setup(void);
-void ls_bl1_early_platform_setup(void);
-
-/* BL2 utility functions */
-void ls_bl2_early_platform_setup(meminfo_t *mem_layout);
-uint32_t ls_get_spsr_for_bl32_entry(void);
-uint32_t ls_get_spsr_for_bl33_entry(void);
-
-/* BL3 utility functions */
-void ls_bl31_early_platform_setup(void *from_bl2,
- void *plat_params_from_bl2);
-
-/* IO storage utility functions */
-void plat_ls_io_setup(void);
-
-
-void ls_setup_page_tables(uintptr_t total_base,
- size_t total_size,
- uintptr_t code_start,
- uintptr_t code_limit,
- uintptr_t rodata_start,
- uintptr_t rodata_limit
-#if USE_COHERENT_MEM
- , uintptr_t coh_start,
- uintptr_t coh_limit
-#endif
-);
-
-/* PSCI utility functions */
-int ls_check_mpidr(u_register_t mpidr);
-
-/* Security utility functions */
-int tzc380_setup(void);
-
-/* Timer utility functions */
-uint64_t ls_get_timer(uint64_t start);
-void ls_delay_timer_init(void);
-
-/* TSP utility functions */
-void ls_tsp_early_platform_setup(void);
-
-/* Helper functions */
-unsigned int plat_ls_calc_core_pos(u_register_t mpidr);
-
-/* others */
-unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr);
-
-#endif /* PLAT_LS_H */
diff --git a/plat/layerscape/common/include/soc.h b/plat/layerscape/common/include/soc.h
deleted file mode 100644
index a5dc855..0000000
--- a/plat/layerscape/common/include/soc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SOC_H
-#define SOC_H
-
-#include <stdint.h>
-
-#define SVR_WO_E 0xFFFFFEu
-#define SVR_LS1043A 0x879204u
-#define SVR_LS1043AE 0x879200u
-
-void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
-
-#endif /* SOC_H */
diff --git a/plat/layerscape/common/ls_bl1_setup.c b/plat/layerscape/common/ls_bl1_setup.c
deleted file mode 100644
index fa69be2..0000000
--- a/plat/layerscape/common/ls_bl1_setup.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-
-#include "ls_16550.h"
-#include "plat_ls.h"
-
-/* Data structure which holds the extents of the trusted SRAM for BL1*/
-static meminfo_t bl1_tzram_layout;
-
-meminfo_t *bl1_plat_sec_mem_layout(void)
-{
- return &bl1_tzram_layout;
-}
-
-/*******************************************************************************
- * BL1 specific platform actions shared between ARM standard platforms.
- ******************************************************************************/
-void ls_bl1_early_platform_setup(void)
-{
- static console_t console;
-
-#if !LS1043_DISABLE_TRUSTED_WDOG
- /* TODO: Enable watchdog */
-
-#endif
-
- /* Initialize the console to provide early debug support */
- console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
- LS_TF_UART_BAUDRATE, &console);
-
- /* Allow BL1 to see the whole Trusted RAM */
- bl1_tzram_layout.total_base = LS_SRAM_BASE;
- bl1_tzram_layout.total_size = LS_SRAM_SIZE;
-}
-
-/******************************************************************************
- * Perform the very early platform specific architecture setup shared between
- * ARM standard platforms. This only does basic initialization. Later
- * architectural setup (bl1_arch_setup()) does not do anything platform
- * specific.
- *****************************************************************************/
-void ls_bl1_plat_arch_setup(void)
-{
- ls_setup_page_tables(bl1_tzram_layout.total_base,
- bl1_tzram_layout.total_size,
- BL_CODE_BASE,
- BL1_CODE_END,
- BL1_RO_DATA_BASE,
- BL1_RO_DATA_END
-#if USE_COHERENT_MEM
- , BL_COHERENT_RAM_BASE,
- BL_COHERENT_RAM_END
-#endif
- );
- VERBOSE("After setup the page tables\n");
-#ifdef __aarch64__
- enable_mmu_el3(0);
-#else
- enable_mmu_svc_mon(0);
-#endif /* __aarch64__ */
- VERBOSE("After MMU enabled\n");
-}
-
-void bl1_plat_arch_setup(void)
-{
- ls_bl1_plat_arch_setup();
-}
-
-/*
- * Perform the platform specific architecture setup shared between
- * ARM standard platforms.
- */
-void ls_bl1_platform_setup(void)
-{
- /* Initialise the IO layer and register platform IO devices */
- plat_ls_io_setup();
-}
-
-void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
-{
-#if !LS1043_DISABLE_TRUSTED_WDOG
- /*TODO: Disable watchdog before leaving BL1 */
-#endif
-}
diff --git a/plat/layerscape/common/ls_bl2_setup.c b/plat/layerscape/common/ls_bl2_setup.c
deleted file mode 100644
index 6ca66bd..0000000
--- a/plat/layerscape/common/ls_bl2_setup.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/bl_common.h>
-#include <common/desc_image_load.h>
-
-#include "ls_16550.h"
-#include "plat_ls.h"
-#include "ls_def.h"
-
-/* Data structure which holds the extents of the trusted SRAM for BL2 */
-static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-
-/*******************************************************************************
- * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
- * in x0. This memory layout is sitting at the base of the free trusted SRAM.
- * Copy it to a safe location before its reclaimed by later BL2 functionality.
- ******************************************************************************/
-void ls_bl2_early_platform_setup(meminfo_t *mem_layout)
-{
- static console_t console;
-
- /* Initialize the console to provide early debug support */
- console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
- LS_TF_UART_BAUDRATE, &console);
-
- /* Setup the BL2 memory layout */
- bl2_tzram_layout = *mem_layout;
-
- /* Initialise the IO layer and register platform IO devices */
- plat_ls_io_setup();
-}
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup here. At the
- * moment this is only initializes the mmu in a quick and dirty way.
- ******************************************************************************/
-void ls_bl2_plat_arch_setup(void)
-{
- ls_setup_page_tables(bl2_tzram_layout.total_base,
- bl2_tzram_layout.total_size,
- BL_CODE_BASE,
- BL_CODE_END,
- BL_RO_DATA_BASE,
- BL_RO_DATA_END
-#if USE_COHERENT_MEM
- , BL_COHERENT_RAM_BASE,
- BL_COHERENT_RAM_END
-#endif
- );
-
-#ifdef __aarch64__
- enable_mmu_el1(0);
-#else
- enable_mmu_svc_mon(0);
-#endif
-}
-
-void bl2_plat_arch_setup(void)
-{
- ls_bl2_plat_arch_setup();
-}
-
-int ls_bl2_handle_post_image_load(unsigned int image_id)
-{
- int err = 0;
- bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
-
- assert(bl_mem_params);
-
- switch (image_id) {
-#ifdef __aarch64__
- case BL32_IMAGE_ID:
- bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry();
- break;
-#endif
-
- case BL33_IMAGE_ID:
- /* BL33 expects to receive the primary CPU MPID (through r0) */
- bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
- bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl33_entry();
- break;
- }
-
- return err;
-}
-
-/*******************************************************************************
- * This function can be used by the platforms to update/use image
- * information for given `image_id`.
- ******************************************************************************/
-int bl2_plat_handle_post_image_load(unsigned int image_id)
-{
- return ls_bl2_handle_post_image_load(image_id);
-}
diff --git a/plat/layerscape/common/ls_bl31_setup.c b/plat/layerscape/common/ls_bl31_setup.c
deleted file mode 100644
index 7a91aef..0000000
--- a/plat/layerscape/common/ls_bl31_setup.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/bl_common.h>
-#include <common/interrupt_props.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/console.h>
-#include <lib/mmio.h>
-
-#include "ls_16550.h"
-#include "plat_ls.h"
-#include "soc.h"
-
-/*
- * Placeholder variables for copying the arguments that have been passed to
- * BL31 from BL2.
- */
-static entry_point_info_t bl32_image_ep_info;
-static entry_point_info_t bl33_image_ep_info;
-
-static const interrupt_prop_t g0_interrupt_props[] = {
- INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
-};
-
-gicv2_driver_data_t ls_gic_data = {
- .gicd_base = GICD_BASE,
- .gicc_base = GICC_BASE,
- .interrupt_props = g0_interrupt_props,
- .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
-};
-
-
-/*******************************************************************************
- * Return a pointer to the 'entry_point_info' structure of the next image for the
- * security state specified. BL33 corresponds to the non-secure image type
- * while BL32 corresponds to the secure image type. A NULL pointer is returned
- * if the image does not exist.
- ******************************************************************************/
-entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
-{
- entry_point_info_t *next_image_info;
-
- assert(sec_state_is_valid(type));
- next_image_info = (type == NON_SECURE)
- ? &bl33_image_ep_info : &bl32_image_ep_info;
-
- if (next_image_info->pc)
- return next_image_info;
- else
- return NULL;
-}
-
-/*******************************************************************************
- * Perform any BL31 early platform setup common to Layerscape platforms.
- * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
- * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
- * done before the MMU is initialized so that the memory layout can be used
- * while creating page tables. BL2 has flushed this information to memory, so
- * we are guaranteed to pick up good data.
- ******************************************************************************/
-void ls_bl31_early_platform_setup(void *from_bl2,
- void *plat_params_from_bl2)
-{
- static console_t console;
-
- /* Initialize the console to provide early debug support */
- console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
- LS_TF_UART_BAUDRATE, &console);
-#if RESET_TO_BL31
- /* There are no parameters from BL2 if BL31 is a reset vector */
- assert(from_bl2 == NULL);
- assert(plat_params_from_bl2 == NULL);
-
-#ifdef BL32_BASE
- /* Populate entry point information for BL32 */
- SET_PARAM_HEAD(&bl32_image_ep_info,
- PARAM_EP,
- VERSION_1,
- 0);
- SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
- bl32_image_ep_info.pc = BL32_BASE;
- bl32_image_ep_info.spsr = ls_get_spsr_for_bl32_entry();
-#endif /* BL32_BASE */
-
- /* Populate entry point information for BL33 */
- SET_PARAM_HEAD(&bl33_image_ep_info,
- PARAM_EP,
- VERSION_1,
- 0);
- /*
- * Tell BL31 where the non-trusted software image
- * is located and the entry state information
- */
- bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
-
- bl33_image_ep_info.spsr = ls_get_spsr_for_bl33_entry();
- SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
-
-#else /* RESET_TO_BL31 */
-
- /*
- * In debug builds, we pass a special value in 'plat_params_from_bl2'
- * to verify platform parameters from BL2 to BL31.
- * In release builds, it's not used.
- */
- assert(((unsigned long long)plat_params_from_bl2) ==
- LS_BL31_PLAT_PARAM_VAL);
-
- /*
- * Check params passed from BL2 should not be NULL,
- */
- bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
-
- assert(params_from_bl2 != NULL);
- assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
- assert(params_from_bl2->h.version >= VERSION_2);
-
- bl_params_node_t *bl_params = params_from_bl2->head;
-
- /*
- * Copy BL33 and BL32 (if present), entry point information.
- * They are stored in Secure RAM, in BL2's address space.
- */
- while (bl_params) {
- if (bl_params->image_id == BL32_IMAGE_ID)
- bl32_image_ep_info = *bl_params->ep_info;
-
- if (bl_params->image_id == BL33_IMAGE_ID)
- bl33_image_ep_info = *bl_params->ep_info;
-
- bl_params = bl_params->next_params_info;
- }
-
- if (bl33_image_ep_info.pc == 0)
- panic();
-
-#endif /* RESET_TO_BL31 */
-}
-
-/*******************************************************************************
- * Perform any BL31 platform setup common to Layerscape platforms
- ******************************************************************************/
-void ls_bl31_platform_setup(void)
-{
- uint32_t gicc_base, gicd_base;
-
- NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL31);
- /* Initialize the GIC driver, cpu and distributor interfaces */
- get_gic_offset(&gicc_base, &gicd_base);
- ls_gic_data.gicd_base = (uintptr_t)gicd_base;
- ls_gic_data.gicc_base = (uintptr_t)gicc_base;
- gicv2_driver_init(&ls_gic_data);
- gicv2_distif_init();
- gicv2_pcpu_distif_init();
- gicv2_cpuif_enable();
-
-#if RESET_TO_BL31
- /*
- * Do initial security configuration to allow DRAM/device access
- * (if earlier BL has not already done so).
- */
- plat_ls_security_setup();
-
-#endif /* RESET_TO_BL31 */
-
- /* Enable and initialize the System level generic timer */
- mmio_write_32(LS1043_SYS_CNTCTL_BASE + CNTCR_OFF,
- CNTCR_FCREQ(0U) | CNTCR_EN);
-
- VERBOSE("Leave arm_bl31_platform_setup\n");
-}
-
-/*******************************************************************************
- * Perform any BL31 platform runtime setup prior to BL31 exit common to Layerscape
- * platforms
- ******************************************************************************/
-void ls_bl31_plat_runtime_setup(void)
-{
- static console_t console;
-
- /* Initialize the runtime console */
- console_ls_16550_register(PLAT_LS1043_UART_BASE, PLAT_LS1043_UART_CLOCK,
- PLAT_LS1043_UART_BAUDRATE, &console);
-}
-
-void bl31_platform_setup(void)
-{
- ls_bl31_platform_setup();
-}
-
-void bl31_plat_runtime_setup(void)
-{
- ls_bl31_plat_runtime_setup();
-}
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup shared between
- * Layerscape platforms. This only does basic initialization. Later
- * architectural setup (bl31_arch_setup()) does not do anything platform
- * specific.
- ******************************************************************************/
-void ls_bl31_plat_arch_setup(void)
-{
- ls_setup_page_tables(BL31_BASE,
- BL31_END - BL31_BASE,
- BL_CODE_BASE,
- BL_CODE_END,
- BL_RO_DATA_BASE,
- BL_RO_DATA_END
-#if USE_COHERENT_MEM
- , BL_COHERENT_RAM_BASE,
- BL_COHERENT_RAM_END
-#endif
- );
- enable_mmu_el3(0);
-}
-
-void bl31_plat_arch_setup(void)
-{
- ls_bl31_plat_arch_setup();
-}
diff --git a/plat/layerscape/common/ls_common.c b/plat/layerscape/common/ls_common.c
deleted file mode 100644
index 23c0d00..0000000
--- a/plat/layerscape/common/ls_common.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <lib/mmio.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-
-const mmap_region_t *plat_ls_get_mmap(void);
-
-/*
- * Table of memory regions for various BL stages to map using the MMU.
- * This doesn't include Trusted SRAM as ls_setup_page_tables() already
- * takes care of mapping it.
- *
- * The flash needs to be mapped as writable in order to erase the FIP's Table of
- * Contents in case of unrecoverable error (see plat_error_handler()).
- */
-#ifdef IMAGE_BL1
-const mmap_region_t plat_ls_mmap[] = {
- LS_MAP_FLASH0_RW,
- LS_MAP_NS_DRAM,
- LS_MAP_CCSR,
- {0}
-};
-#endif
-#ifdef IMAGE_BL2
-const mmap_region_t plat_ls_mmap[] = {
- LS_MAP_FLASH0_RW,
- LS_MAP_CCSR,
- LS_MAP_NS_DRAM,
- LS_MAP_TSP_SEC_MEM,
- {0}
-};
-#endif
-#ifdef IMAGE_BL31
-const mmap_region_t plat_ls_mmap[] = {
- LS_MAP_CCSR,
- LS_MAP_FLASH0_RW,
- LS_MAP_NS_DRAM,
- LS_MAP_TSP_SEC_MEM,
- {0}
-};
-#endif
-#ifdef IMAGE_BL32
-const mmap_region_t plat_ls_mmap[] = {
- LS_MAP_CCSR,
- LS_MAP_FLASH0_RW,
- LS_MAP_TSP_SEC_MEM,
- {0}
-};
-#endif
-/*
- * Set up the page tables for the generic and platform-specific memory regions.
- * The extents of the generic memory regions are specified by the function
- * arguments and consist of:
- * - Trusted SRAM seen by the BL image;
- * - Code section;
- * - Read-only data section;
- * - Coherent memory region, if applicable.
- */
-void ls_setup_page_tables(uintptr_t total_base,
- size_t total_size,
- uintptr_t code_start,
- uintptr_t code_limit,
- uintptr_t rodata_start,
- uintptr_t rodata_limit
-#if USE_COHERENT_MEM
- ,
- uintptr_t coh_start,
- uintptr_t coh_limit
-#endif
- )
-{
- /* Now (re-)map the platform-specific memory regions */
- mmap_add(plat_ls_get_mmap());
- /*
- * Map the Trusted SRAM with appropriate memory attributes.
- * Subsequent mappings will adjust the attributes for specific regions.
- */
- VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
- (void *) total_base, (void *) (total_base + total_size));
- mmap_add_region(total_base, total_base,
- total_size,
- MT_MEMORY | MT_RW | MT_SECURE);
-
- /* Re-map the code section */
- VERBOSE("Code region: %p - %p\n",
- (void *) code_start, (void *) code_limit);
- mmap_add_region(code_start, code_start,
- code_limit - code_start,
- MT_CODE | MT_SECURE);
-
- /* Re-map the read-only data section */
- VERBOSE("Read-only data region: %p - %p\n",
- (void *) rodata_start, (void *) rodata_limit);
- mmap_add_region(rodata_start, rodata_start,
- rodata_limit - rodata_start,
- MT_RO_DATA | MT_SECURE);
-
-#if USE_COHERENT_MEM
- /* Re-map the coherent memory region */
- VERBOSE("Coherent region: %p - %p\n",
- (void *) coh_start, (void *) coh_limit);
- mmap_add_region(coh_start, coh_start,
- coh_limit - coh_start,
- MT_DEVICE | MT_RW | MT_SECURE);
-#endif
-
- /* Create the page tables to reflect the above mappings */
- init_xlat_tables();
-}
-
-uintptr_t plat_get_ns_image_entrypoint(void)
-{
-#ifdef PRELOADED_BL33_BASE
- return PRELOADED_BL33_BASE;
-#else
- return LS_NS_DRAM_BASE;
-#endif
-}
-
-/*******************************************************************************
- * Gets SPSR for BL32 entry
- ******************************************************************************/
-uint32_t ls_get_spsr_for_bl32_entry(void)
-{
- /*
- * The Secure Payload Dispatcher service is responsible for
- * setting the SPSR prior to entry into the BL32 image.
- */
- return 0;
-}
-
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-#ifdef __aarch64__
-uint32_t ls_get_spsr_for_bl33_entry(void)
-{
- unsigned int mode;
- uint32_t spsr;
-
- /* Figure out what mode we enter the non-secure world in */
- mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
-
- /*
- * TODO: Consider the possibility of specifying the SPSR in
- * the FIP ToC and allowing the platform to have a say as
- * well.
- */
- spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
- return spsr;
-}
-#else
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-uint32_t ls_get_spsr_for_bl33_entry(void)
-{
- unsigned int hyp_status, mode, spsr;
-
- hyp_status = GET_VIRT_EXT(read_id_pfr1());
-
- mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
-
- /*
- * TODO: Consider the possibility of specifying the SPSR in
- * the FIP ToC and allowing the platform to have a say as
- * well.
- */
- spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
- SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
- return spsr;
-}
-#endif /* __aarch64__ */
-
-/*******************************************************************************
- * Returns Layerscape platform specific memory map regions.
- ******************************************************************************/
-const mmap_region_t *plat_ls_get_mmap(void)
-{
- return plat_ls_mmap;
-}
-
-
-unsigned int plat_get_syscnt_freq2(void)
-{
- unsigned int counter_base_frequency;
-
- counter_base_frequency = COUNTER_FREQUENCY;
-
- return counter_base_frequency;
-}
diff --git a/plat/layerscape/common/ls_common.mk b/plat/layerscape/common/ls_common.mk
deleted file mode 100644
index 39867e6..0000000
--- a/plat/layerscape/common/ls_common.mk
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-
-# Process LS1043_DISABLE_TRUSTED_WDOG flag
-# TODO:Temparally disabled it on development phase, not implemented yet
-LS1043_DISABLE_TRUSTED_WDOG := 1
-
-# On Layerscape platforms, separate the code and read-only data sections to allow
-# mapping the former as executable and the latter as execute-never.
-SEPARATE_CODE_AND_RODATA := 1
-
-COLD_BOOT_SINGLE_CPU := 1
-
-PLAT_BL_COMMON_SOURCES += plat/layerscape/common/${ARCH}/ls_helpers.S \
- plat/layerscape/common/ls_common.c
-
-include lib/xlat_tables_v2/xlat_tables.mk
-
-PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
-
-BL1_SOURCES += \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- drivers/io/io_storage.c \
- plat/layerscape/common/ls_timer.c \
- plat/layerscape/common/ls_bl1_setup.c \
- plat/layerscape/common/ls_io_storage.c
-
-BL2_SOURCES += drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- drivers/io/io_storage.c \
- plat/layerscape/common/ls_timer.c \
- plat/layerscape/common/ls_bl2_setup.c \
- plat/layerscape/common/ls_io_storage.c
-BL2_SOURCES += plat/layerscape/common/${ARCH}/ls_bl2_mem_params_desc.c
-BL2_SOURCES += plat/layerscape/common/ls_image_load.c \
- common/desc_image_load.c
-
-BL31_SOURCES += plat/layerscape/common/ls_bl31_setup.c \
- plat/layerscape/common/ls_timer.c \
- plat/layerscape/common/ls_topology.c \
- plat/layerscape/common/ns_access.c \
- plat/common/plat_psci_common.c
diff --git a/plat/layerscape/common/ls_image_load.c b/plat/layerscape/common/ls_image_load.c
deleted file mode 100644
index 70c01f2..0000000
--- a/plat/layerscape/common/ls_image_load.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/desc_image_load.h>
-
-#include "ls_def.h"
-
-/*******************************************************************************
- * This function flushes the data structures so that they are visible
- * in memory for the next BL image.
- ******************************************************************************/
-void plat_flush_next_bl_params(void)
-{
- flush_bl_params_desc();
-}
-
-/*******************************************************************************
- * This function returns the list of loadable images.
- ******************************************************************************/
-bl_load_info_t *plat_get_bl_image_load_info(void)
-{
- return get_bl_load_info_from_mem_params_desc();
-}
-
-/*******************************************************************************
- * This function returns the list of executable images.
- ******************************************************************************/
-bl_params_t *plat_get_next_bl_params(void)
-{
- return get_next_bl_params_from_mem_params_desc();
-}
diff --git a/plat/layerscape/common/ls_io_storage.c b/plat/layerscape/common/ls_io_storage.c
deleted file mode 100644
index 71c2f45..0000000
--- a/plat/layerscape/common/ls_io_storage.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_fip.h>
-#include <drivers/io/io_memmap.h>
-#include <drivers/io/io_storage.h>
-#include <tools_share/firmware_image_package.h>
-
-/* IO devices */
-static const io_dev_connector_t *fip_dev_con;
-static uintptr_t fip_dev_handle;
-static const io_dev_connector_t *memmap_dev_con;
-static uintptr_t memmap_dev_handle;
-
-static const io_block_spec_t fip_block_spec = {
- .offset = PLAT_LS_FIP_BASE,
- .length = PLAT_LS_FIP_MAX_SIZE
-};
-
-static const io_uuid_spec_t bl2_uuid_spec = {
- .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
-};
-
-static const io_uuid_spec_t bl31_uuid_spec = {
- .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
-};
-
-static const io_uuid_spec_t bl32_uuid_spec = {
- .uuid = UUID_SECURE_PAYLOAD_BL32,
-};
-
-static const io_uuid_spec_t bl33_uuid_spec = {
- .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
-};
-
-static int open_fip(const uintptr_t spec);
-static int open_memmap(const uintptr_t spec);
-
-struct plat_io_policy {
- uintptr_t *dev_handle;
- uintptr_t image_spec;
- int (*check)(const uintptr_t spec);
-};
-
-static const struct plat_io_policy policies[] = {
- [FIP_IMAGE_ID] = {
- &memmap_dev_handle,
- (uintptr_t)&fip_block_spec,
- open_memmap
- },
- [BL2_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl2_uuid_spec,
- open_fip
- },
- [BL31_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl31_uuid_spec,
- open_fip
- },
- [BL32_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl32_uuid_spec,
- open_fip
- },
- [BL33_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl33_uuid_spec,
- open_fip
- },
-};
-
-static int open_fip(const uintptr_t spec)
-{
- int result;
- uintptr_t local_image_handle;
-
- /* See if a Firmware Image Package is available */
- result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
- if (result == 0) {
- result = io_open(fip_dev_handle, spec, &local_image_handle);
- if (result == 0) {
- VERBOSE("Using FIP\n");
- io_close(local_image_handle);
- }
- }
- return result;
-}
-
-
-static int open_memmap(const uintptr_t spec)
-{
- int result;
- uintptr_t local_image_handle;
-
- result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
- if (result == 0) {
- result = io_open(memmap_dev_handle, spec, &local_image_handle);
- if (result == 0) {
- VERBOSE("Using Memmap\n");
- io_close(local_image_handle);
- }
- }
- return result;
-}
-
-
-void ls_io_setup(void)
-{
- int io_result;
-
- io_result = register_io_dev_fip(&fip_dev_con);
- assert(io_result == 0);
-
- io_result = register_io_dev_memmap(&memmap_dev_con);
- assert(io_result == 0);
-
- /* Open connections to devices and cache the handles */
- io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
- &fip_dev_handle);
- assert(io_result == 0);
-
- io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
- &memmap_dev_handle);
- assert(io_result == 0);
-
- /* Ignore improbable errors in release builds */
- (void)io_result;
-}
-
-void plat_ls_io_setup(void)
-{
- ls_io_setup();
-}
-
-int plat_ls_get_alt_image_source(
- unsigned int image_id __unused,
- uintptr_t *dev_handle __unused,
- uintptr_t *image_spec __unused)
-{
- /* By default do not try an alternative */
- return -ENOENT;
-}
-
-/*
- * Return an IO device handle and specification which can be used to access
- * an image. Use this to enforce platform load policy.
- */
-int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
- uintptr_t *image_spec)
-{
- int result;
- const struct plat_io_policy *policy;
-
- assert(image_id < ARRAY_SIZE(policies));
-
- policy = &policies[image_id];
- result = policy->check(policy->image_spec);
- if (result == 0) {
- *image_spec = policy->image_spec;
- *dev_handle = *(policy->dev_handle);
- } else {
- VERBOSE("Trying alternative IO\n");
- result = plat_ls_get_alt_image_source(image_id, dev_handle,
- image_spec);
- }
-
- return result;
-}
diff --git a/plat/layerscape/common/ls_timer.c b/plat/layerscape/common/ls_timer.c
deleted file mode 100644
index 021890b..0000000
--- a/plat/layerscape/common/ls_timer.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <drivers/delay_timer.h>
-#include <lib/mmio.h>
-
-#define TIMER_BASE_ADDR 0x02B00000
-
-uint64_t ls_get_timer(uint64_t start)
-{
- return read_cntpct_el0() * 1000 / read_cntfrq_el0() - start;
-}
-
-static uint32_t ls_timeus_get_value(void)
-{
- /*
- * Generic delay timer implementation expects the timer to be a down
- * counter. We apply bitwise NOT operator to the tick values returned
- * by read_cntpct_el0() to simulate the down counter. The value is
- * clipped from 64 to 32 bits.
- */
- return (uint32_t)(~read_cntpct_el0());
-}
-
-static const timer_ops_t ls_timer_ops = {
- .get_timer_value = ls_timeus_get_value,
- .clk_mult = 1,
- .clk_div = 25,
-};
-
-
-/*
- * Initialise the nxp layerscape on-chip free rolling us counter as the delay
- * timer.
- */
-void ls_delay_timer_init(void)
-{
- uintptr_t cntcr = TIMER_BASE_ADDR;
-
- mmio_write_32(cntcr, 0x1);
-
- timer_init(&ls_timer_ops);
-}
diff --git a/plat/layerscape/common/ls_topology.c b/plat/layerscape/common/ls_topology.c
deleted file mode 100644
index 5b76087..0000000
--- a/plat/layerscape/common/ls_topology.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "plat_ls.h"
-
-/*******************************************************************************
- * This function validates an MPIDR by checking whether it falls within the
- * acceptable bounds. An error code (-1) is returned if an incorrect mpidr
- * is passed.
- ******************************************************************************/
-int ls_check_mpidr(u_register_t mpidr)
-{
- unsigned int cluster_id, cpu_id;
- uint64_t valid_mask;
-
- valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK);
- cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
- cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
-
- mpidr &= MPIDR_AFFINITY_MASK;
- if (mpidr & valid_mask)
- return -1;
-
- if (cluster_id >= PLAT_LS_CLUSTER_COUNT)
- return -1;
-
- /*
- * Validate cpu_id by checking whether it represents a CPU in
- * one of the two clusters present on the platform.
- */
- if (cpu_id >= plat_ls_get_cluster_core_count(mpidr))
- return -1;
-
-
- return 0;
-}
diff --git a/plat/layerscape/common/ls_tzc380.c b/plat/layerscape/common/ls_tzc380.c
deleted file mode 100644
index 44f3fcd..0000000
--- a/plat/layerscape/common/ls_tzc380.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <endian.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "soc_tzasc.h"
-
-int tzc380_set_region(unsigned int tzasc_base, unsigned int region_id,
- unsigned int enabled, unsigned int low_addr,
- unsigned int high_addr, unsigned int size,
- unsigned int security, unsigned int subreg_disable_mask)
-{
- unsigned int reg;
- unsigned int reg_base;
- unsigned int attr_value;
-
- reg_base = (tzasc_base + TZASC_REGIONS_REG + (region_id << 4));
-
- if (region_id == 0) {
- reg = (reg_base + TZASC_REGION_ATTR_OFFSET);
- mmio_write_32((uintptr_t)reg, ((security & 0xF) << 28));
- } else {
- reg = reg_base + TZASC_REGION_LOWADDR_OFFSET;
- mmio_write_32((uintptr_t)reg,
- (low_addr & TZASC_REGION_LOWADDR_MASK));
-
- reg = reg_base + TZASC_REGION_HIGHADDR_OFFSET;
- mmio_write_32((uintptr_t)reg, high_addr);
-
- reg = reg_base + TZASC_REGION_ATTR_OFFSET;
- attr_value = ((security & 0xF) << 28) |
- ((subreg_disable_mask & 0xFF) << 8) |
- ((size & 0x3F) << 1) | (enabled & 0x1);
- mmio_write_32((uintptr_t)reg, attr_value);
-
- }
- return 0;
-}
-
-int tzc380_setup(void)
-{
- int reg_id = 0;
-
- INFO("Configuring TZASC-380\n");
-
- /*
- * Configure CCI control override register to terminate all barrier
- * transactions
- */
- mmio_write_32(PLAT_LS1043_CCI_BASE, CCI_TERMINATE_BARRIER_TX);
-
- /* Configure CSU secure access register to disable TZASC bypass mux */
- mmio_write_32((uintptr_t)(CONFIG_SYS_FSL_CSU_ADDR +
- CSU_SEC_ACCESS_REG_OFFSET),
- bswap32(TZASC_BYPASS_MUX_DISABLE));
-
- for (reg_id = 0; reg_id < MAX_NUM_TZC_REGION; reg_id++) {
- tzc380_set_region(CONFIG_SYS_FSL_TZASC_ADDR,
- reg_id,
- tzc380_reg_list[reg_id].enabled,
- tzc380_reg_list[reg_id].low_addr,
- tzc380_reg_list[reg_id].high_addr,
- tzc380_reg_list[reg_id].size,
- tzc380_reg_list[reg_id].secure,
- tzc380_reg_list[reg_id].sub_mask);
- }
-
- return 0;
-}
diff --git a/plat/layerscape/common/ns_access.c b/plat/layerscape/common/ns_access.c
deleted file mode 100644
index 9717c72..0000000
--- a/plat/layerscape/common/ns_access.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <endian.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "ns_access.h"
-
-static void enable_devices_ns_access(struct csu_ns_dev *_ns_dev, uint32_t num)
-{
- uint32_t *base = (uint32_t *)CONFIG_SYS_FSL_CSU_ADDR;
- uint32_t *reg;
- uint32_t val;
- int i;
-
- for (i = 0; i < num; i++) {
- reg = base + _ns_dev[i].ind / 2;
- val = be32toh(mmio_read_32((uintptr_t)reg));
- if (_ns_dev[i].ind % 2 == 0) {
- val &= 0x0000ffff;
- val |= _ns_dev[i].val << 16;
- } else {
- val &= 0xffff0000;
- val |= _ns_dev[i].val;
- }
- mmio_write_32((uintptr_t)reg, htobe32(val));
- }
-}
-
-void enable_layerscape_ns_access(void)
-{
- enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
-}
diff --git a/plat/layerscape/common/tsp/ls_tsp.mk b/plat/layerscape/common/tsp/ls_tsp.mk
deleted file mode 100644
index 7cb9781..0000000
--- a/plat/layerscape/common/tsp/ls_tsp.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# TSP source files common to ARM standard platforms
-BL32_SOURCES += plat/layerscape/common/ls_topology.c \
- plat/layerscape/common/tsp/ls_tsp_setup.c \
- plat/common/aarch64/platform_mp_stack.S
diff --git a/plat/layerscape/common/tsp/ls_tsp_setup.c b/plat/layerscape/common/tsp/ls_tsp_setup.c
deleted file mode 100644
index 969d0b8..0000000
--- a/plat/layerscape/common/tsp/ls_tsp_setup.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <common/interrupt_props.h>
-#include <drivers/arm/gicv2.h>
-
-#include "ls_16550.h"
-#include "plat_ls.h"
-#include "soc.h"
-
-static const interrupt_prop_t g0_interrupt_props[] = {
- INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
-};
-
-gicv2_driver_data_t ls_gic_data = {
- .gicd_base = GICD_BASE,
- .gicc_base = GICC_BASE,
- .interrupt_props = g0_interrupt_props,
- .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
-};
-
-/*******************************************************************************
- * Initialize the UART
- ******************************************************************************/
-void ls_tsp_early_platform_setup(void)
-{
- static console_t console;
- /*
- * Initialize a different console than already in use to display
- * messages from TSP
- */
- console_ls_16550_register(PLAT_LS1043_UART2_BASE, PLAT_LS1043_UART_CLOCK,
- PLAT_LS1043_UART_BAUDRATE, &console);
- NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL32);
-}
-
-/*******************************************************************************
- * Perform platform specific setup placeholder
- ******************************************************************************/
-void tsp_platform_setup(void)
-{
- uint32_t gicc_base, gicd_base;
-
- /* Initialize the GIC driver, cpu and distributor interfaces */
- get_gic_offset(&gicc_base, &gicd_base);
- ls_gic_data.gicd_base = (uintptr_t)gicd_base;
- ls_gic_data.gicc_base = (uintptr_t)gicc_base;
- gicv2_driver_init(&ls_gic_data);
- gicv2_distif_init();
- gicv2_pcpu_distif_init();
- gicv2_cpuif_enable();
-}
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the MMU
- ******************************************************************************/
-void tsp_plat_arch_setup(void)
-{
- ls_setup_page_tables(BL32_BASE,
- (BL32_END - BL32_BASE),
- BL_CODE_BASE,
- BL_CODE_END,
- BL_RO_DATA_BASE,
- BL_RO_DATA_END
-#if USE_COHERENT_MEM
- , BL_COHERENT_RAM_BASE,
- BL_COHERENT_RAM_END
-#endif
- );
- enable_mmu_el1(0);
-}
diff --git a/plat/layerscape/common/tsp/platform_tsp.h b/plat/layerscape/common/tsp/platform_tsp.h
deleted file mode 100644
index 260f66a..0000000
--- a/plat/layerscape/common/tsp/platform_tsp.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_TSP_H
-#define PLATFORM_TSP_H
-
-/*******************************************************************************
- * Mandatory TSP functions (only if platform contains a TSP)
- ******************************************************************************/
-void tsp_early_platform_setup(void);
-void tsp_plat_arch_setup(void);
-void tsp_platform_setup(void);
-
-#endif /* PLATFORM_TSP_H */
diff --git a/plat/nxp/common/aarch64/ls_helpers.S b/plat/nxp/common/aarch64/ls_helpers.S
index 19ea9e5..311dce1 100644
--- a/plat/nxp/common/aarch64/ls_helpers.S
+++ b/plat/nxp/common/aarch64/ls_helpers.S
@@ -6,6 +6,7 @@
*/
#include <asm_macros.S>
+#include <cortex_a53.h>
#include <drivers/console.h>
#include <lib/cpus/aarch64/cortex_a72.h>
@@ -156,6 +157,31 @@
#endif
/* this function disables the load-store prefetch of the calling core
+ * Note: this function is for A53 cores ONLY
+ * in: none
+ * out: none
+ * uses x0
+ */
+func _disable_ldstr_pfetch_A53
+ mrs x0, CORTEX_A53_CPUACTLR_EL1
+ tst x0, #CORTEX_A53_CPUACTLR_EL1_L1PCTL
+ b.ne 1f
+ b 2f
+
+.align 6
+1:
+ dsb sy
+ isb
+ bic x0, x0, #CORTEX_A53_CPUACTLR_EL1_L1PCTL
+ msr CORTEX_A53_CPUACTLR_EL1, x0
+ isb
+
+2:
+ ret
+endfunc _disable_ldstr_pfetch_A53
+
+
+/* this function disables the load-store prefetch of the calling core
* Note: this function is for A72 cores ONLY
* in: none
* out: none
diff --git a/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h b/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h
index 175a796..6296aef 100644
--- a/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h
+++ b/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h
@@ -32,6 +32,7 @@
#define NXP_SFP_ADDR 0x01E80000
#define NXP_RCPM_ADDR 0x01EE2000
#define NXP_CSU_ADDR 0x01510000
+#define NXP_IFC_ADDR 0x01530000
#define NXP_SCFG_ADDR 0x01570000
#define NXP_DCSR_ADDR 0x20000000
#define NXP_DCSR_DCFG_ADDR (NXP_DCSR_ADDR + 0x00140000)
diff --git a/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
index 84f07e6..928ac05 100644
--- a/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
+++ b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
@@ -56,6 +56,23 @@
#define RCPM_POWMGTCSR_OFFSET 0x130
#define RCPM_IPPDEXPCR0_OFFSET 0x140
#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
+
+#define RCPM2_IPSTPCR0_OFFSET 0x8
+#define RCPM2_IPSTPCR1_OFFSET 0xC
+#define RCPM2_IPSTPCR2_OFFSET 0x10
+#define RCPM2_IPSTPCR3_OFFSET 0x14
+#define RCPM2_IPSTPCR4_OFFSET 0x28
+
+#define RCPM2_IPSTPACKR0_OFFSET 0x18
+#define RCPM2_IPSTPACKR1_OFFSET 0x1C
+#define RCPM2_IPSTPACKR2_OFFSET 0x20
+#define RCPM2_IPSTPACKR3_OFFSET 0x24
+#define RCPM2_IPSTPACKR4_OFFSET 0x2C
+#define RCPM2_POWMGTDCR_OFFSET 0x0
+
+/* bitfield masks */
+#define POWMGTDCR_OVRD_EN 0x80000000
+
#endif /* NXP_RCPM_ADDR */
#define DCFG_SBEESR2_ADDR 0x20140534
diff --git a/plat/nxp/common/setup/include/plat_common.h b/plat/nxp/common/setup/include/plat_common.h
index 97a9cb7..e13f45c 100644
--- a/plat/nxp/common/setup/include/plat_common.h
+++ b/plat/nxp/common/setup/include/plat_common.h
@@ -113,7 +113,7 @@
typedef struct {
uint64_t num_dram_regions;
- uint64_t total_dram_size;
+ int64_t total_dram_size;
region_info_t region[NUM_DRAM_REGIONS];
} dram_regions_info_t;
@@ -131,9 +131,11 @@
#endif
);
+#define SOC_NAME_MAX_LEN (20)
+
/* Structure to define SoC personality */
struct soc_type {
- char name[10];
+ char name[SOC_NAME_MAX_LEN];
uint32_t version;
uint8_t num_clusters;
uint8_t cores_per_cluster;
diff --git a/plat/nxp/common/setup/ls_bl2_el3_setup.c b/plat/nxp/common/setup/ls_bl2_el3_setup.c
index 6428eb9..5b5144d 100644
--- a/plat/nxp/common/setup/ls_bl2_el3_setup.c
+++ b/plat/nxp/common/setup/ls_bl2_el3_setup.c
@@ -279,10 +279,12 @@
soc_preload_setup();
- if (dram_regions_info.total_dram_size < NXP_DRAM0_SIZE) {
- NOTICE("ERROR: DRAM0 Size is not correctly configured.");
+#ifdef DDR_INIT
+ if (dram_regions_info.total_dram_size <= 0) {
+ ERROR("Asserting as the DDR is not initialized yet.");
assert(false);
}
+#endif
if ((dram_regions_info.region[0].addr == 0)
&& (dram_regions_info.total_dram_size > 0)) {
diff --git a/plat/nxp/common/setup/ls_io_storage.c b/plat/nxp/common/setup/ls_io_storage.c
index 0c01765..7f01e72 100644
--- a/plat/nxp/common/setup/ls_io_storage.c
+++ b/plat/nxp/common/setup/ls_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -19,6 +19,12 @@
#ifdef FLEXSPI_NOR_BOOT
#include <flexspi_nor.h>
#endif
+#if defined(NAND_BOOT)
+#include <ifc_nand.h>
+#endif
+#if defined(NOR_BOOT)
+#include <ifc_nor.h>
+#endif
#if defined(QSPI_BOOT)
#include <qspi.h>
#endif
@@ -263,7 +269,7 @@
return result;
}
-#if defined(SD_BOOT) || defined(EMMC_BOOT)
+#if defined(SD_BOOT) || defined(EMMC_BOOT) || defined(NAND_BOOT)
static int plat_io_block_setup(size_t fip_offset, uintptr_t block_dev_spec)
{
int io_result;
@@ -282,7 +288,7 @@
}
#endif
-#if defined(FLEXSPI_NOR_BOOT) || defined(QSPI_BOOT)
+#if defined(FLEXSPI_NOR_BOOT) || defined(QSPI_BOOT) || defined(NOR_BOOT)
static int plat_io_memmap_setup(size_t fip_offset)
{
int io_result;
@@ -401,20 +407,51 @@
int ifc_nor_io_setup(void)
{
+#if defined(NOR_BOOT)
+ int ret;
+
+ ret = ifc_nor_init(NXP_NOR_FLASH_ADDR,
+ NXP_NOR_FLASH_SIZE);
+
+ if (ret != 0) {
+ return ret;
+ }
+
+ return plat_io_memmap_setup(NXP_NOR_FLASH_ADDR + PLAT_FIP_OFFSET);
+#else
ERROR("NOR driver not present. Check your BUILD\n");
/* Should never reach here */
assert(false);
return -1;
+#endif
}
int ifc_nand_io_setup(void)
{
+#if defined(NAND_BOOT)
+ uintptr_t block_dev_spec;
+ int ret;
+
+ ret = ifc_nand_init(&block_dev_spec,
+ NXP_IFC_REGION_ADDR,
+ NXP_IFC_ADDR,
+ NXP_IFC_SRAM_BUFFER_SIZE,
+ NXP_SD_BLOCK_BUF_ADDR,
+ NXP_SD_BLOCK_BUF_SIZE);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return plat_io_block_setup(PLAT_FIP_OFFSET, block_dev_spec);
+#else
+
ERROR("NAND driver not present. Check your BUILD\n");
/* Should never reach here */
assert(false);
return -1;
+#endif
}
int ls_flexspi_nor_io_setup(void)
diff --git a/plat/nxp/common/soc_errata/errata.c b/plat/nxp/common/soc_errata/errata.c
index fb1818a..a117c91 100644
--- a/plat/nxp/common/soc_errata/errata.c
+++ b/plat/nxp/common/soc_errata/errata.c
@@ -15,6 +15,10 @@
INFO("SoC workaround for Errata A050426 was applied\n");
erratum_a050426();
#endif
+#ifdef ERRATA_SOC_A008850
+ INFO("SoC workaround for Errata A008850 Early-Phase was applied\n");
+ erratum_a008850_early();
+#endif
/*
* The following DDR Erratas workaround are implemented in DDR driver,
* but print information here.
diff --git a/plat/nxp/common/soc_errata/errata.h b/plat/nxp/common/soc_errata/errata.h
index b543b4b..ab67995 100644
--- a/plat/nxp/common/soc_errata/errata.h
+++ b/plat/nxp/common/soc_errata/errata.h
@@ -8,6 +8,8 @@
#ifndef ERRATA_H
#define ERRATA_H
+#include "errata_list.h"
+
void soc_errata(void);
#endif /* ERRATA_H */
diff --git a/plat/nxp/common/soc_errata/errata.mk b/plat/nxp/common/soc_errata/errata.mk
index 2942615..d2511bb 100644
--- a/plat/nxp/common/soc_errata/errata.mk
+++ b/plat/nxp/common/soc_errata/errata.mk
@@ -8,7 +8,8 @@
# applied.
ERRATA := \
- ERRATA_SOC_A050426
+ ERRATA_SOC_A050426 \
+ ERRATA_SOC_A008850
define enable_errata
$(1) ?= 0
diff --git a/plat/nxp/common/soc_errata/errata_a008850.c b/plat/nxp/common/soc_errata/errata_a008850.c
new file mode 100644
index 0000000..e8c0f64
--- /dev/null
+++ b/plat/nxp/common/soc_errata/errata_a008850.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <cci.h>
+#include <common/debug.h>
+#include <ls_interconnect.h>
+#include <mmio.h>
+
+#include <platform_def.h>
+
+void erratum_a008850_early(void)
+{
+ /* part 1 of 2 */
+ uintptr_t cci_base = NXP_CCI_ADDR;
+ uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
+
+ /* enabling forced barrier termination on CCI400 */
+ mmio_write_32(cci_base + CTRL_OVERRIDE_REG,
+ (val | CCI_TERMINATE_BARRIER_TX));
+
+}
+
+void erratum_a008850_post(void)
+{
+ /* part 2 of 2 */
+ uintptr_t cci_base = NXP_CCI_ADDR;
+ uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
+
+ /* Clear the BARRIER_TX bit */
+ val = val & ~(CCI_TERMINATE_BARRIER_TX);
+
+ /*
+ * Disable barrier termination on CCI400, allowing
+ * barriers to propagate across CCI
+ */
+ mmio_write_32(cci_base + CTRL_OVERRIDE_REG, val);
+
+ INFO("SoC workaround for Errata A008850 Post-Phase was applied\n");
+}
diff --git a/plat/nxp/common/soc_errata/errata_list.h b/plat/nxp/common/soc_errata/errata_list.h
index 74d2315..ae95fa2 100644
--- a/plat/nxp/common/soc_errata/errata_list.h
+++ b/plat/nxp/common/soc_errata/errata_list.h
@@ -12,4 +12,9 @@
void erratum_a050426(void);
#endif
+#ifdef ERRATA_SOC_A008850
+void erratum_a008850_early(void);
+void erratum_a008850_post(void);
+#endif
+
#endif /* ERRATA_LIST_H */
diff --git a/plat/nxp/soc-ls1028a/soc.c b/plat/nxp/soc-ls1028a/soc.c
index edfd657..2fb353f 100644
--- a/plat/nxp/soc-ls1028a/soc.c
+++ b/plat/nxp/soc-ls1028a/soc.c
@@ -23,9 +23,6 @@
#include <nxp_smmu.h>
#endif
#include <nxp_timer.h>
-#ifdef CONFIG_OCRAM_ECC_EN
-#include <ocram.h>
-#endif
#include <plat_console.h>
#include <plat_gic.h>
#include <plat_tzc400.h>
@@ -36,6 +33,9 @@
#endif
#include <errata.h>
+#ifdef CONFIG_OCRAM_ECC_EN
+#include <ocram.h>
+#endif
#include "plat_common.h"
#include "platform_def.h"
#include "soc.h"
diff --git a/plat/nxp/soc-ls1043a/aarch64/ls1043a.S b/plat/nxp/soc-ls1043a/aarch64/ls1043a.S
new file mode 100644
index 0000000..a1baf79
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/aarch64/ls1043a.S
@@ -0,0 +1,1637 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <cortex_a53.h>
+#include <dcfg_lsch2.h>
+#include <plat_gic.h>
+#include <scfg.h>
+
+#include <bl31_data.h>
+#include <plat_psci.h>
+#include <platform_def.h>
+
+/* the BASE address for these offsets is AUX_01_DATA in the */
+/* bootcore's psci data region */
+#define DEVDISR2_MASK_OFFSET 0x0 /* references AUX_01_DATA */
+#define DEVDISR5_MASK_OFFSET 0x8 /* references AUX_02_DATA */
+#define CPUACTLR_DATA_OFFSET 0x10 /* references AUX_03_DATA */
+/* the BASE address for these offsets is AUX_04_DATA in the */
+/* bootcore's psci data region */
+#define GICD_BASE_ADDR_OFFSET 0x0 /* references AUX_04_DATA */
+#define GICC_BASE_ADDR_OFFSET 0x8 /* references AUX_05_DATA */
+
+#define DAIF_DATA AUX_06_DATA /* references AUX_06_DATA */
+
+#define IPSTPACK_RETRY_CNT 0x10000
+#define DDR_SLEEP_RETRY_CNT 0x10000
+#define CPUACTLR_EL1 S3_1_C15_C2_0
+#define DDR_SDRAM_CFG_2_FRCSR 0x80000000
+#define DDR_SDRAM_CFG_2_OFFSET 0x114
+#define DDR_TIMING_CFG_4_OFFSET 0x160
+#define DDR_CNTRL_BASE_ADDR 0x01080000
+
+#define DLL_LOCK_MASK 0x3
+#define DLL_LOCK_VALUE 0x2
+
+#define ERROR_DDR_SLEEP -1
+#define ERROR_DDR_WAKE -2
+#define ERROR_NO_QUIESCE -3
+
+#define CORE_RESTARTABLE 0
+#define CORE_NOT_RESTARTABLE 1
+
+#define RESET_RETRY_CNT 800
+
+.global soc_init_lowlevel
+.global soc_init_percpu
+.global _soc_core_release
+.global _soc_core_restart
+.global _soc_ck_disabled
+.global _soc_sys_reset
+.global _soc_sys_off
+.global _getGICD_BaseAddr
+.global _getGICC_BaseAddr
+.global _soc_set_start_addr
+.global _soc_core_prep_off
+.global _soc_core_entr_off
+.global _soc_core_exit_off
+.global _soc_core_prep_stdby
+.global _soc_core_entr_stdby
+.global _soc_core_exit_stdby
+.global _soc_core_prep_pwrdn
+.global _soc_core_entr_pwrdn
+.global _soc_core_exit_pwrdn
+.global _soc_clstr_prep_stdby
+.global _soc_clstr_exit_stdby
+.global _soc_clstr_prep_pwrdn
+.global _soc_clstr_exit_pwrdn
+.global _soc_sys_prep_stdby
+.global _soc_sys_exit_stdby
+.global _soc_sys_prep_pwrdn
+.global _soc_sys_pwrdn_wfi
+.global _soc_sys_exit_pwrdn
+
+/*
+ * This function initialize the soc.
+ * in: void
+ * out: void
+ */
+func soc_init_lowlevel
+ ret
+endfunc soc_init_lowlevel
+
+/*
+ * void soc_init_percpu(void)
+ * this function performs any soc-specific initialization that is needed on
+ * a per-core basis
+ * in: none
+ * out: none
+ * uses x0, x1, x2, x3
+ */
+func soc_init_percpu
+ mov x3, x30
+
+ bl plat_my_core_mask
+ mov x2, x0
+
+ /* see if this core is marked for prefetch disable */
+ mov x0, #PREFETCH_DIS_OFFSET
+ bl _get_global_data /* 0-1 */
+ tst x0, x2
+ b.eq 1f
+ bl _disable_ldstr_pfetch_A53 /* 0 */
+1:
+ mov x30, x3
+ ret
+endfunc soc_init_percpu
+
+/*
+ * part of CPU_ON
+ * this function releases a secondary core from reset
+ * in: x0 = core_mask_lsb
+ * out: none
+ * uses: x0, x1, x2, x3
+ */
+_soc_core_release:
+
+#if (TEST_BL31)
+ mov w2, w0
+ CoreMaskMsb w2, w3
+ /* x2 = core mask msb */
+#else
+ mov x2, x0
+#endif
+ /* write COREBCR */
+ ldr x1, =NXP_SCFG_ADDR
+ rev w3, w2
+ str w3, [x1, #SCFG_COREBCR_OFFSET]
+ isb
+
+ /* read-modify-write BRR */
+ mov x1, #NXP_DCFG_ADDR
+ ldr w2, [x1, #DCFG_BRR_OFFSET]
+ rev w3, w2
+ orr w3, w3, w0
+ rev w2, w3
+ str w2, [x1, #DCFG_BRR_OFFSET]
+ isb
+
+ /* send event */
+ sev
+ isb
+ ret
+
+
+/*
+ * part of CPU_ON
+ * this function restarts a core shutdown via _soc_core_entr_off
+ * in: x0 = core mask lsb (of the target cpu)
+ * out: x0 == 0, on success
+ * x0 != 0, on failure
+ * uses x0 ~ x5
+ */
+_soc_core_restart:
+ mov x5, x30
+ mov x3, x0
+
+ /* x3 = core mask lsb */
+ bl _getGICD_BaseAddr
+ mov x4, x0
+
+ /* x4 = GICD_BASE_ADDR */
+ /* enable forwarding of group 0 interrupts by setting GICD_CTLR[0] = 1 */
+ ldr w1, [x4, #GICD_CTLR_OFFSET]
+ orr w1, w1, #GICD_CTLR_EN_GRP0
+ str w1, [x4, #GICD_CTLR_OFFSET]
+ dsb sy
+ isb
+
+ /*
+ * fire SGI by writing to GICD_SGIR the following values:
+ * [25:24] = 0x0 (forward interrupt to the CPU interfaces specified in CPUTargetList field)
+ * [23:16] = core mask lsb[7:0] (forward interrupt to target cpu)
+ * [15] = 0 (forward SGI only if it is configured as group 0 interrupt)
+ * [3:0] = 0xF (interrupt ID = 15)
+ */
+ lsl w1, w3, #16
+ orr w1, w1, #0xF
+ str w1, [x4, #GICD_SGIR_OFFSET]
+ dsb sy
+ isb
+
+ /* load '0' on success */
+ mov x0, xzr
+
+ mov x30, x5
+ ret
+
+/*
+ * this function determines if a core is disabled via COREDISR
+ * in: w0 = core_mask_lsb
+ * out: w0 = 0, core not disabled
+ * w0 != 0, core disabled
+ * uses x0, x1, x2
+ */
+_soc_ck_disabled:
+
+ /* get base addr of dcfg block */
+ ldr x1, =NXP_DCFG_ADDR
+
+ /* read COREDISR */
+ ldr w1, [x1, #DCFG_COREDISR_OFFSET]
+ rev w2, w1
+
+ /* test core bit */
+ and w0, w2, w0
+ ret
+
+/*
+ * this function resets the system via SoC-specific methods
+ * in: none
+ * out: none
+ * uses x0, x1, x2, x3
+ */
+_soc_sys_reset:
+
+ ldr x2, =NXP_DCFG_ADDR
+
+ /* make sure the mask is cleared in the reset request mask register */
+ mov w1, wzr
+ str w1, [x2, #DCFG_RSTRQMR1_OFFSET]
+
+ /* x2 = NXP_DCFG_ADDR */
+
+ /* set the reset request */
+ ldr w1, =RSTCR_RESET_REQ
+ ldr x3, =DCFG_RSTCR_OFFSET
+ rev w0, w1
+ str w0, [x2, x3]
+
+ /* x2 = NXP_DCFG_ADDR */
+ /* x3 = DCFG_RSTCR_OFFSET */
+
+ /* just in case this address range is mapped as cacheable,
+ * flush the write out of the dcaches */
+ add x3, x2, x3
+ dc cvac, x3
+ dsb st
+ isb
+
+ /* Note: this function does not return */
+1:
+ wfi
+ b 1b
+
+
+/*
+ * part of SYSTEM_OFF
+ * this function turns off the SoC clocks
+ * Note: this function is not intended to return, and the only allowable
+ * recovery is POR
+ * in: none
+ * out: none
+ * uses x0 ~ x8
+ */
+_soc_sys_off:
+
+ /* mask interrupts at the core */
+ mrs x1, DAIF
+ mov x0, #DAIF_SET_MASK
+ orr x0, x1, x0
+ msr DAIF, x0
+
+ /* disable icache, dcache, mmu @ EL1 */
+ mov x1, #SCTLR_I_C_M_MASK
+ mrs x0, sctlr_el1
+ bic x0, x0, x1
+ msr sctlr_el1, x0
+
+ /* disable dcache for EL3 */
+ mrs x1, SCTLR_EL3
+ bic x1, x1, #SCTLR_C_MASK
+ /* make sure icache is enabled */
+ orr x1, x1, #SCTLR_I_MASK
+ msr SCTLR_EL3, x1
+ isb
+
+ /* set WFIL2_EN in SCFG_COREPMCR */
+ ldr x0, =SCFG_COREPMCR_OFFSET
+ ldr x1, =COREPMCR_WFIL2
+ bl write_reg_scfg
+
+ /* set OVRD_EN in RCPM2_POWMGTDCR */
+ ldr x0, =RCPM2_POWMGTDCR_OFFSET
+ ldr x1, =POWMGTDCR_OVRD_EN
+ bl write_reg_rcpm2
+
+ /* read IPPDEXPCR0 @ RCPM_IPPDEXPCR0 */
+ ldr x0, =RCPM_IPPDEXPCR0_OFFSET
+ bl read_reg_rcpm
+ mov x7, x0
+
+ /* build an override mask for IPSTPCR4/IPSTPACK4/DEVDISR5 */
+ mov x5, xzr
+ ldr x6, =IPPDEXPCR_MASK2
+ and x6, x6, x7
+ cbz x6, 1f
+
+ /* x5 = override mask
+ * x6 = IPPDEXPCR bits for DEVDISR5
+ * x7 = IPPDEXPCR */
+
+ /* get the overrides */
+ orr x4, x5, #DEVDISR5_I2C_1
+ tst x6, #IPPDEXPCR_I2C1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR5_LPUART1
+ tst x6, #IPPDEXPCR_LPUART1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR5_FLX_TMR
+ tst x6, #IPPDEXPCR_FLX_TMR1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR5_OCRAM1
+ tst x6, #IPPDEXPCR_OCRAM1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR5_GPIO
+ tst x6, #IPPDEXPCR_GPIO1
+ csel x5, x5, x4, EQ
+1:
+ /* store the DEVDISR5 override mask */
+ ldr x2, =BC_PSCI_BASE
+ add x2, x2, #AUX_01_DATA
+ str w5, [x2, #DEVDISR5_MASK_OFFSET]
+
+ /* build an override mask for IPSTPCR1/IPSTPACK1/DEVDISR2 */
+ mov x5, xzr
+ ldr x6, =IPPDEXPCR_MASK1
+ and x6, x6, x7
+ cbz x6, 2f
+
+ /* x5 = override mask */
+ /* x6 = IPPDEXPCR bits for DEVDISR2 */
+
+ /* get the overrides */
+ orr x4, x5, #DEVDISR2_FMAN1_MAC1
+ tst x6, #IPPDEXPCR_MAC1_1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC2
+ tst x6, #IPPDEXPCR_MAC1_2
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC3
+ tst x6, #IPPDEXPCR_MAC1_3
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC4
+ tst x6, #IPPDEXPCR_MAC1_4
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC5
+ tst x6, #IPPDEXPCR_MAC1_5
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC6
+ tst x6, #IPPDEXPCR_MAC1_6
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC9
+ tst x6, #IPPDEXPCR_MAC1_9
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1
+ tst x6, #IPPDEXPCR_FM1
+ csel x5, x5, x4, EQ
+
+2:
+ /* store the DEVDISR2 override mask */
+ ldr x2, =BC_PSCI_BASE
+ add x2, x2, #AUX_01_DATA
+ str w5, [x2, #DEVDISR2_MASK_OFFSET]
+
+ /* x5 = DEVDISR2 override mask */
+
+ /* write IPSTPCR0 - no overrides */
+ ldr x0, =RCPM2_IPSTPCR0_OFFSET
+ ldr x1, =IPSTPCR0_VALUE
+ bl write_reg_rcpm2
+
+ /* x5 = DEVDISR2 override mask */
+
+ /* write IPSTPCR1 - overrides possible */
+ ldr x0, =RCPM2_IPSTPCR1_OFFSET
+ ldr x1, =IPSTPCR1_VALUE
+ bic x1, x1, x5
+ bl write_reg_rcpm2
+
+ /* write IPSTPCR2 - no overrides */
+ ldr x0, =RCPM2_IPSTPCR2_OFFSET
+ ldr x1, =IPSTPCR2_VALUE
+ bl write_reg_rcpm2
+
+ /* write IPSTPCR3 - no overrides */
+ ldr x0, =RCPM2_IPSTPCR3_OFFSET
+ ldr x1, =IPSTPCR3_VALUE
+ bl write_reg_rcpm2
+
+ /* write IPSTPCR4 - overrides possible */
+ ldr x2, =BC_PSCI_BASE
+ add x2, x2, #AUX_01_DATA
+ ldr w6, [x2, #DEVDISR5_MASK_OFFSET]
+ ldr x0, =RCPM2_IPSTPCR4_OFFSET
+ ldr x1, =IPSTPCR4_VALUE
+ bic x1, x1, x6
+ bl write_reg_rcpm2
+
+ /* x5 = DEVDISR2 override mask */
+ /* x6 = DEVDISR5 override mask */
+
+ /* poll on IPSTPACK0 */
+ ldr x3, =RCPM2_IPSTPACKR0_OFFSET
+ ldr x4, =IPSTPCR0_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+3:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 14f
+ sub x7, x7, #1
+ cbnz x7, 3b
+
+14:
+ /* poll on IPSTPACK1 */
+ ldr x3, =IPSTPCR1_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+ bic x4, x3, x5
+ ldr x3, =RCPM2_IPSTPACKR1_OFFSET
+4:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 15f
+ sub x7, x7, #1
+ cbnz x7, 4b
+
+15:
+ /* poll on IPSTPACK2 */
+ ldr x3, =RCPM2_IPSTPACKR2_OFFSET
+ ldr x4, =IPSTPCR2_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+5:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 16f
+ sub x7, x7, #1
+ cbnz x7, 5b
+
+16:
+ /* poll on IPSTPACK3 */
+ ldr x3, =RCPM2_IPSTPACKR3_OFFSET
+ ldr x4, =IPSTPCR3_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+6:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 17f
+ sub x7, x7, #1
+ cbnz x7, 6b
+
+17:
+ /* poll on IPSTPACK4 */
+ ldr x3, =IPSTPCR4_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+ bic x4, x3, x6
+ ldr x3, =RCPM2_IPSTPACKR4_OFFSET
+7:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 18f
+ sub x7, x7, #1
+ cbnz x7, 7b
+
+18:
+ ldr x7, =BC_PSCI_BASE
+ add x7, x7, #AUX_01_DATA
+
+ /* x5 = DEVDISR2 override mask
+ * x6 = DEVDISR5 override mask
+ * x7 = [soc_data_area] */
+
+ /* DEVDISR1 - load new value */
+ mov x0, #DCFG_DEVDISR1_OFFSET
+ bl read_reg_dcfg
+ mov x0, #DCFG_DEVDISR1_OFFSET
+ ldr x1, =DEVDISR1_VALUE
+ bl write_reg_dcfg
+
+ /* DEVDISR2 - load new value */
+ mov x0, #DCFG_DEVDISR2_OFFSET
+ bl read_reg_dcfg
+ mov x0, #DCFG_DEVDISR2_OFFSET
+ ldr x1, =DEVDISR2_VALUE
+ bic x1, x1, x5
+ bl write_reg_dcfg
+
+ /* x6 = DEVDISR5 override mask */
+ /* x7 = [soc_data_area] */
+
+ /* DEVDISR3 - load new value */
+ mov x0, #DCFG_DEVDISR3_OFFSET
+ bl read_reg_dcfg
+ mov x0, #DCFG_DEVDISR3_OFFSET
+ ldr x1, =DEVDISR3_VALUE
+ bl write_reg_dcfg
+
+ /* DEVDISR4 - load new value */
+ mov x0, #DCFG_DEVDISR4_OFFSET
+ bl read_reg_dcfg
+ mov x0, #DCFG_DEVDISR4_OFFSET
+ ldr x1, =DEVDISR4_VALUE
+ bl write_reg_dcfg
+
+ /* DEVDISR5 - load new value */
+ mov x0, #DCFG_DEVDISR5_OFFSET
+ bl read_reg_dcfg
+ mov x0, #DCFG_DEVDISR5_OFFSET
+ ldr x1, =DEVDISR5_VALUE
+ bic x1, x1, x6
+ bl write_reg_dcfg
+
+ /* x7 = [soc_data_area] */
+
+ /* disable data prefetch */
+ mrs x0, CPUACTLR_EL1
+ bic x0, x0, #CPUACTLR_L1PCTL_MASK
+ msr CPUACTLR_EL1, x0
+
+ /* x6 = DEVDISR5 override mask */
+
+ /* setup registers for cache-only execution */
+ ldr x5, =IPSTPCR4_VALUE
+ bic x5, x5, x6
+ mov x6, #DDR_CNTRL_BASE_ADDR
+ mov x7, #DCSR_RCPM2_BASE
+ mov x8, #NXP_DCFG_ADDR
+ dsb sy
+ isb
+
+ /* set the DLL_LOCK cycle count */
+ ldr w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
+ rev w2, w1
+ bic w2, w2, #DLL_LOCK_MASK
+ orr w2, w2, #DLL_LOCK_VALUE
+ rev w1, w2
+ str w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
+
+ /* x5 = ipstpcr4 (IPSTPCR4_VALUE bic DEVDISR5_MASK)
+ * x6 = DDR_CNTRL_BASE_ADDR
+ * x7 = DCSR_RCPM2_BASE
+ * x8 = NXP_DCFG_ADDR */
+
+ /* enter the cache-only sequence - there is no return */
+ b final_shutdown
+
+
+/*
+ * part of CPU_OFF
+ * this function programs SoC & GIC registers in preparation for shutting down
+ * the core
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0 ~ x7
+ */
+_soc_core_prep_off:
+ mov x7, x30
+ mov x6, x0
+
+ /* make sure the smpen bit is set */
+ mrs x2, CORTEX_A53_ECTLR_EL1
+ orr x2, x2, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A53_ECTLR_EL1, x2
+ isb
+
+ /* configure the cpu interface */
+
+ /* disable signaling of ints */
+ bl _getGICC_BaseAddr // 0-1
+ mov x4, x0
+
+ ldr w3, [x4, #GICC_CTLR_OFFSET]
+ bic w3, w3, #GICC_CTLR_EN_GRP0
+ bic w3, w3, #GICC_CTLR_EN_GRP1
+ str w3, [x4, #GICC_CTLR_OFFSET]
+ dsb sy
+ isb
+
+ /*
+ * x3 = GICC_CTRL
+ * x4 = GICC_BASE_ADDR
+ * x6 = core mask
+ */
+
+ /* set the priority filter */
+ ldr w2, [x4, #GICC_PMR_OFFSET]
+ orr w2, w2, #GICC_PMR_FILTER
+ str w2, [x4, #GICC_PMR_OFFSET]
+
+ /* setup GICC_CTLR */
+ bic w3, w3, #GICC_CTLR_ACKCTL_MASK
+ orr w3, w3, #GICC_CTLR_FIQ_EN_MASK
+ orr w3, w3, #GICC_CTLR_EOImodeS_MASK
+ orr w3, w3, #GICC_CTLR_CBPR_MASK
+ str w3, [x4, #GICC_CTLR_OFFSET]
+
+ /* x3 = GICC_CTRL */
+ /* x4 = GICC_BASE_ADDR */
+
+ /* setup the banked-per-core GICD registers */
+ bl _getGICD_BaseAddr
+
+ /*
+ * x0 = GICD_BASE_ADDR
+ * x3 = GICC_CTRL
+ * x4 = GICC_BASE_ADDR
+ * x6 = core mask
+ */
+
+ /* define SGI15 as Grp0 */
+ ldr w2, [x0, #GICD_IGROUPR0_OFFSET]
+ bic w2, w2, #GICD_IGROUP0_SGI15
+ str w2, [x0, #GICD_IGROUPR0_OFFSET]
+
+ /* set priority of SGI 15 to highest... */
+ ldr w2, [x0, #GICD_IPRIORITYR3_OFFSET]
+ bic w2, w2, #GICD_IPRIORITY_SGI15_MASK
+ str w2, [x0, #GICD_IPRIORITYR3_OFFSET]
+
+ /* enable SGI 15 */
+ ldr w2, [x0, #GICD_ISENABLER0_OFFSET]
+ orr w2, w2, #GICD_ISENABLE0_SGI15
+ str w2, [x0, #GICD_ISENABLER0_OFFSET]
+
+ /* enable the cpu interface */
+ orr w3, w3, #GICC_CTLR_EN_GRP0
+ str w3, [x4, #GICC_CTLR_OFFSET]
+
+ /* x0 = GICD_BASE_ADDR
+ * x6 = core mask */
+
+ /* clear any pending SGIs */
+ add x0, x0, #GICD_CPENDSGIR3_OFFSET
+ ldr x2, =GICD_CPENDSGIR_CLR_MASK
+ str w2, [x0]
+
+ dsb sy
+ isb
+ mov x30, x7
+ ret
+
+/*
+ * part of CPU_OFF
+ * this function performs the final steps to shutdown the core
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0 ~ x5
+ */
+_soc_core_entr_off:
+ mov x5, x30
+ mov x4, x0
+
+ bl _getGICD_BaseAddr
+ mov x3, x0
+
+ /* x3 = GICD_BASE_ADDR */
+ /* x4 = core mask (lsb) */
+
+3:
+ /* enter low-power state by executing wfi */
+ wfi
+
+ /* x3 = GICD_BASE_ADDR */
+ /* x4 = core mask (lsb) */
+
+ /* see if we got hit by SGI 15 */
+ add x0, x3, #GICD_SPENDSGIR3_OFFSET
+ ldr w2, [x0]
+ and w2, w2, #GICD_SPENDSGIR3_SGI15_MASK
+ cbz w2, 4f
+
+ /* clear the pending SGI */
+ ldr x2, =GICD_CPENDSGIR_CLR_MASK
+ add x0, x3, #GICD_CPENDSGIR3_OFFSET
+ str w2, [x0]
+4:
+ /* check if core has been turned on */
+ mov x0, x4
+ bl _getCoreState
+
+ /* x0 = core state */
+ cmp x0, #CORE_WAKEUP
+ b.ne 3b
+
+ /* if we get here, then we have exited the wfi */
+ dsb sy
+ isb
+ mov x30, x5
+ ret
+
+/*
+ * part of CPU_OFF
+ * this function starts the process of starting a core back up
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0 ~ x5
+ */
+_soc_core_exit_off:
+ mov x5, x30
+ mov x4, x0
+
+ /* x4 = core mask */
+
+ bl _getGICC_BaseAddr
+ mov x2, x0
+
+ /* read GICC_IAR */
+ ldr w0, [x2, #GICC_IAR_OFFSET]
+
+ /* write GICC_EIOR - signal end-of-interrupt */
+ str w0, [x2, #GICC_EOIR_OFFSET]
+
+ /* write GICC_DIR - disable interrupt */
+ str w0, [x2, #GICC_DIR_OFFSET]
+
+ /* x2 = GICC_BASE_ADDR */
+
+ /* disable signaling of grp0 ints */
+ ldr w1, [x2, #GICC_CTLR_OFFSET]
+ bic w1, w1, #GICC_CTLR_EN_GRP0
+ str w1, [x2, #GICC_CTLR_OFFSET]
+
+ dsb sy
+ isb
+ mov x30, x5
+ ret
+
+/*
+ * this function loads a 64-bit execution address of the core in the soc registers
+ * BOOTLOCPTRL/H
+ * in: x0, 64-bit address to write to BOOTLOCPTRL/H
+ * uses x0, x1, x2, x3
+ */
+_soc_set_start_addr:
+ /* get the 64-bit base address of the scfg block */
+ ldr x2, =NXP_SCFG_ADDR
+
+ /* write the 32-bit BOOTLOCPTRL register (offset 0x604 in the scfg block) */
+ mov x1, x0
+ rev w3, w1
+ str w3, [x2, #SCFG_BOOTLOCPTRL_OFFSET]
+
+ /* write the 32-bit BOOTLOCPTRH register (offset 0x600 in the scfg block) */
+ lsr x1, x0, #32
+ rev w3, w1
+ str w3, [x2, #SCFG_BOOTLOCPTRH_OFFSET]
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function puts the calling core into standby state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0
+ */
+_soc_core_entr_stdby:
+ dsb sy
+ isb
+ wfi
+
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to standby
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_core_prep_stdby:
+ /* clear CORTEX_A53_ECTLR_EL1[2:0] */
+ mrs x1, CORTEX_A53_ECTLR_EL1
+ bic x1, x1, #CPUECTLR_TIMER_MASK
+ msr CORTEX_A53_ECTLR_EL1, x1
+
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after standby state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_core_exit_stdby:
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_core_prep_pwrdn:
+ /* make sure the smp bit is set */
+ mrs x1, CORTEX_A53_ECTLR_EL1
+ orr x1, x1, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A53_ECTLR_EL1, x1
+ isb
+
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function puts the calling core into a power-down state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0
+ */
+_soc_core_entr_pwrdn:
+ dsb sy
+ isb
+ wfi
+
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_core_exit_pwrdn:
+ ret
+
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to standby
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_clstr_prep_stdby:
+ /* clear CORTEX_A53_ECTLR_EL1[2:0] */
+ mrs x1, CORTEX_A53_ECTLR_EL1
+ bic x1, x1, #CPUECTLR_TIMER_MASK
+ msr CORTEX_A53_ECTLR_EL1, x1
+
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after standby state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_clstr_exit_stdby:
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_clstr_prep_pwrdn:
+ /* make sure the smp bit is set */
+ mrs x1, CORTEX_A53_ECTLR_EL1
+ orr x1, x1, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A53_ECTLR_EL1, x1
+ isb
+
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_clstr_exit_pwrdn:
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to standby
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_sys_prep_stdby:
+ /* clear CORTEX_A53_ECTLR_EL1[2:0] */
+ mrs x1, CORTEX_A53_ECTLR_EL1
+ bic x1, x1, #CPUECTLR_TIMER_MASK
+ msr CORTEX_A53_ECTLR_EL1, x1
+
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after standby state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_sys_exit_stdby:
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to
+ * suspend-to-power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4
+ */
+_soc_sys_prep_pwrdn:
+ mov x4, x30
+ /* make sure the smp bit is set */
+ mrs x1, CORTEX_A53_ECTLR_EL1
+ orr x1, x1, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A53_ECTLR_EL1, x1
+ isb
+
+ /* set WFIL2_EN in SCFG_COREPMCR */
+ ldr x0, =SCFG_COREPMCR_OFFSET
+ ldr x1, =COREPMCR_WFIL2
+ bl write_reg_scfg // 0-3
+
+ /* set OVRD_EN in RCPM2_POWMGTDCR */
+ ldr x0, =RCPM2_POWMGTDCR_OFFSET
+ ldr x1, =POWMGTDCR_OVRD_EN
+ bl write_reg_rcpm2 // 0-3
+
+ mov x30, x4
+ ret
+/*
+ * part of CPU_SUSPEND
+ * this function puts the calling core, and potentially the soc, into a
+ * low-power state
+ * in: x0 = core mask lsb
+ * out: x0 = 0, success
+ * x0 < 0, failure
+ * uses x0 ~ x9
+ */
+_soc_sys_pwrdn_wfi:
+ mov x18, x30
+
+ /* read IPPDEXPCR0 @ RCPM_IPPDEXPCR0 */
+ ldr x0, =RCPM_IPPDEXPCR0_OFFSET
+ bl read_reg_rcpm
+ mov x7, x0
+
+ /* build an override mask for IPSTPCR4/IPSTPACK4/DEVDISR5 */
+ mov x5, xzr
+ ldr x6, =IPPDEXPCR_MASK2
+ and x6, x6, x7
+ cbz x6, 1f
+
+ /* x5 = override mask
+ * x6 = IPPDEXPCR bits for DEVDISR5
+ * x7 = IPPDEXPCR */
+
+ /* get the overrides */
+ orr x4, x5, #DEVDISR5_I2C_1
+ tst x6, #IPPDEXPCR_I2C1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR5_LPUART1
+ tst x6, #IPPDEXPCR_LPUART1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR5_FLX_TMR
+ tst x6, #IPPDEXPCR_FLX_TMR1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR5_OCRAM1
+ tst x6, #IPPDEXPCR_OCRAM1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR5_GPIO
+ tst x6, #IPPDEXPCR_GPIO1
+ csel x5, x5, x4, EQ
+1:
+ /* store the DEVDISR5 override mask */
+ ldr x2, =BC_PSCI_BASE
+ add x2, x2, #AUX_01_DATA
+ str w5, [x2, #DEVDISR5_MASK_OFFSET]
+
+ /* build an override mask for IPSTPCR1/IPSTPACK1/DEVDISR2 */
+ mov x5, xzr
+ ldr x6, =IPPDEXPCR_MASK1
+ and x6, x6, x7
+ cbz x6, 2f
+
+ /* x5 = override mask */
+ /* x6 = IPPDEXPCR bits for DEVDISR2 */
+
+ /* get the overrides */
+ orr x4, x5, #DEVDISR2_FMAN1_MAC1
+ tst x6, #IPPDEXPCR_MAC1_1
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC2
+ tst x6, #IPPDEXPCR_MAC1_2
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC3
+ tst x6, #IPPDEXPCR_MAC1_3
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC4
+ tst x6, #IPPDEXPCR_MAC1_4
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC5
+ tst x6, #IPPDEXPCR_MAC1_5
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC6
+ tst x6, #IPPDEXPCR_MAC1_6
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1_MAC9
+ tst x6, #IPPDEXPCR_MAC1_9
+ csel x5, x5, x4, EQ
+
+ orr x4, x5, #DEVDISR2_FMAN1
+ tst x6, #IPPDEXPCR_FM1
+ csel x5, x5, x4, EQ
+
+2:
+ /* store the DEVDISR2 override mask */
+ ldr x2, =BC_PSCI_BASE
+ add x2, x2, #AUX_01_DATA
+ str w5, [x2, #DEVDISR2_MASK_OFFSET]
+
+ /* x5 = DEVDISR2 override mask */
+
+ /* write IPSTPCR0 - no overrides */
+ ldr x0, =RCPM2_IPSTPCR0_OFFSET
+ ldr x1, =IPSTPCR0_VALUE
+ bl write_reg_rcpm2
+
+ /* x5 = DEVDISR2 override mask */
+
+ /* write IPSTPCR1 - overrides possible */
+ ldr x0, =RCPM2_IPSTPCR1_OFFSET
+ ldr x1, =IPSTPCR1_VALUE
+ bic x1, x1, x5
+ bl write_reg_rcpm2
+
+ /* write IPSTPCR2 - no overrides */
+ ldr x0, =RCPM2_IPSTPCR2_OFFSET
+ ldr x1, =IPSTPCR2_VALUE
+ bl write_reg_rcpm2
+
+ /* write IPSTPCR3 - no overrides */
+ ldr x0, =RCPM2_IPSTPCR3_OFFSET
+ ldr x1, =IPSTPCR3_VALUE
+ bl write_reg_rcpm2
+
+ /* write IPSTPCR4 - overrides possible */
+ ldr x2, =BC_PSCI_BASE
+ add x2, x2, #AUX_01_DATA
+ ldr w6, [x2, #DEVDISR5_MASK_OFFSET]
+ ldr x0, =RCPM2_IPSTPCR4_OFFSET
+ ldr x1, =IPSTPCR4_VALUE
+ bic x1, x1, x6
+ bl write_reg_rcpm2
+
+ /* x5 = DEVDISR2 override mask */
+ /* x6 = DEVDISR5 override mask */
+
+ /* poll on IPSTPACK0 */
+ ldr x3, =RCPM2_IPSTPACKR0_OFFSET
+ ldr x4, =IPSTPCR0_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+3:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 14f
+ sub x7, x7, #1
+ cbnz x7, 3b
+
+14:
+ /* poll on IPSTPACK1 */
+ ldr x3, =IPSTPCR1_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+ bic x4, x3, x5
+ ldr x3, =RCPM2_IPSTPACKR1_OFFSET
+4:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 15f
+ sub x7, x7, #1
+ cbnz x7, 4b
+
+15:
+ /* poll on IPSTPACK2 */
+ ldr x3, =RCPM2_IPSTPACKR2_OFFSET
+ ldr x4, =IPSTPCR2_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+5:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 16f
+ sub x7, x7, #1
+ cbnz x7, 5b
+
+16:
+ /* poll on IPSTPACK3 */
+ ldr x3, =RCPM2_IPSTPACKR3_OFFSET
+ ldr x4, =IPSTPCR3_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+6:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 17f
+ sub x7, x7, #1
+ cbnz x7, 6b
+
+17:
+ /* poll on IPSTPACK4 */
+ ldr x3, =IPSTPCR4_VALUE
+ ldr x7, =IPSTPACK_RETRY_CNT
+ bic x4, x3, x6
+ ldr x3, =RCPM2_IPSTPACKR4_OFFSET
+7:
+ mov x0, x3
+ bl read_reg_rcpm2
+ cmp x0, x4
+ b.eq 18f
+ sub x7, x7, #1
+ cbnz x7, 7b
+
+18:
+ ldr x7, =BC_PSCI_BASE
+ add x7, x7, #AUX_01_DATA
+
+ /* x5 = DEVDISR2 override mask
+ * x6 = DEVDISR5 override mask
+ * x7 = [soc_data_area] */
+
+ /* save DEVDISR1 and load new value */
+ mov x0, #DCFG_DEVDISR1_OFFSET
+ bl read_reg_dcfg
+ mov w13, w0
+ mov x0, #DCFG_DEVDISR1_OFFSET
+ ldr x1, =DEVDISR1_VALUE
+ bl write_reg_dcfg
+
+ /* save DEVDISR2 and load new value */
+ mov x0, #DCFG_DEVDISR2_OFFSET
+ bl read_reg_dcfg
+ mov w14, w0
+ mov x0, #DCFG_DEVDISR2_OFFSET
+ ldr x1, =DEVDISR2_VALUE
+ bic x1, x1, x5
+ bl write_reg_dcfg
+
+ /* x6 = DEVDISR5 override mask */
+ /* x7 = [soc_data_area] */
+
+ /* save DEVDISR3 and load new value */
+ mov x0, #DCFG_DEVDISR3_OFFSET
+ bl read_reg_dcfg
+ mov w15, w0
+ mov x0, #DCFG_DEVDISR3_OFFSET
+ ldr x1, =DEVDISR3_VALUE
+ bl write_reg_dcfg
+
+ /* save DEVDISR4 and load new value */
+ mov x0, #DCFG_DEVDISR4_OFFSET
+ bl read_reg_dcfg
+ mov w16, w0
+ mov x0, #DCFG_DEVDISR4_OFFSET
+ ldr x1, =DEVDISR4_VALUE
+ bl write_reg_dcfg
+
+ /* save DEVDISR5 and load new value */
+ mov x0, #DCFG_DEVDISR5_OFFSET
+ bl read_reg_dcfg
+ mov w17, w0
+ mov x0, #DCFG_DEVDISR5_OFFSET
+ ldr x1, =DEVDISR5_VALUE
+ bic x1, x1, x6
+ bl write_reg_dcfg
+
+ /* x7 = [soc_data_area] */
+
+ /* save cpuactlr and disable data prefetch */
+ mrs x0, CPUACTLR_EL1
+ str w0, [x7, #CPUACTLR_DATA_OFFSET]
+ bic x0, x0, #CPUACTLR_L1PCTL_MASK
+ msr CPUACTLR_EL1, x0
+
+ /* x6 = DEVDISR5 override mask */
+
+ /* setup registers for cache-only execution */
+ ldr x5, =IPSTPCR4_VALUE
+ bic x5, x5, x6
+ mov x6, #DDR_CNTRL_BASE_ADDR
+ mov x7, #DCSR_RCPM2_BASE
+ mov x8, #NXP_DCFG_ADDR
+ dsb sy
+ isb
+
+ /* set the DLL_LOCK cycle count */
+ ldr w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
+ rev w2, w1
+ bic w2, w2, #DLL_LOCK_MASK
+ orr w2, w2, #DLL_LOCK_VALUE
+ rev w1, w2
+ str w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
+
+ /*
+ * x5 = ipstpcr4 (IPSTPCR4_VALUE bic DEVDISR5_MASK)
+ * x6 = DDR_CNTRL_BASE_ADDR
+ * x7 = DCSR_RCPM2_BASE
+ * x8 = NXP_DCFG_ADDR
+ * w13 = DEVDISR1 saved value
+ * w14 = DEVDISR2 saved value
+ * w15 = DEVDISR3 saved value
+ * w16 = DEVDISR4 saved value
+ * w17 = DEVDISR5 saved value
+ */
+
+ /* enter the cache-only sequence */
+ mov x9, #CORE_RESTARTABLE
+ bl final_pwrdown
+
+ /* when we are here, the core has come out of wfi and the SoC is back up */
+
+ mov x30, x18
+ ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_sys_exit_pwrdn:
+ /* clear POWMGTDCR */
+ mov x1, #DCSR_RCPM2_BASE
+ str wzr, [x1, #RCPM2_POWMGTDCR_OFFSET]
+
+ /* clear WFIL2_EN in SCFG_COREPMCR */
+ mov x1, #NXP_SCFG_ADDR
+ str wzr, [x1, #SCFG_COREPMCR_OFFSET]
+
+ ret
+
+/*
+ * write a register in the SCFG block
+ * in: x0 = offset
+ * in: w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+write_reg_scfg:
+ ldr x2, =NXP_SCFG_ADDR
+ /* swap for BE */
+ rev w3, w1
+ str w3, [x2, x0]
+ ret
+/*
+ * read a register in the SCFG block
+ * in: x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+read_reg_scfg:
+ ldr x2, =NXP_SCFG_ADDR
+ ldr w1, [x2, x0]
+ /* swap for BE */
+ rev w0, w1
+ ret
+
+/*
+ * write a register in the DCFG block
+ * in: x0 = offset
+ * in: w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+write_reg_dcfg:
+ ldr x2, =NXP_DCFG_ADDR
+ /* swap for BE */
+ rev w3, w1
+ str w3, [x2, x0]
+ ret
+
+/*
+ * read a register in the DCFG block
+ * in: x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+read_reg_dcfg:
+ ldr x2, =NXP_DCFG_ADDR
+ ldr w1, [x2, x0]
+ /* swap for BE */
+ rev w0, w1
+ ret
+
+/*
+ * write a register in the RCPM block
+ * in: x0 = offset
+ * in: w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+write_reg_rcpm:
+ ldr x2, =NXP_RCPM_ADDR
+ /* swap for BE */
+ rev w3, w1
+ str w3, [x2, x0]
+ ret
+
+/*
+ * read a register in the RCPM block
+ * in: x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+read_reg_rcpm:
+ ldr x2, =NXP_RCPM_ADDR
+ ldr w1, [x2, x0]
+ /* swap for BE */
+ rev w0, w1
+ ret
+
+/*
+ * write a register in the DCSR-RCPM2 block
+ * in: x0 = offset
+ * in: w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+write_reg_rcpm2:
+ ldr x2, =DCSR_RCPM2_BASE
+ /* swap for BE */
+ rev w3, w1
+ str w3, [x2, x0]
+ ret
+
+/*
+ * read a register in the DCSR-RCPM2 block
+ * in: x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+read_reg_rcpm2:
+ ldr x2, =DCSR_RCPM2_BASE
+ ldr w1, [x2, x0]
+ /* swap for BE */
+ rev w0, w1
+ ret
+
+/*
+ * this function returns the base address of the gic distributor
+ * in: none
+ * out: x0 = base address of gic distributor
+ * uses x0, x1
+ */
+_getGICD_BaseAddr:
+ /* read SVR and get the SoC version */
+ mov x0, #NXP_DCFG_ADDR
+ ldr w1, [x0, #DCFG_SVR_OFFSET]
+ rev w0, w1
+
+ /* x0 = svr */
+ and w0, w0, #SVR_MIN_VER_MASK
+ cmp w0, #SVR_MINOR_VER_0
+ b.ne 8f
+
+ /* load the gic base addresses for rev 1.0 parts */
+ ldr x0, =NXP_GICD_4K_ADDR
+ b 10f
+8:
+ /* for rev 1.1 and later parts, the GIC base addresses */
+ /* can be at 4k or 64k offsets */
+
+ /* read the scfg reg GIC400_ADDR_ALIGN */
+ mov x0, #NXP_SCFG_ADDR
+ ldr w1, [x0, #SCFG_GIC400_ADDR_ALIGN_OFFSET]
+ rev w0, w1
+
+ /* x0 = GIC400_ADDR_ALIGN value */
+ and x0, x0, #SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK
+ mov x1, #SCFG_GIC400_ADDR_ALIGN_4KMODE_EN
+ cmp x0, x1
+ b.ne 9f
+
+ /* load the base addresses for 4k offsets */
+ ldr x0, =NXP_GICD_4K_ADDR
+ b 10f
+9:
+ /* load the base address for 64k offsets */
+ ldr x0, =NXP_GICD_64K_ADDR
+10:
+ ret
+
+/*
+ * this function returns the base address of the gic distributor
+ * in: none
+ * out: x0 = base address of gic controller
+ * uses x0, x1
+ */
+_getGICC_BaseAddr:
+ /* read SVR and get the SoC version */
+ mov x0, #NXP_DCFG_ADDR
+ ldr w1, [x0, #DCFG_SVR_OFFSET]
+ rev w0, w1
+
+ /* x0 = svr */
+ and w0, w0, #SVR_MIN_VER_MASK
+ cmp w0, #SVR_MINOR_VER_0
+ b.ne 8f
+
+ /* load the gic base addresses for rev 1.0 parts */
+ ldr x0, =NXP_GICC_4K_ADDR
+ b 10f
+8:
+ /* for rev 1.1 and later parts, the GIC base addresses */
+ /* can be at 4k or 64k offsets */
+
+ /* read the scfg reg GIC400_ADDR_ALIGN */
+ mov x0, #NXP_SCFG_ADDR
+ ldr w1, [x0, #SCFG_GIC400_ADDR_ALIGN_OFFSET]
+ rev w0, w1
+
+ /* x0 = GIC400_ADDR_ALIGN value */
+ and x0, x0, #SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK
+ mov x1, #SCFG_GIC400_ADDR_ALIGN_4KMODE_EN
+ cmp x0, x1
+ b.ne 9f
+
+ /* load the base addresses for 4k offsets */
+ ldr x0, =NXP_GICC_4K_ADDR
+ b 10f
+9:
+ /* load the base address for 64k offsets */
+ ldr x0, =NXP_GICC_64K_ADDR
+10:
+ ret
+
+/*
+ * this function will pwrdown ddr and the final core - it will do this
+ * by loading itself into the icache and then executing from there
+ * in: x5 = ipstpcr4 (IPSTPCR4_VALUE bic DEVDISR5_MASK)
+ * x6 = DDR_CNTRL_BASE_ADDR
+ * x7 = DCSR_RCPM2_BASE
+ * x8 = NXP_DCFG_ADDR
+ * x9 = 0, restartable
+ * = 1, non-restartable
+ * w13 = DEVDISR1 saved value
+ * w14 = DEVDISR2 saved value
+ * w15 = DEVDISR3 saved value
+ * w16 = DEVDISR4 saved value
+ * w17 = DEVDISR5 saved value
+ * out: none
+ * uses x0 ~ x9
+ */
+
+/* 4Kb aligned */
+.align 12
+final_pwrdown:
+ mov x0, xzr
+ b touch_line_0
+start_line_0:
+ mov x0, #1
+ mov x2, #DDR_SDRAM_CFG_2_FRCSR /* put ddr in self refresh - start */
+ ldr w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
+ rev w4, w3
+ orr w4, w4, w2
+ rev w3, w4
+ str w3, [x6, #DDR_SDRAM_CFG_2_OFFSET] /* put ddr in self refresh - end */
+ orr w3, w5, #DEVDISR5_MEM /* quiesce ddr clocks - start */
+ rev w4, w3
+ str w4, [x7, #RCPM2_IPSTPCR4_OFFSET] /* quiesce ddr clocks - end */
+
+ mov w3, #DEVDISR5_MEM
+ rev w3, w3 /* polling mask */
+ mov x2, #DDR_SLEEP_RETRY_CNT /* poll on ipstpack4 - start */
+touch_line_0:
+ cbz x0, touch_line_1
+
+start_line_1:
+ ldr w1, [x7, #RCPM2_IPSTPACKR4_OFFSET]
+ tst w1, w3
+ b.ne 1f
+ subs x2, x2, #1
+ b.gt start_line_1 /* poll on ipstpack4 - end */
+
+ /* if we get here, we have a timeout err */
+ rev w4, w5
+ str w4, [x7, #RCPM2_IPSTPCR4_OFFSET] /* re-enable ddr clks interface */
+ mov x0, #ERROR_DDR_SLEEP /* load error code */
+ b 2f
+1:
+ str w4, [x8, #DCFG_DEVDISR5_OFFSET] /* disable ddr cntrlr clk in devdisr5 */
+5:
+ wfi /* stop the final core */
+
+ cbnz x9, 5b /* if non-restartable, keep in wfi */
+ rev w4, w5
+ str w4, [x8, #DCFG_DEVDISR5_OFFSET] /* re-enable ddr in devdisr5 */
+ str w4, [x7, #RCPM2_IPSTPCR4_OFFSET] /* re-enable ddr clk in ipstpcr4 */
+touch_line_1:
+ cbz x0, touch_line_2
+
+start_line_2:
+ ldr w1, [x7, #RCPM2_IPSTPACKR4_OFFSET] /* poll on ipstpack4 - start */
+ tst w1, w3
+ b.eq 2f
+ nop
+ b start_line_2 /* poll on ipstpack4 - end */
+2:
+ mov x2, #DDR_SDRAM_CFG_2_FRCSR /* take ddr out-of self refresh - start */
+ ldr w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
+ rev w4, w3
+ bic w4, w4, w2
+ rev w3, w4
+ mov x1, #DDR_SLEEP_RETRY_CNT /* wait for ddr cntrlr clock - start */
+3:
+ subs x1, x1, #1
+ b.gt 3b /* wait for ddr cntrlr clock - end */
+ str w3, [x6, #DDR_SDRAM_CFG_2_OFFSET] /* take ddr out-of self refresh - end */
+ rev w1, w17
+touch_line_2:
+ cbz x0, touch_line_3
+
+start_line_3:
+ str w1, [x8, #DCFG_DEVDISR5_OFFSET] /* reset devdisr5 */
+ rev w1, w16
+ str w1, [x8, #DCFG_DEVDISR4_OFFSET] /* reset devdisr4 */
+ rev w1, w15
+ str w1, [x8, #DCFG_DEVDISR3_OFFSET] /* reset devdisr3 */
+ rev w1, w14
+ str w1, [x8, #DCFG_DEVDISR2_OFFSET] /* reset devdisr2 */
+ rev w1, w13
+ str w1, [x8, #DCFG_DEVDISR1_OFFSET] /* reset devdisr1 */
+ str wzr, [x7, #RCPM2_IPSTPCR4_OFFSET] /* reset ipstpcr4 */
+ str wzr, [x7, #RCPM2_IPSTPCR3_OFFSET] /* reset ipstpcr3 */
+ str wzr, [x7, #RCPM2_IPSTPCR2_OFFSET] /* reset ipstpcr2 */
+ str wzr, [x7, #RCPM2_IPSTPCR1_OFFSET] /* reset ipstpcr1 */
+ str wzr, [x7, #RCPM2_IPSTPCR0_OFFSET] /* reset ipstpcr0 */
+ b continue_restart
+touch_line_3:
+ cbz x0, start_line_0
+
+/* execute here after ddr is back up */
+continue_restart:
+ /*
+ * if x0 = 1, all is well
+ * if x0 < 1, we had an error
+ */
+ cmp x0, #1
+ b.ne 4f
+ mov x0, #0
+4:
+ ret
+
+/*
+ * Note: there is no return from this function
+ * this function will shutdown ddr and the final core - it will do this
+ * by loading itself into the icache and then executing from there
+ * in: x5 = ipstpcr4 (IPSTPCR4_VALUE bic DEVDISR5_MASK)
+ * x6 = DDR_CNTRL_BASE_ADDR
+ * x7 = DCSR_RCPM2_BASE
+ * x8 = NXP_DCFG_ADDR
+ * out: none
+ * uses x0 ~ x8
+ */
+
+/* 4Kb aligned */
+.align 12
+final_shutdown:
+
+ mov x0, xzr
+ b touch_line0
+start_line0:
+ mov x0, #1
+ mov x2, #DDR_SDRAM_CFG_2_FRCSR /* put ddr in self refresh - start */
+ ldr w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
+ rev w4, w3
+ orr w4, w4, w2
+ rev w3, w4
+ str w3, [x6, #DDR_SDRAM_CFG_2_OFFSET] /* put ddr in self refresh - end */
+ orr w3, w5, #DEVDISR5_MEM /* quiesce ddr clocks - start */
+ rev w4, w3
+ str w4, [x7, #RCPM2_IPSTPCR4_OFFSET] /* quiesce ddr clocks - end */
+
+ mov w3, #DEVDISR5_MEM
+ rev w3, w3 /* polling mask */
+ mov x2, #DDR_SLEEP_RETRY_CNT /* poll on ipstpack4 - start */
+touch_line0:
+ cbz x0, touch_line1
+
+start_line1:
+ ldr w1, [x7, #RCPM2_IPSTPACKR4_OFFSET]
+ tst w1, w3
+ b.ne 1f
+ subs x2, x2, #1
+ b.gt start_line1 /* poll on ipstpack4 - end */
+ nop
+ nop
+ nop
+ nop
+1:
+ str w4, [x8, #DCFG_DEVDISR5_OFFSET] /* disable ddr cntrlr clk in devdisr5 */
+5:
+ wfi /* stop the final core */
+ b 5b /* stay here until POR */
+ nop
+ nop
+ nop
+touch_line1:
+ cbz x0, start_line0
diff --git a/plat/nxp/soc-ls1043a/aarch64/ls1043a_helpers.S b/plat/nxp/soc-ls1043a/aarch64/ls1043a_helpers.S
new file mode 100644
index 0000000..bc88886
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/aarch64/ls1043a_helpers.S
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+#include <platform_def.h>
+
+ .globl plat_secondary_cold_boot_setup
+ .globl plat_is_my_cpu_primary
+ .globl plat_reset_handler
+ .globl platform_mem_init
+
+func platform_mem1_init
+ ret
+endfunc platform_mem1_init
+
+func platform_mem_init
+ ret
+endfunc platform_mem_init
+
+func apply_platform_errata
+ ret
+endfunc apply_platform_errata
+
+func plat_reset_handler
+ mov x29, x30
+ bl apply_platform_errata
+
+#if defined(IMAGE_BL31)
+ ldr x0, =POLICY_SMMU_PAGESZ_64K
+ cbz x0, 1f
+ /* Set the SMMU page size in the sACR register */
+ bl _set_smmu_pagesz_64
+#endif
+1:
+ mov x30, x29
+ ret
+endfunc plat_reset_handler
+
+/*
+ * void plat_secondary_cold_boot_setup (void);
+ *
+ * This function performs any platform specific actions
+ * needed for a secondary cpu after a cold reset e.g
+ * mark the cpu's presence, mechanism to place it in a
+ * holding pen etc.
+ */
+func plat_secondary_cold_boot_setup
+ /* ls1043a does not do cold boot for secondary CPU */
+cb_panic:
+ b cb_panic
+endfunc plat_secondary_cold_boot_setup
+
+/*
+ * unsigned int plat_is_my_cpu_primary (void);
+ *
+ * Find out whether the current cpu is the primary
+ * cpu.
+ */
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+ cmp x0, 0x0
+ cset w0, eq
+ ret
+endfunc plat_is_my_cpu_primary
diff --git a/plat/layerscape/board/ls1043/include/ns_access.h b/plat/nxp/soc-ls1043a/include/ns_access.h
similarity index 94%
rename from plat/layerscape/board/ls1043/include/ns_access.h
rename to plat/nxp/soc-ls1043a/include/ns_access.h
index 833a5df..423c454 100644
--- a/plat/layerscape/board/ls1043/include/ns_access.h
+++ b/plat/nxp/soc-ls1043a/include/ns_access.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018, 2020-2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +8,7 @@
#ifndef NS_ACCESS_H
#define NS_ACCESS_H
-#include "fsl_csu.h"
+#include <csu.h>
enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
@@ -90,15 +91,15 @@
CSU_CSLX_DSCR = 121,
};
-static struct csu_ns_dev ns_dev[] = {
+struct csu_ns_dev_st ns_dev[] = {
{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
- {CSU_CSLX_OCRAM, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM, CSU_S_SUP_RW},
{CSU_CSLX_GIC, CSU_ALL_RW},
{CSU_CSLX_PCIE1, CSU_ALL_RW},
- {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM2, CSU_S_SUP_RW},
{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
{CSU_CSLX_PCIE2, CSU_ALL_RW},
{CSU_CSLX_SATA, CSU_ALL_RW},
diff --git a/plat/nxp/soc-ls1043a/include/soc.h b/plat/nxp/soc-ls1043a/include/soc.h
new file mode 100644
index 0000000..e018102
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/include/soc.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SOC_H
+#define SOC_H
+
+/* Chassis specific defines - common across SoC's of a particular platform */
+#include "dcfg_lsch2.h"
+#include "soc_default_base_addr.h"
+#include "soc_default_helper_macros.h"
+
+/* DDR Regions Info */
+#define NUM_DRAM_REGIONS 3
+#define NXP_DRAM0_ADDR 0x80000000
+#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
+
+#define NXP_DRAM1_ADDR 0x880000000
+#define NXP_DRAM1_MAX_SIZE 0x780000000 /* 30 GB */
+
+#define NXP_DRAM2_ADDR 0x8800000000
+#define NXP_DRAM2_MAX_SIZE 0x7800000000 /* 480 GB */
+/* DRAM0 Size defined in platform_def.h */
+#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
+
+/*
+ * P23: 23 x 23 package
+ * A: without security
+ * AE: with security
+ * SVR Definition (not include major and minor rev)
+ */
+#define SVR_LS1023A 0x879209
+#define SVR_LS1023AE 0x879208
+#define SVR_LS1023A_P23 0x87920B
+#define SVR_LS1023AE_P23 0x87920A
+#define SVR_LS1043A 0x879201
+#define SVR_LS1043AE 0x879200
+#define SVR_LS1043A_P23 0x879203
+#define SVR_LS1043AE_P23 0x879202
+
+/* Number of cores in platform */
+#define PLATFORM_CORE_COUNT 4
+#define NUMBER_OF_CLUSTERS 1
+#define CORES_PER_CLUSTER 4
+
+/* set to 0 if the clusters are not symmetrical */
+#define SYMMETRICAL_CLUSTERS 1
+
+/*
+ * Required LS standard platform porting definitions
+ * for CCI-400
+ */
+#define NXP_CCI_CLUSTER0_SL_IFACE_IX 4
+
+/* ls1043 version info for GIC configuration */
+#define REV1_0 0x10
+#define REV1_1 0x11
+#define GIC_ADDR_BIT 31
+
+/* Errata */
+#define NXP_ERRATUM_A009663
+#define NXP_ERRATUM_A009942
+
+#define NUM_OF_DDRC 1
+
+/* Defines required for using XLAT tables from ARM common code */
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40)
+
+/* Clock Divisors */
+#define NXP_PLATFORM_CLK_DIVIDER 1
+#define NXP_UART_CLK_DIVIDER 1
+
+/*
+ * Set this switch to 1 if you need to keep the debug block
+ * clocked during system power-down.
+ */
+#define DEBUG_ACTIVE 0
+
+#define IPPDEXPCR_MAC1_1 0x80000000 // DEVDISR2_FMAN1_MAC1
+#define IPPDEXPCR_MAC1_2 0x40000000 // DEVDISR2_FMAN1_MAC2
+#define IPPDEXPCR_MAC1_3 0x20000000 // DEVDISR2_FMAN1_MAC3
+#define IPPDEXPCR_MAC1_4 0x10000000 // DEVDISR2_FMAN1_MAC4
+#define IPPDEXPCR_MAC1_5 0x08000000 // DEVDISR2_FMAN1_MAC5
+#define IPPDEXPCR_MAC1_6 0x04000000 // DEVDISR2_FMAN1_MAC6
+#define IPPDEXPCR_MAC1_9 0x00800000 // DEVDISR2_FMAN1_MAC9
+#define IPPDEXPCR_I2C1 0x00080000 // DEVDISR5_I2C_1
+#define IPPDEXPCR_LPUART1 0x00040000 // DEVDISR5_LPUART1
+#define IPPDEXPCR_FLX_TMR1 0x00020000 // DEVDISR5_FLX_TMR
+#define IPPDEXPCR_OCRAM1 0x00010000 // DEVDISR5_OCRAM1
+#define IPPDEXPCR_GPIO1 0x00000040 // DEVDISR5_GPIO
+#define IPPDEXPCR_FM1 0x00000008 // DEVDISR2_FMAN1
+
+#define IPPDEXPCR_MASK1 0xFC800008 // overrides for DEVDISR2
+#define IPPDEXPCR_MASK2 0x000F0040 // overriddes for DEVDISR5
+
+#define IPSTPCR0_VALUE 0xA000C201
+#define IPSTPCR1_VALUE 0x00000080
+#define IPSTPCR2_VALUE 0x000C0000
+#define IPSTPCR3_VALUE 0x38000000
+#if (DEBUG_ACTIVE)
+ #define IPSTPCR4_VALUE 0x10833BFC
+#else
+ #define IPSTPCR4_VALUE 0x10A33BFC
+#endif
+
+#define DEVDISR1_QE 0x00000001
+#define DEVDISR1_SEC 0x00000200
+#define DEVDISR1_USB1 0x00004000
+#define DEVDISR1_SATA 0x00008000
+#define DEVDISR1_USB2 0x00010000
+#define DEVDISR1_USB3 0x00020000
+#define DEVDISR1_DMA2 0x00400000
+#define DEVDISR1_DMA1 0x00800000
+#define DEVDISR1_ESDHC 0x20000000
+#define DEVDISR1_PBL 0x80000000
+
+#define DEVDISR2_FMAN1 0x00000080
+#define DEVDISR2_FMAN1_MAC9 0x00800000
+#define DEVDISR2_FMAN1_MAC6 0x04000000
+#define DEVDISR2_FMAN1_MAC5 0x08000000
+#define DEVDISR2_FMAN1_MAC4 0x10000000
+#define DEVDISR2_FMAN1_MAC3 0x20000000
+#define DEVDISR2_FMAN1_MAC2 0x40000000
+#define DEVDISR2_FMAN1_MAC1 0x80000000
+
+#define DEVDISR3_BMAN 0x00040000
+#define DEVDISR3_QMAN 0x00080000
+#define DEVDISR3_PEX3 0x20000000
+#define DEVDISR3_PEX2 0x40000000
+#define DEVDISR3_PEX1 0x80000000
+
+#define DEVDISR4_QSPI 0x08000000
+#define DEVDISR4_DUART2 0x10000000
+#define DEVDISR4_DUART1 0x20000000
+
+#define DEVDISR5_ICMMU 0x00000001
+#define DEVDISR5_I2C_1 0x00000002
+#define DEVDISR5_I2C_2 0x00000004
+#define DEVDISR5_I2C_3 0x00000008
+#define DEVDISR5_I2C_4 0x00000010
+#define DEVDISR5_WDG_5 0x00000020
+#define DEVDISR5_WDG_4 0x00000040
+#define DEVDISR5_WDG_3 0x00000080
+#define DEVDISR5_DSPI1 0x00000100
+#define DEVDISR5_WDG_2 0x00000200
+#define DEVDISR5_FLX_TMR 0x00000400
+#define DEVDISR5_WDG_1 0x00000800
+#define DEVDISR5_LPUART6 0x00001000
+#define DEVDISR5_LPUART5 0x00002000
+#define DEVDISR5_LPUART3 0x00008000
+#define DEVDISR5_LPUART2 0x00010000
+#define DEVDISR5_LPUART1 0x00020000
+#define DEVDISR5_DBG 0x00200000
+#define DEVDISR5_GPIO 0x00400000
+#define DEVDISR5_IFC 0x00800000
+#define DEVDISR5_OCRAM2 0x01000000
+#define DEVDISR5_OCRAM1 0x02000000
+#define DEVDISR5_LPUART4 0x10000000
+#define DEVDISR5_DDR 0x80000000
+#define DEVDISR5_MEM 0x80000000
+
+#define DEVDISR1_VALUE 0xA0C3C201
+#define DEVDISR2_VALUE 0xCC0C0080
+#define DEVDISR3_VALUE 0xE00C0000
+#define DEVDISR4_VALUE 0x38000000
+#if (DEBUG_ACTIVE)
+ #define DEVDISR5_VALUE 0x10833BFC
+#else
+ #define DEVDISR5_VALUE 0x10A33BFC
+#endif
+
+/*
+ * PWR mgmt features supported in the soc-specific code:
+ * value == 0x0 the soc code does not support this feature
+ * value != 0x0 the soc code supports this feature
+ */
+#define SOC_CORE_RELEASE 0x1
+#define SOC_CORE_RESTART 0x1
+#define SOC_CORE_OFF 0x1
+#define SOC_CORE_STANDBY 0x1
+#define SOC_CORE_PWR_DWN 0x1
+#define SOC_CLUSTER_STANDBY 0x1
+#define SOC_CLUSTER_PWR_DWN 0x1
+#define SOC_SYSTEM_STANDBY 0x1
+#define SOC_SYSTEM_PWR_DWN 0x1
+#define SOC_SYSTEM_OFF 0x1
+#define SOC_SYSTEM_RESET 0x1
+
+/* PSCI-specific defines */
+#define SYSTEM_PWR_DOMAINS 1
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
+ NUMBER_OF_CLUSTERS + \
+ SYSTEM_PWR_DOMAINS)
+
+/* Power state coordination occurs at the system level */
+#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL
+
+/* Local power state for power domains in Run state */
+#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN
+
+/* define retention state */
+#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
+#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
+
+/* define power-down state */
+#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
+#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ * CACHE_WRITEBACK_GRANULE is defined in soc.def
+ */
+
+/* One cache line needed for bakery locks on ARM platforms */
+#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
+
+#ifndef __ASSEMBLER__
+/* CCI slave interfaces */
+static const int cci_map[] = {
+ NXP_CCI_CLUSTER0_SL_IFACE_IX,
+};
+void soc_init_lowlevel(void);
+void soc_init_percpu(void);
+void _soc_set_start_addr(unsigned long addr);
+
+#endif
+
+#endif /* SOC_H */
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c b/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
new file mode 100644
index 0000000..2231c18
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+
+#include <errata.h>
+#include <platform_def.h>
+
+#ifdef CONFIG_STATIC_DDR
+const struct ddr_cfg_regs static_1600 = {
+ .cs[0].config = U(0x80040322),
+ .cs[0].bnds = U(0x7F),
+ .sdram_cfg[0] = U(0xC50C0000),
+ .sdram_cfg[1] = U(0x401100),
+ .timing_cfg[0] = U(0x91550018),
+ .timing_cfg[1] = U(0xBBB48C42),
+ .timing_cfg[2] = U(0x48C111),
+ .timing_cfg[3] = U(0x10C1000),
+ .timing_cfg[4] = U(0x2),
+ .timing_cfg[5] = U(0x3401400),
+ .timing_cfg[7] = U(0x13300000),
+ .timing_cfg[8] = U(0x2115600),
+ .sdram_mode[0] = U(0x3010210),
+ .sdram_mode[9] = U(0x4000000),
+ .sdram_mode[8] = U(0x500),
+ .sdram_mode[2] = U(0x10210),
+ .sdram_mode[10] = U(0x400),
+ .sdram_mode[11] = U(0x4000000),
+ .sdram_mode[4] = U(0x10210),
+ .sdram_mode[12] = U(0x400),
+ .sdram_mode[13] = U(0x4000000),
+ .sdram_mode[6] = U(0x10210),
+ .sdram_mode[14] = U(0x400),
+ .sdram_mode[15] = U(0x4000000),
+ .interval = U(0x18600618),
+ .zq_cntl = U(0x8A090705),
+ .clk_cntl = U(0x3000000),
+ .cdr[0] = U(0x80040000),
+ .cdr[1] = U(0xA181),
+ .wrlvl_cntl[0] = U(0x8675F607),
+ .wrlvl_cntl[1] = U(0x7090807,
+ .wrlvl_cntl[2] = U(0x7070707),
+ .debug[28] = U(0x00700046),
+};
+
+uint64_t board_static_ddr(struct ddr_info *priv)
+{
+ memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
+
+ return ULL(0x80000000);
+}
+
+#else
+static const struct rc_timing rcz[] = {
+ {1600, 12, 7},
+ {}
+};
+
+static const struct board_timing ram[] = {
+ {0x1f, rcz, 0x00020100, 0},
+};
+
+int ddr_board_options(struct ddr_info *priv)
+{
+ int ret;
+ struct memctl_opt *popts = &priv->opt;
+
+ ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
+ if (ret)
+ return ret;
+
+ popts->cpo_sample = U(0x46);
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+
+ return 0;
+}
+
+/* DDR model number: MT40A512M8HX-093E */
+struct dimm_params ddr_raw_timing = {
+ .n_ranks = U(1),
+ .rank_density = ULL(2147483648),
+ .capacity = ULL(2147483648),
+ .primary_sdram_width = U(32),
+ .n_row_addr = U(15),
+ .n_col_addr = U(10),
+ .bank_group_bits = U(2),
+ .burst_lengths_bitmask = U(0x0c),
+ .tckmin_x_ps = 938,
+ .tckmax_ps = 1500,
+ .caslat_x = U(0x000DFA00),
+ .taa_ps = 13500,
+ .trcd_ps = 13500,
+ .trp_ps = 13500,
+ .tras_ps = 33000,
+ .trc_ps = 46500,
+ .twr_ps = 15000,
+ .trfc1_ps = 260000,
+ .trfc2_ps = 160000,
+ .trfc4_ps = 110000,
+ .tfaw_ps = 21000,
+ .trrds_ps = 3700,
+ .trrdl_ps = 5300,
+ .tccdl_ps = 5355,
+ .refresh_rate_ps = U(7800000),
+ .rc = U(0x1f),
+};
+
+int ddr_get_ddr_params(struct dimm_params *pdimm,
+ struct ddr_conf *conf)
+{
+ static const char dimm_model[] = "Fixed DDR on board";
+
+ conf->dimm_in_use[0] = 1;
+ memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+
+ return 1;
+}
+#endif
+
+int64_t init_ddr(void)
+{
+ struct ddr_info info;
+ struct sysinfo sys;
+ int64_t dram_size;
+
+ zeromem(&sys, sizeof(sys));
+ get_clocks(&sys);
+ debug("platform clock %lu\n", sys.freq_platform);
+ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+ zeromem(&info, sizeof(struct ddr_info));
+ info.num_ctlrs = 1;
+ info.dimm_on_ctlr = 1;
+ info.clk = get_ddr_freq(&sys, 0);
+ info.ddr[0] = (void *)NXP_DDR_ADDR;
+
+ dram_size = dram_init(&info);
+
+ if (dram_size < 0) {
+ ERROR("DDR init failed\n");
+ }
+
+#ifdef ERRATA_SOC_A008850
+ erratum_a008850_post();
+#endif
+ return dram_size;
+}
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/plat_def.h b/plat/nxp/soc-ls1043a/ls1043ardb/plat_def.h
new file mode 100644
index 0000000..249f457
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/plat_def.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+/*
+ * Required without TBBR.
+ * To include the defines for DDR PHY Images.
+ */
+#include <tbbr_img_def.h>
+
+#include "policy.h"
+#include <soc.h>
+
+#define NXP_SPD_EEPROM0 0x51
+
+#define NXP_SYSCLK_FREQ 100000000
+#define NXP_DDRCLK_FREQ 100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE 115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE 0x2000
+#else
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE (0x00100000)
+#define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000)
+
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES 3
+#define MAX_IO_BLOCK_DEVICES 1
+#define MAX_IO_HANDLES 4
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES 2
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES 1
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER 29
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+
+#define PLAT_LS_G0_IRQ_PROPS(grp)
+
+#endif /* PLAT_DEF_H */
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/platform.c b/plat/nxp/soc-ls1043a/ls1043ardb/platform.c
new file mode 100644
index 0000000..65d508c
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/platform.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/platform.mk b/plat/nxp/soc-ls1043a/ls1043ardb/platform.mk
new file mode 100644
index 0000000..5d23356
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/platform.mk
@@ -0,0 +1,40 @@
+#
+# Copyright 2018-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+
+BOOT_MODE ?= nor
+BOARD := ls1043ardb
+POVDD_ENABLE := no
+
+# DDR Compilation Configs
+CONFIG_DDR_NODIMM := 1
+NUM_OF_DDRC := 1
+DDRC_NUM_DIMM := 0
+DDRC_NUM_CS := 4
+DDR_ECC_EN := no
+CONFIG_STATIC_DDR := 0
+
+# On-Board Flash Details
+# 128MB IFC NOR Flash
+NOR_FLASH_SZ := 0x8000000
+
+# Platform specific features.
+WARM_BOOT := no
+
+# Adding Platform files build files
+BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
+ ${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE := nor \
+ sd \
+ nand
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
+include plat/nxp/soc-ls1043a/soc.mk
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h b/plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h
new file mode 100644
index 0000000..4721a32
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat_def.h>
+#include <plat_default_def.h>
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/policy.h b/plat/nxp/soc-ls1043a/ls1043ardb/policy.h
new file mode 100644
index 0000000..843b5e2
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/policy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef POLICY_H
+#define POLICY_H
+
+/*
+ * Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+#endif /* POLICY_H */
diff --git a/plat/nxp/soc-ls1043a/soc.c b/plat/nxp/soc-ls1043a/soc.c
new file mode 100644
index 0000000..7badf8c
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/soc.c
@@ -0,0 +1,435 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <caam.h>
+#include <cassert.h>
+#include <cci.h>
+#include <common/debug.h>
+#include <dcfg.h>
+#ifdef I2C_INIT
+#include <i2c.h>
+#endif
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <ls_interconnect.h>
+#ifdef POLICY_FUSE_PROVISION
+#include <nxp_gpio.h>
+#endif
+#if TRUSTED_BOARD_BOOT
+#include <nxp_smmu.h>
+#endif
+#include <nxp_timer.h>
+#include <plat_console.h>
+#include <plat_gic.h>
+#include <plat_tzc380.h>
+#include <scfg.h>
+#if defined(NXP_SFP_ENABLED)
+#include <sfp.h>
+#endif
+
+#include <errata.h>
+#include <ns_access.h>
+#ifdef CONFIG_OCRAM_ECC_EN
+#include <ocram.h>
+#endif
+#include <plat_common.h>
+#include <platform_def.h>
+#include <soc.h>
+
+static dcfg_init_info_t dcfg_init_data = {
+ .g_nxp_dcfg_addr = NXP_DCFG_ADDR,
+ .nxp_sysclk_freq = NXP_SYSCLK_FREQ,
+ .nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
+ .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
+ };
+
+
+/* Function to return the SoC SYS CLK */
+unsigned int get_sys_clk(void)
+{
+ return NXP_SYSCLK_FREQ;
+}
+
+/*
+ * Function returns the base counter frequency
+ * after reading the first entry at CNTFID0 (0x20 offset).
+ *
+ * Function is used by:
+ * 1. ARM common code for PSCI management.
+ * 2. ARM Generic Timer init.
+ *
+ */
+unsigned int plat_get_syscnt_freq2(void)
+{
+ unsigned int counter_base_frequency;
+
+ counter_base_frequency = get_sys_clk()/4;
+
+ return counter_base_frequency;
+}
+
+#ifdef IMAGE_BL2
+
+static struct soc_type soc_list[] = {
+ SOC_ENTRY(LS1023A, LS1023A, 1, 2),
+ SOC_ENTRY(LS1023AE, LS1023AE, 1, 2),
+ SOC_ENTRY(LS1023A_P23, LS1023A_P23, 1, 2),
+ SOC_ENTRY(LS1023AE_P23, LS1023AE_P23, 1, 2),
+ SOC_ENTRY(LS1043A, LS1043A, 1, 4),
+ SOC_ENTRY(LS1043AE, LS1043AE, 1, 4),
+ SOC_ENTRY(LS1043A_P23, LS1043A_P23, 1, 4),
+ SOC_ENTRY(LS1043AE_P23, LS1043AE_P23, 1, 4),
+};
+
+#ifdef POLICY_FUSE_PROVISION
+static gpio_init_info_t gpio_init_data = {
+ .gpio1_base_addr = NXP_GPIO1_ADDR,
+ .gpio2_base_addr = NXP_GPIO2_ADDR,
+ .gpio3_base_addr = NXP_GPIO3_ADDR,
+ .gpio4_base_addr = NXP_GPIO4_ADDR,
+};
+#endif
+
+/*
+ * Function to set the base counter frequency at
+ * the first entry of the Frequency Mode Table,
+ * at CNTFID0 (0x20 offset).
+ *
+ * Set the value of the pirmary core register cntfrq_el0.
+ */
+static void set_base_freq_CNTFID0(void)
+{
+ /*
+ * Below register specifies the base frequency of the system counter.
+ * As per NXP Board Manuals:
+ * The system counter always works with SYS_REF_CLK/4 frequency clock.
+ *
+ */
+ unsigned int counter_base_frequency = get_sys_clk()/4;
+
+ /*
+ * Setting the frequency in the Frequency modes table.
+ *
+ * Note: The value for ls1046ardb board at this offset
+ * is not RW as stated. This offset have the
+ * fixed value of 100000400 Hz.
+ *
+ * The below code line has no effect.
+ * Keeping it for other platforms where it has effect.
+ */
+ mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency);
+
+ write_cntfrq_el0(counter_base_frequency);
+}
+
+void soc_preload_setup(void)
+{
+
+}
+
+/*******************************************************************************
+ * This function implements soc specific erratas
+ * This is called before DDR is initialized or MMU is enabled
+ ******************************************************************************/
+void soc_early_init(void)
+{
+ uint8_t num_clusters, cores_per_cluster;
+ dram_regions_info_t *dram_regions_info = get_dram_regions_info();
+
+#ifdef CONFIG_OCRAM_ECC_EN
+ ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
+#endif
+ dcfg_init(&dcfg_init_data);
+#ifdef POLICY_FUSE_PROVISION
+ gpio_init(&gpio_init_data);
+ sec_init(NXP_CAAM_ADDR);
+#endif
+#if LOG_LEVEL > 0
+ /* Initialize the console to provide early debug support */
+
+ plat_console_init(NXP_CONSOLE_ADDR,
+ NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
+#endif
+ set_base_freq_CNTFID0();
+
+ /* Enable snooping on SEC read and write transactions */
+ scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET),
+ SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP);
+
+ /*
+ * Initialize Interconnect for this cluster during cold boot.
+ * No need for locks as no other CPU is active.
+ */
+ cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
+
+ /*
+ * Enable Interconnect coherency for the primary CPU's cluster.
+ */
+ get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
+ plat_ls_interconnect_enter_coherency(num_clusters);
+
+#if TRUSTED_BOARD_BOOT
+ uint32_t mode;
+
+ sfp_init(NXP_SFP_ADDR);
+ /*
+ * For secure boot disable SMMU.
+ * Later when platform security policy comes in picture,
+ * this might get modified based on the policy
+ */
+ if (check_boot_mode_secure(&mode) == true) {
+ bypass_smmu(NXP_SMMU_ADDR);
+ }
+
+ /*
+ * For Mbedtls currently crypto is not supported via CAAM
+ * enable it when that support is there. In tbbr.mk
+ * the CAAM_INTEG is set as 0.
+ */
+
+#ifndef MBEDTLS_X509
+ /* Initialize the crypto accelerator if enabled */
+ if (is_sec_enabled() == false) {
+ INFO("SEC is disabled.\n");
+ } else {
+ sec_init(NXP_CAAM_ADDR);
+ }
+#endif
+#elif defined(POLICY_FUSE_PROVISION)
+ gpio_init(&gpio_init_data);
+ sfp_init(NXP_SFP_ADDR);
+ sec_init(NXP_CAAM_ADDR);
+#endif
+
+ soc_errata();
+
+ /*
+ * Initialize system level generic timer for Layerscape Socs.
+ */
+ delay_timer_init(NXP_TIMER_ADDR);
+
+#ifdef DDR_INIT
+ i2c_init(NXP_I2C_ADDR);
+ dram_regions_info->total_dram_size = init_ddr();
+#endif
+}
+
+void soc_bl2_prepare_exit(void)
+{
+#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
+ set_sfp_wr_disable();
+#endif
+}
+
+/*****************************************************************************
+ * This function returns the boot device based on RCW_SRC
+ ****************************************************************************/
+enum boot_device get_boot_dev(void)
+{
+ enum boot_device src = BOOT_DEVICE_NONE;
+ uint32_t porsr1;
+ uint32_t rcw_src, val;
+
+ porsr1 = read_reg_porsr1();
+
+ rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
+
+ val = rcw_src & RCW_SRC_NAND_MASK;
+
+ if (val == RCW_SRC_NAND_VAL) {
+ val = rcw_src & NAND_RESERVED_MASK;
+ if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
+ src = BOOT_DEVICE_IFC_NAND;
+ INFO("RCW BOOT SRC is IFC NAND\n");
+ }
+ } else {
+ /* RCW SRC NOR */
+ val = rcw_src & RCW_SRC_NOR_MASK;
+ if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
+ src = BOOT_DEVICE_IFC_NOR;
+ INFO("RCW BOOT SRC is IFC NOR\n");
+ } else {
+ switch (rcw_src) {
+ case QSPI_VAL1:
+ case QSPI_VAL2:
+ src = BOOT_DEVICE_QSPI;
+ INFO("RCW BOOT SRC is QSPI\n");
+ break;
+ case SD_VAL:
+ src = BOOT_DEVICE_EMMC;
+ INFO("RCW BOOT SRC is SD/EMMC\n");
+ break;
+ default:
+ src = BOOT_DEVICE_NONE;
+ }
+ }
+ }
+
+ return src;
+}
+
+/* This function sets up access permissions on memory regions */
+void soc_mem_access(void)
+{
+ struct tzc380_reg tzc380_reg_list[MAX_NUM_TZC_REGION];
+ int dram_idx, index = 0U;
+ dram_regions_info_t *info_dram_regions = get_dram_regions_info();
+
+ for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions;
+ dram_idx++) {
+ if (info_dram_regions->region[dram_idx].size == 0) {
+ ERROR("DDR init failure, or");
+ ERROR("DRAM regions not populated correctly.\n");
+ break;
+ }
+
+ index = populate_tzc380_reg_list(tzc380_reg_list,
+ dram_idx, index,
+ info_dram_regions->region[dram_idx].addr,
+ info_dram_regions->region[dram_idx].size,
+ NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
+ }
+
+ mem_access_setup(NXP_TZC_ADDR, index, tzc380_reg_list);
+
+ /* Configure CSU secure access register to disable TZASC bypass mux */
+ mmio_write_32((uintptr_t)(NXP_CSU_ADDR +
+ CSU_SEC_ACCESS_REG_OFFSET),
+ bswap32(TZASC_BYPASS_MUX_DISABLE));
+}
+
+
+#else
+const unsigned char _power_domain_tree_desc[] = {1, 1, 4};
+
+CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
+ assert_invalid_ls1043_cluster_count);
+
+/* This function returns the SoC topology */
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+
+ return _power_domain_tree_desc;
+}
+
+/*
+ * This function returns the core count within the cluster corresponding to
+ * `mpidr`.
+ */
+unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
+{
+ return CORES_PER_CLUSTER;
+}
+
+void soc_early_platform_setup2(void)
+{
+ dcfg_init(&dcfg_init_data);
+ /* Initialize system level generic timer for Socs */
+ delay_timer_init(NXP_TIMER_ADDR);
+
+#if LOG_LEVEL > 0
+ /* Initialize the console to provide early debug support */
+ plat_console_init(NXP_CONSOLE_ADDR,
+ NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
+#endif
+}
+
+/*
+ * For LS1043a rev1.0, GIC base address align with 4k.
+ * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
+ * is set, GIC base address align with 4K, or else align
+ * with 64k.
+ */
+void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
+{
+ uint32_t *ccsr_svr = (uint32_t *)(NXP_DCFG_ADDR + DCFG_SVR_OFFSET);
+ uint32_t *gic_align = (uint32_t *)(NXP_SCFG_ADDR +
+ SCFG_GIC400_ADDR_ALIGN_OFFSET);
+ uint32_t val;
+
+ val = be32toh(mmio_read_32((uintptr_t)ccsr_svr));
+
+ if ((val & 0xff) == REV1_1) {
+ val = be32toh(mmio_read_32((uintptr_t)gic_align));
+ if (val & (1L << GIC_ADDR_BIT)) {
+ *gicc_base = NXP_GICC_4K_ADDR;
+ *gicd_base = NXP_GICD_4K_ADDR;
+ } else {
+ *gicc_base = NXP_GICC_64K_ADDR;
+ *gicd_base = NXP_GICD_64K_ADDR;
+ }
+ } else {
+ *gicc_base = NXP_GICC_4K_ADDR;
+ *gicd_base = NXP_GICD_4K_ADDR;
+ }
+}
+
+void soc_platform_setup(void)
+{
+ /* Initialize the GIC driver, cpu and distributor interfaces */
+ static uint32_t target_mask_array[PLATFORM_CORE_COUNT];
+ /*
+ * On a GICv2 system, the Group 1 secure interrupts are treated
+ * as Group 0 interrupts.
+ */
+ static interrupt_prop_t ls_interrupt_props[] = {
+ PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
+ PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
+ };
+ static uint32_t gicc_base, gicd_base;
+
+ get_gic_offset(&gicc_base, &gicd_base);
+ plat_ls_gic_driver_init(gicd_base, gicc_base,
+ PLATFORM_CORE_COUNT,
+ ls_interrupt_props,
+ ARRAY_SIZE(ls_interrupt_props),
+ target_mask_array);
+
+ plat_ls_gic_init();
+ enable_init_timer();
+}
+
+/* This function initializes the soc from the BL31 module */
+void soc_init(void)
+{
+ /* low-level init of the soc */
+ soc_init_lowlevel();
+ _init_global_data();
+ soc_init_percpu();
+ _initialize_psci();
+
+ /*
+ * Initialize the interconnect during cold boot.
+ * No need for locks as no other CPU is active.
+ */
+ cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
+
+ /*
+ * Enable coherency in interconnect for the primary CPU's cluster.
+ * Earlier bootloader stages might already do this but we can't
+ * assume so. No harm in executing this code twice.
+ */
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+
+ /* Init CSU to enable non-secure access to peripherals */
+ enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR);
+
+ /* Initialize the crypto accelerator if enabled */
+ if (is_sec_enabled() == false) {
+ INFO("SEC is disabled.\n");
+ } else {
+ sec_init(NXP_CAAM_ADDR);
+ }
+}
+
+void soc_runtime_setup(void)
+{
+
+}
+#endif
diff --git a/plat/nxp/soc-ls1043a/soc.def b/plat/nxp/soc-ls1043a/soc.def
new file mode 100644
index 0000000..b174bd6
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/soc.def
@@ -0,0 +1,107 @@
+#
+# Copyright 2017-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# This file contains the basic architecture definitions that drive the build
+#
+# -----------------------------------------------------------------------------
+
+CORE_TYPE := a53
+
+CACHE_LINE := 6
+
+# set to GIC400 or GIC500
+GIC := GIC400
+
+# set to CCI400 or CCN504 or CCN508
+INTERCONNECT := CCI400
+
+# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
+CHASSIS := 2
+
+# TZC IP Details TZC used is TZC380 or TZC400
+TZC_ID := TZC380
+
+# CONSOLE Details available is NS16550 or PL011
+CONSOLE := NS16550
+
+# Select the DDR PHY generation to be used
+PLAT_DDR_PHY := PHY_GEN1
+
+PHYS_SYS := 64
+
+# ddr controller - set to MMDC or NXP
+DDRCNTLR := NXP
+
+# ddr phy - set to NXP or SNPS
+DDRPHY := NXP
+
+# Area of OCRAM reserved by ROM code
+NXP_ROM_RSVD := 0x5900
+
+# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
+# Input to CST create_hdr_esbc tool
+CSF_HDR_SZ := 0x3000
+
+# In IMAGE_BL2, compile time flag for handling Cache coherency
+# with CAAM for BL2 running from OCRAM
+SEC_MEM_NON_COHERENT := yes
+
+# OCRAM MAP
+OCRAM_START_ADDR := 0x10000000
+OCRAM_SIZE := 0x20000
+
+# BL2 binary is placed at start of OCRAM.
+# Also used by create_pbl.mk.
+BL2_BASE := 0x10000000
+
+# After BL2 bin, OCRAM is used by ROM Code:
+# (OCRAM_START_ADDR + BL2_BIN_SIZE) -> (NXP_ROM_RSVD - 1)
+
+# After ROM Code, OCRAM is used by CSF header.
+# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1)
+
+# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ)
+# This value should be greater than BL2_TEXT_LIMIT
+# Input to CST create_hdr_isbc tool
+BL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ))))
+# Covert to HEX to be used by create_pbl.mk
+BL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
+
+# Core Errata
+ERRATA_A53_855873 := 1
+ERRATA_A53_1530924 := 1
+
+# SoC ERRATAS to be enabled
+ERRATA_SOC_A008850 := 1
+ERRATA_SOC_A010539 := 1
+ERRATA_SOC_A009660 := 1
+
+# DDR Errata
+ERRATA_DDR_A009663 := 1
+ERRATA_DDR_A009942 := 1
+
+# enable dynamic memory mapping
+PLAT_XLAT_TABLES_DYNAMIC := 1
+
+# Define Endianness of each module
+NXP_GUR_ENDIANNESS := BE
+NXP_DDR_ENDIANNESS := BE
+NXP_SEC_ENDIANNESS := BE
+NXP_SFP_ENDIANNESS := BE
+NXP_SNVS_ENDIANNESS := BE
+NXP_ESDHC_ENDIANNESS := BE
+NXP_QSPI_ENDIANNESS := BE
+NXP_FSPI_ENDIANNESS := BE
+NXP_SCFG_ENDIANNESS := BE
+NXP_GPIO_ENDIANNESS := BE
+NXP_IFC_ENDIANNESS := BE
+
+NXP_SFP_VER := 3_2
+
+# OCRAM ECC Enabled
+OCRAM_ECC_EN := yes
diff --git a/plat/nxp/soc-ls1043a/soc.mk b/plat/nxp/soc-ls1043a/soc.mk
new file mode 100644
index 0000000..b6ce14e
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/soc.mk
@@ -0,0 +1,114 @@
+#
+# Copyright 2018-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# SoC-specific build parameters
+SOC := ls1043a
+PLAT_PATH := plat/nxp
+PLAT_COMMON_PATH := plat/nxp/common
+PLAT_DRIVERS_PATH := drivers/nxp
+PLAT_SOC_PATH := ${PLAT_PATH}/soc-${SOC}
+BOARD_PATH := ${PLAT_SOC_PATH}/${BOARD}
+
+# get SoC-specific defnitions
+include ${PLAT_SOC_PATH}/soc.def
+include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
+include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
+
+# For Security Features
+DISABLE_FUSE_WRITE := 1
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
+SECURE_BOOT := yes
+endif
+$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
+
+# Selecting Drivers for SoC
+$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,CSU_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
+$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
+
+# Selecting PSCI & SIP_SVC support
+$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
+$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
+
+# Source File Addition
+PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/include/default\
+ -I${BOARD_PATH}\
+ -I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
+ -I${PLAT_SOC_PATH}/include\
+ -I${PLAT_COMMON_PATH}/soc_errata
+
+ifeq (${SECURE_BOOT},yes)
+include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
+endif
+
+ifeq ($(WARM_BOOT),yes)
+include ${PLAT_COMMON_PATH}/warm_reset/warm_reset.mk
+endif
+
+ifeq (${NXP_NV_SW_MAINT_LAST_EXEC_DATA}, yes)
+include ${PLAT_COMMON_PATH}/nv_storage/nv_storage.mk
+endif
+
+ifeq (${PSCI_NEEDED}, yes)
+include ${PLAT_COMMON_PATH}/psci/psci.mk
+endif
+
+ifeq (${SIPSVC_NEEDED}, yes)
+include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
+endif
+
+# for fuse-fip & fuse-programming
+ifeq (${FUSE_PROG}, 1)
+include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
+endif
+
+ifeq (${IMG_LOADR_NEEDED},yes)
+include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
+endif
+
+# Adding source files for the above selected drivers.
+include ${PLAT_DRIVERS_PATH}/drivers.mk
+
+# Adding SoC specific files
+include ${PLAT_COMMON_PATH}/soc_errata/errata.mk
+
+PLAT_INCLUDES += ${NV_STORAGE_INCLUDES}\
+ ${WARM_RST_INCLUDES}
+
+BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
+ ${WARM_RST_BL31_SOURCES}\
+ ${PSCI_SOURCES}\
+ ${SIPSVC_SOURCES}\
+ ${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
+
+PLAT_BL_COMMON_SOURCES += ${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
+ ${PLAT_SOC_PATH}/aarch64/${SOC}_helpers.S\
+ ${NV_STORAGE_SOURCES}\
+ ${WARM_RST_BL_COMM_SOURCES}\
+ ${PLAT_SOC_PATH}/soc.c
+
+ifeq (${TEST_BL31}, 1)
+BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S\
+ ${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
+endif
+
+BL2_SOURCES += ${DDR_CNTLR_SOURCES}\
+ ${TBBR_SOURCES}\
+ ${FUSE_SOURCES}
+
+# Adding TFA setup files
+include ${PLAT_PATH}/common/setup/common.mk
diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk
index 0d88d65..aef0ad1 100644
--- a/plat/renesas/common/common.mk
+++ b/plat/renesas/common/common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2022, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -17,6 +17,11 @@
CRASH_REPORTING := 1
HANDLE_EA_EL3_FIRST := 1
+# This option gets enabled automatically if the TRUSTED_BOARD_BOOT
+# is set via root Makefile, but Renesas support Trusted-Boot without
+# Crypto module.
+override CRYPTO_SUPPORT := 0
+
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
ifeq (${SPD},none)
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 3c6f48a..0c93f27 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -308,6 +308,8 @@
print_reset_reason();
+ stm32mp1_syscfg_enable_io_compensation_finish();
+
#if !STM32MP_USE_STM32IMAGE
fconf_populate("TB_FW", STM32MP_DTB_BASE);
#endif /* !STM32MP_USE_STM32IMAGE */
diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index 2eec16f..38de1b7 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,7 +18,8 @@
void stm32mp1_gic_init(void);
void stm32mp1_syscfg_init(void);
-void stm32mp1_syscfg_enable_io_compensation(void);
+void stm32mp1_syscfg_enable_io_compensation_start(void);
+void stm32mp1_syscfg_enable_io_compensation_finish(void);
void stm32mp1_syscfg_disable_io_compensation(void);
void stm32mp1_deconfigure_uart_pins(void);
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index 793ad71..01a6439 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -1,16 +1,17 @@
/*
- * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <platform_def.h>
-
#include <common/debug.h>
+#include <drivers/clk.h>
+#include <drivers/delay_timer.h>
#include <drivers/st/bsec.h>
#include <drivers/st/stpmic1.h>
#include <lib/mmio.h>
+#include <platform_def.h>
#include <stm32mp_dt.h>
#include <stm32mp1_private.h>
@@ -24,6 +25,9 @@
#define SYSCFG_CMPENSETR 0x24U
#define SYSCFG_CMPENCLRR 0x28U
+#define CMPCR_CMPENSETR_OFFSET 0x4U
+#define CMPCR_CMPENCLRR_OFFSET 0x8U
+
/*
* SYSCFG_BOOTR Register
*/
@@ -54,28 +58,66 @@
#define SYSCFG_CMPCR_RAPSRC GENMASK(23, 20)
#define SYSCFG_CMPCR_ANSRC_SHIFT 24
+#define SYSCFG_CMPCR_READY_TIMEOUT_US 10000U
+
/*
* SYSCFG_CMPENSETR Register
*/
#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
-void stm32mp1_syscfg_init(void)
+static void enable_io_comp_cell_finish(uintptr_t cmpcr_off)
{
- uint32_t bootr;
- uint32_t otp = 0;
- uint32_t vdd_voltage;
+ uint64_t start;
- /*
- * Interconnect update : select master using the port 1.
- * LTDC = AXI_M9.
- */
- mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
+ start = timeout_init_us(SYSCFG_CMPCR_READY_TIMEOUT_US);
- /* Disable Pull-Down for boot pin connected to VDD */
- bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
- SYSCFG_BOOTR_BOOT_MASK;
- mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
- bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
+ while ((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) {
+ if (timeout_elapsed(start)) {
+ /* Failure on IO compensation enable is not a issue: warn only. */
+ WARN("IO compensation cell not ready\n");
+ break;
+ }
+ }
+
+ mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_SW_CTRL);
+}
+
+static void disable_io_comp_cell(uintptr_t cmpcr_off)
+{
+ uint32_t value;
+
+ if (((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) ||
+ ((mmio_read_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENSETR_OFFSET) &
+ SYSCFG_CMPENSETR_MPU_EN) == 0U)) {
+ return;
+ }
+
+ value = mmio_read_32(SYSCFG_BASE + cmpcr_off) >> SYSCFG_CMPCR_ANSRC_SHIFT;
+
+ mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
+
+ value <<= SYSCFG_CMPCR_RANSRC_SHIFT;
+ value |= mmio_read_32(SYSCFG_BASE + cmpcr_off);
+
+ mmio_write_32(SYSCFG_BASE + cmpcr_off, value | SYSCFG_CMPCR_SW_CTRL);
+
+ mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN);
+}
+
+static void enable_high_speed_mode_low_voltage(void)
+{
+ mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
+ SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
+ SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
+ SYSCFG_IOCTRLSETR_HSLVEN_ETH |
+ SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
+ SYSCFG_IOCTRLSETR_HSLVEN_SPI);
+}
+
+static void stm32mp1_syscfg_set_hslv(void)
+{
+ uint32_t otp = 0;
+ uint32_t vdd_voltage;
/*
* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
@@ -105,12 +147,7 @@
if (vdd_voltage == 0U) {
WARN("VDD unknown");
} else if (vdd_voltage < 2700000U) {
- mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
- SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
- SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
- SYSCFG_IOCTRLSETR_HSLVEN_ETH |
- SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
- SYSCFG_IOCTRLSETR_HSLVEN_SPI);
+ enable_high_speed_mode_low_voltage();
if (otp == 0U) {
INFO("Product_below_2v5=0: HSLVEN protected by HW\n");
@@ -123,33 +160,50 @@
panic();
}
}
+}
+
+void stm32mp1_syscfg_init(void)
+{
+ uint32_t bootr;
+
+ /*
+ * Interconnect update : select master using the port 1.
+ * LTDC = AXI_M9.
+ */
+ mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
- stm32mp1_syscfg_enable_io_compensation();
+ /* Disable Pull-Down for boot pin connected to VDD */
+ bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
+ SYSCFG_BOOTR_BOOT_MASK;
+ mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
+ bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
+
+ stm32mp1_syscfg_set_hslv();
+
+ stm32mp1_syscfg_enable_io_compensation_start();
}
-void stm32mp1_syscfg_enable_io_compensation(void)
+void stm32mp1_syscfg_enable_io_compensation_start(void)
{
/*
* Activate automatic I/O compensation.
* Warning: need to ensure CSI enabled and ready in clock driver.
* Enable non-secure clock, we assume non-secure is suspended.
*/
- stm32mp1_clk_enable_non_secure(SYSCFG);
+ clk_enable(SYSCFG);
- mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
+ mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPCR,
SYSCFG_CMPENSETR_MPU_EN);
-
- while ((mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) &
- SYSCFG_CMPCR_READY) == 0U) {
- ;
- }
+}
- mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+void stm32mp1_syscfg_enable_io_compensation_finish(void)
+{
+ enable_io_comp_cell_finish(SYSCFG_CMPCR);
}
void stm32mp1_syscfg_disable_io_compensation(void)
{
- uint32_t value;
+ clk_enable(SYSCFG);
/*
* Deactivate automatic I/O compensation.
@@ -157,18 +211,7 @@
* requested for other usages and always OFF in STANDBY.
* Disable non-secure SYSCFG clock, we assume non-secure is suspended.
*/
- value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) >>
- SYSCFG_CMPCR_ANSRC_SHIFT;
-
- mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR,
- SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
-
- value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) |
- (value << SYSCFG_CMPCR_RANSRC_SHIFT);
-
- mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
-
- mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENCLRR, SYSCFG_CMPENSETR_MPU_EN);
+ disable_io_comp_cell(SYSCFG_CMPCR);
- stm32mp1_clk_disable_non_secure(SYSCFG);
+ clk_disable(SYSCFG);
}
diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json
index 3ad853d..404ef90 100644
--- a/tools/conventional-changelog-tf-a/package.json
+++ b/tools/conventional-changelog-tf-a/package.json
@@ -1,6 +1,7 @@
{
"name": "conventional-changelog-tf-a",
- "version": "1.0.0",
+ "version": "2.6.0",
+ "license": "BSD-3-Clause",
"private": true,
"main": "index.js",
"dependencies": {