tree 351d6dc998168666a4d8211372834e523e7d7f26
parent f86a5deace6a1ab527add77b5b3257145b9b5bff
author Andrew F. Davis <afd@ti.com> 1556217210 -0400
committer John Tsichritzis <john.tsichritzis@arm.com> 1559816426 +0100

ti: k3: common: Remove coherency workaround for AM65x

We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.

Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>