Tegra: memctrl_v2: platform handler for TZDRAM settings
The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.
Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index e120314..0567aa9 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -26,6 +26,16 @@
static uint64_t video_mem_size_mb;
/*
+ * The following platform setup functions are weakly defined. They
+ * provide typical implementations that will be overridden by a SoC.
+ */
+#pragma weak plat_memctrl_tzdram_setup
+void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
+{
+ ; /* do nothing */
+}
+
+/*
* Init Memory controller during boot.
*/
void tegra_memctrl_setup(void)
@@ -144,8 +154,6 @@
*/
void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
{
- uint32_t val;
-
/*
* Setup the Memory controller to allow only secure accesses to
* the TZDRAM carveout
@@ -157,21 +165,9 @@
tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
/*
- * When TZ encryption enabled,
- * We need setup TZDRAM before CPU to access TZ Carveout,
- * otherwise CPU will fetch non-decrypted data.
- * So save TZDRAM setting for restore by SC7 resume FW.
- * Scratch registers map:
- * RSV55_0 = CFG1[12:0] | CFG0[31:20]
- * RSV55_1 = CFG3[1:0]
+ * Perform platform specific steps.
*/
-
- val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK;
- val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK;
- mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, val);
-
- val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
- mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, val);
+ plat_memctrl_tzdram_setup(phys_base, size_in_bytes);
/*
* MCE propagates the security configuration values across the
diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index 22f05f4..f5b0ed4 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -165,6 +165,14 @@
******************************************************************************/
tegra_mc_settings_t *tegra_get_mc_settings(void);
-#endif /* __ASSMEBLY__ */
+/*******************************************************************************
+ * Handler to program the scratch registers with TZDRAM settings for the
+ * resume firmware.
+ *
+ * Implemented by SoCs under tegra/soc/txxx
+ ******************************************************************************/
+void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes);
+
+#endif /* __ASSEMBLY__ */
#endif /* MEMCTRL_V2_H */
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
index 74811ae..a2a8155 100644
--- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -537,3 +537,32 @@
{
return &tegra186_mc_settings;
}
+
+/*******************************************************************************
+ * Handler to program the scratch registers with TZDRAM settings for the
+ * resume firmware
+ ******************************************************************************/
+void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
+{
+ uint32_t val;
+
+ (void)phys_base;
+ (void)size_in_bytes;
+
+ /*
+ * When TZ encryption is enabled, we need to setup TZDRAM
+ * before CPU accesses TZ Carveout, else CPU will fetch
+ * non-decrypted data. So save TZDRAM setting for SC7 resume
+ * FW to restore.
+ *
+ * Scratch registers map:
+ * RSV55_0 = CFG1[12:0] | CFG0[31:20]
+ * RSV55_1 = CFG3[1:0]
+ */
+ val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK;
+ val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK;
+ mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, val);
+
+ val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
+ mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, val);
+}