diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
index 13a6a9b..b0d0427 100644
--- a/plat/allwinner/sun50i_a64/sunxi_power.c
+++ b/plat/allwinner/sun50i_a64/sunxi_power.c
@@ -232,7 +232,7 @@
 	/* locate the PMIC DT node, bail out if not found */
 	node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803");
 	if (node < 0) {
-		WARN("BL31: PMIC: Cannot find AXP803 DT node, skipping initial setup.\n");
+		WARN("PMIC: No PMIC DT node, skipping setup\n");
 		return;
 	}
 
@@ -245,7 +245,7 @@
 	/* descend into the "regulators" subnode */
 	node = fdt_subnode_offset(fdt, node, "regulators");
 	if (node < 0) {
-		WARN("BL31: PMIC: Cannot find regulators subnode, skipping initial setup.\n");
+		WARN("PMIC: No regulators DT node, skipping setup\n");
 		return;
 	}
 
@@ -275,6 +275,7 @@
 			continue;
 		}
 	}
+
 	/*
 	 * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts
 	 * down. So always enable DC1SW as the very last regulator.
@@ -291,11 +292,16 @@
 
 	switch (socid) {
 	case SUNXI_SOC_H5:
+		NOTICE("PMIC: Assuming H5 reference regulator design\n");
+
 		pmic = REF_DESIGN_H5;
-		NOTICE("BL31: PMIC: Defaulting to PortL GPIO according to H5 reference design.\n");
+
 		break;
 	case SUNXI_SOC_A64:
 		pmic = GENERIC_A64;
+
+		INFO("PMIC: Probing AXP803 on RSB\n");
+
 		ret = sunxi_init_platform_r_twi(socid, true);
 		if (ret)
 			return ret;
@@ -305,14 +311,12 @@
 			return ret;
 
 		pmic = AXP803_RSB;
-		NOTICE("BL31: PMIC: Detected AXP803 on RSB.\n");
 
 		if (fdt)
 			setup_axp803_rails(fdt);
 
 		break;
 	default:
-		NOTICE("BL31: PMIC: No support for Allwinner %x SoC.\n", socid);
 		return -ENODEV;
 	}
 	return 0;