Merge changes from topic "qemu_sbsa" into integration
* changes:
plat/qemu: add gicv3 support for qemu
plat/qemu: move gicv2 codes to separate file
diff --git a/Makefile b/Makefile
index aca57b6..43ff8d2 100644
--- a/Makefile
+++ b/Makefile
@@ -273,8 +273,7 @@
CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \
-Wmissing-include-dirs $(ERRORS) $(WARNINGS)
ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \
- -D__ASSEMBLY__ -ffreestanding \
- -Wa,--fatal-warnings
+ -ffreestanding -Wa,--fatal-warnings
TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \
-ffreestanding -fno-builtin -Wall -std=gnu99 \
-Os -ffunction-sections -fdata-sections
@@ -735,12 +734,6 @@
$(eval $(call add_define,PRELOADED_BL33_BASE))
endif
endif
-# Define the AARCH32/AARCH64 flag based on the ARCH flag
-ifeq (${ARCH},aarch32)
- $(eval $(call add_define,AARCH32))
-else
- $(eval $(call add_define,AARCH64))
-endif
# Define the DYN_DISABLE_AUTH flag only if set.
ifeq (${DYN_DISABLE_AUTH},1)
@@ -763,14 +756,22 @@
msg_start:
@echo "Building ${PLAT}"
-# Check if deprecated declarations and cpp warnings should be treated as error or not.
ifeq (${ERROR_DEPRECATED},0)
+# Check if deprecated declarations and cpp warnings should be treated as error or not.
ifneq ($(findstring clang,$(notdir $(CC))),)
CPPFLAGS += -Wno-error=deprecated-declarations
else
CPPFLAGS += -Wno-error=deprecated-declarations -Wno-error=cpp
endif
+# __ASSEMBLY__ is deprecated in favor of the compiler-builtin __ASSEMBLER__.
+ASFLAGS += -D__ASSEMBLY__
+# AARCH32/AARCH64 macros are deprecated in favor of the compiler-builtin __aarch64__.
+ifeq (${ARCH},aarch32)
+ $(eval $(call add_define,AARCH32))
+else
+ $(eval $(call add_define,AARCH64))
endif
+endif # !ERROR_DEPRECATED
$(eval $(call MAKE_LIB_DIRS))
$(eval $(call MAKE_LIB,c))
diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c
index 76a4375..d222b9c 100644
--- a/bl1/bl1_fwu.c
+++ b/bl1/bl1_fwu.c
@@ -520,7 +520,7 @@
INFO("BL1-FWU: Executing Secure image\n");
-#ifdef AARCH64
+#ifdef __aarch64__
/* Save NS-EL1 system registers. */
cm_el1_sysregs_context_save(NON_SECURE);
#endif
@@ -531,7 +531,7 @@
/* Update the secure image id. */
sec_exec_image_id = image_id;
-#ifdef AARCH64
+#ifdef __aarch64__
*handle = cm_get_context(SECURE);
#else
*handle = smc_get_ctx(SECURE);
@@ -584,7 +584,7 @@
INFO("BL1-FWU: Resuming %s world context\n",
(resume_sec_state == SECURE) ? "secure" : "normal");
-#ifdef AARCH64
+#ifdef __aarch64__
/* Save the EL1 system registers of calling world. */
cm_el1_sysregs_context_save(caller_sec_state);
@@ -641,7 +641,7 @@
sec_exec_image_id = INVALID_IMAGE_ID;
INFO("BL1-FWU: Resuming Normal world context\n");
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* Secure world is done so no need to save the context.
* Just restore the Non-Secure context.
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index fce14f5..d44b46d 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -59,7 +59,7 @@
/* Perform early platform-specific setup */
bl1_early_platform_setup();
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* Update pointer authentication key before the MMU is enabled. It is
* saved in the rodata section, that can be writen before enabling the
@@ -67,7 +67,7 @@
* in the early platform setup.
*/
bl_handle_pauth();
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
/* Perform late platform-specific setup */
bl1_plat_arch_setup();
@@ -97,10 +97,10 @@
/*
* Ensure that MMU/Caches and coherency are turned on
*/
-#ifdef AARCH32
- val = read_sctlr();
-#else
+#ifdef __aarch64__
val = read_sctlr_el3();
+#else
+ val = read_sctlr();
#endif
assert(val & SCTLR_M_BIT);
assert(val & SCTLR_C_BIT);
@@ -198,11 +198,11 @@
******************************************************************************/
void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
{
-#ifdef AARCH32
- NOTICE("BL1: Booting BL32\n");
-#else
+#ifdef __aarch64__
NOTICE("BL1: Booting BL31\n");
-#endif /* AARCH32 */
+#else
+ NOTICE("BL1: Booting BL32\n");
+#endif /* __aarch64__ */
print_entry_point_info(bl_ep_info);
}
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index 7d8d60c..79b0e71 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -15,10 +15,10 @@
#include "bl2_private.h"
-#ifdef AARCH32
-#define NEXT_IMAGE "BL32"
-#else
+#ifdef __aarch64__
#define NEXT_IMAGE "BL31"
+#else
+#define NEXT_IMAGE "BL32"
#endif
#if !BL2_AT_EL3
@@ -31,7 +31,7 @@
/* Perform early platform-specific setup */
bl2_early_platform_setup2(arg0, arg1, arg2, arg3);
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* Update pointer authentication key before the MMU is enabled. It is
* saved in the rodata section, that can be writen before enabling the
@@ -39,7 +39,7 @@
* in the early platform setup.
*/
bl_handle_pauth();
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
/* Perform late platform-specific setup */
bl2_plat_arch_setup();
@@ -55,7 +55,7 @@
/* Perform early platform-specific setup */
bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3);
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* Update pointer authentication key before the MMU is enabled. It is
* saved in the rodata section, that can be writen before enabling the
@@ -63,7 +63,7 @@
* in the early platform setup.
*/
bl_handle_pauth();
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
/* Perform late platform-specific setup */
bl2_el3_plat_arch_setup();
@@ -97,14 +97,14 @@
next_bl_ep_info = bl2_load_images();
#if !BL2_AT_EL3
-#ifdef AARCH32
+#ifndef __aarch64__
/*
* For AArch32 state BL1 and BL2 share the MMU setup.
* Given that BL2 does not map BL1 regions, MMU needs
* to be disabled in order to go back to BL1.
*/
disable_mmu_icache_secure();
-#endif /* AARCH32 */
+#endif /* !__aarch64__ */
console_flush();
diff --git a/bl2u/bl2u_main.c b/bl2u/bl2u_main.c
index d3c83cc..d49c9ce 100644
--- a/bl2u/bl2u_main.c
+++ b/bl2u/bl2u_main.c
@@ -45,14 +45,14 @@
console_flush();
-#ifdef AARCH32
+#ifndef __aarch64__
/*
* For AArch32 state BL1 and BL2U share the MMU setup.
* Given that BL2U does not map BL1 regions, MMU needs
* to be disabled in order to go back to BL1.
*/
disable_mmu_icache_secure();
-#endif /* AARCH32 */
+#endif /* !__aarch64__ */
/*
* Indicate that BL2U is done and resume back to
diff --git a/bl32/tsp/tsp_private.h b/bl32/tsp/tsp_private.h
index e39f291..cbd527f 100644
--- a/bl32/tsp/tsp_private.h
+++ b/bl32/tsp/tsp_private.h
@@ -20,7 +20,7 @@
#define TSP_ARGS_END 0x40
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -148,6 +148,6 @@
uint64_t arg7);
uint64_t tsp_main(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TSP_PRIVATE_H */
diff --git a/common/backtrace/backtrace.c b/common/backtrace/backtrace.c
index 53f8b07..506d4a4 100644
--- a/common/backtrace/backtrace.c
+++ b/common/backtrace/backtrace.c
@@ -93,7 +93,7 @@
* Returns true if the address points to a virtual address that can be read at
* the current EL, false otherwise.
*/
-#ifdef AARCH64
+#ifdef __aarch64__
static bool is_address_readable(uintptr_t addr)
{
unsigned int el = get_current_el();
@@ -123,7 +123,7 @@
return true;
}
-#else /* if AARCH32 */
+#else /* !__aarch64__ */
static bool is_address_readable(uintptr_t addr)
{
unsigned int el = get_current_el();
@@ -144,7 +144,7 @@
return true;
}
-#endif
+#endif /* __aarch64__ */
/*
* Returns true if all the bytes in a given object are in mapped memory and an
@@ -207,7 +207,7 @@
*/
static struct frame_record *adjust_frame_record(struct frame_record *fr)
{
-#ifdef AARCH64
+#ifdef __aarch64__
return fr;
#else
return (struct frame_record *)((uintptr_t)fr - 4U);
diff --git a/common/bl_common.c b/common/bl_common.c
index 61f031b..a09cd71 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -236,7 +236,7 @@
PRINT_IMAGE_ARG(1);
PRINT_IMAGE_ARG(2);
PRINT_IMAGE_ARG(3);
-#ifndef AARCH32
+#ifdef __aarch64__
PRINT_IMAGE_ARG(4);
PRINT_IMAGE_ARG(5);
PRINT_IMAGE_ARG(6);
@@ -245,7 +245,7 @@
#undef PRINT_IMAGE_ARG
}
-#ifdef AARCH64
+#ifdef __aarch64__
/*******************************************************************************
* Handle all possible cases regarding ARMv8.3-PAuth.
******************************************************************************/
@@ -293,4 +293,4 @@
#endif /* ENABLE_PAUTH */
}
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index 858996c..b447f14 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -50,12 +50,13 @@
TF-A has been tested with Linaro Release 18.04.
-Download and install the AArch32 or AArch64 little-endian GCC cross compiler. If
-you would like to use the latest features available, download GCC 8.2-2019.01
-compiler from `arm Developer page`_. Otherwise, the `Linaro Release Notes`_
-documents which version of the compiler to use for a given Linaro Release. Also,
-these `Linaro instructions`_ provide further guidance and a script, which can be
-used to download Linaro deliverables automatically.
+Download and install the AArch32 (arm-eabi) or AArch64 little-endian
+(aarch64-linux-gnu) GCC cross compiler. If you would like to use the latest
+features available, download GCC 8.3-2019.03 compiler from
+`arm Developer page`_. Otherwise, the `Linaro Release Notes`_ documents which
+version of the compiler to use for a given Linaro Release. Also, these
+`Linaro instructions`_ provide further guidance and a script, which can be used
+to download Linaro deliverables automatically.
Optionally, TF-A can be built using clang version 4.0 or newer or Arm
Compiler 6. See instructions below on how to switch the default compiler.
@@ -138,7 +139,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
+ export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
It is possible to build TF-A using Clang or Arm Compiler 6. To do so
``CC`` needs to point to the clang or armclang binary, which will
diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c
index d184054..d0c5abc 100644
--- a/drivers/arm/ccn/ccn.c
+++ b/drivers/arm/ccn/ccn.c
@@ -17,7 +17,7 @@
#include "ccn_private.h"
static const ccn_desc_t *ccn_plat_desc;
-#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
+#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
DEFINE_BAKERY_LOCK(ccn_lock);
#endif
@@ -264,7 +264,7 @@
assert(ccn_plat_desc);
assert(ccn_plat_desc->periphbase);
-#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
+#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
bakery_lock_get(&ccn_lock);
#endif
start_region_id = region_id;
@@ -284,7 +284,7 @@
rn_id_map);
}
-#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
+#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
bakery_lock_release(&ccn_lock);
#endif
}
diff --git a/drivers/arm/css/sds/sds_private.h b/drivers/arm/css/sds/sds_private.h
index 2101dd0..d801a04 100644
--- a/drivers/arm/css/sds/sds_private.h
+++ b/drivers/arm/css/sds/sds_private.h
@@ -58,7 +58,7 @@
#define SDS_REGION_REGIONSIZE_OFFSET 0x4
#define SDS_REGION_DESC_SIZE 0x8
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
@@ -95,6 +95,6 @@
& SDS_REGION_SCH_VERSION_MASK)
#define GET_SDS_REGION_SIZE(region) ((((region_desc_t *)(region))->reg[1]))
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SDS_PRIVATE_H */
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index a94dbf6..94a20ba 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -73,12 +73,12 @@
plat_driver_data->interrupt_props != NULL : 1);
/* Check for system register support */
-#ifdef AARCH32
- assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
-#else
+#ifdef __aarch64__
assert((read_id_aa64pfr0_el1() &
(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
-#endif /* AARCH32 */
+#else
+ assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
+#endif /* __aarch64__ */
/* The GIC version should be 3.0 */
gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index 92066e1..327a9a1 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -40,16 +40,16 @@
* Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
* are zeroes.
*/
-#ifdef AARCH32
+#ifdef __aarch64__
static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
{
- return (((typer_val) >> 32) & U(0xffffff));
+ return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) |
+ ((typer_val >> 32) & U(0xffffff));
}
#else
static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
{
- return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) |
- ((typer_val >> 32) & U(0xffffff));
+ return (((typer_val) >> 32) & U(0xffffff));
}
#endif
diff --git a/drivers/imx/uart/imx_uart.h b/drivers/imx/uart/imx_uart.h
index b71504c..4f6d3de 100644
--- a/drivers/imx/uart/imx_uart.h
+++ b/drivers/imx/uart/imx_uart.h
@@ -152,7 +152,7 @@
#define IMX_UART_TS_RXFULL BIT(3)
#define IMX_UART_TS_SOFTRST BIT(0)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
typedef struct {
console_t console;
@@ -163,6 +163,6 @@
uint32_t clock,
uint32_t baud,
console_imx_uart_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* IMX_UART_H */
diff --git a/drivers/renesas/rcar/delay/micro_delay.h b/drivers/renesas/rcar/delay/micro_delay.h
index 193daba..37b71f8 100644
--- a/drivers/renesas/rcar/delay/micro_delay.h
+++ b/drivers/renesas/rcar/delay/micro_delay.h
@@ -7,7 +7,7 @@
#ifndef MICRO_DELAY_H
#define MICRO_DELAY_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
void rcar_micro_delay(uint64_t micro_sec);
#endif
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
index f4c9d3a..32e04a7 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -148,7 +148,7 @@
#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
diff --git a/drivers/renesas/rcar/pwrc/pwrc.h b/drivers/renesas/rcar/pwrc/pwrc.h
index e67c6ef..2b81783 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.h
+++ b/drivers/renesas/rcar/pwrc/pwrc.h
@@ -38,7 +38,7 @@
#define RCAR_CLUSTER_CA53 (1U)
#define RCAR_CLUSTER_CA57 (2U)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr);
void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr);
void rcar_pwrc_clusteroff(uint64_t mpidr);
diff --git a/include/arch/aarch32/smccc_helpers.h b/include/arch/aarch32/smccc_helpers.h
index d3e5e59..b2ee3cf 100644
--- a/include/arch/aarch32/smccc_helpers.h
+++ b/include/arch/aarch32/smccc_helpers.h
@@ -24,7 +24,7 @@
#define SMC_CTX_PMCR U(0x88)
#define SMC_CTX_SIZE U(0x90)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -156,6 +156,6 @@
/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */
void *smc_get_next_ctx(void);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* SMCCC_HELPERS_H */
diff --git a/include/arch/aarch64/smccc_helpers.h b/include/arch/aarch64/smccc_helpers.h
index e28697d..fac6fd9 100644
--- a/include/arch/aarch64/smccc_helpers.h
+++ b/include/arch/aarch64/smccc_helpers.h
@@ -9,7 +9,7 @@
#include <lib/smccc.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdbool.h>
@@ -82,6 +82,6 @@
_x4 = read_ctx_reg(regs, CTX_GPREG_X4); \
} while (false)
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* SMCCC_HELPERS_H */
diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h
index 937b8c7..d81f434 100644
--- a/include/bl1/bl1.h
+++ b/include/bl1/bl1.h
@@ -61,7 +61,7 @@
#define is_fwu_fid(_fid) \
((_fid >= FWU_SMC_FID_START) && (_fid <= FWU_SMC_FID_END))
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <lib/cassert.h>
@@ -98,5 +98,5 @@
void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
meminfo_t *bl2_mem_layout);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* BL1_H */
diff --git a/include/bl31/ehf.h b/include/bl31/ehf.h
index ee00d09..c13d28c 100644
--- a/include/bl31/ehf.h
+++ b/include/bl31/ehf.h
@@ -7,7 +7,7 @@
#ifndef EHF_H
#define EHF_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdint.h>
@@ -87,6 +87,6 @@
void ehf_allow_ns_preemption(uint64_t preempt_ret_code);
unsigned int ehf_is_ns_preemption_allowed(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* EHF_H */
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index b1683cc..8bb1bab 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h
@@ -79,7 +79,7 @@
#define get_interrupt_src_ss(flag) (((flag) >> INTR_SRC_SS_FLAG_SHIFT) & \
INTR_SRC_SS_FLAG_MASK)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <errno.h>
#include <stdint.h>
@@ -143,5 +143,5 @@
int disable_intr_rm_local(uint32_t type, uint32_t security_state);
int enable_intr_rm_local(uint32_t type, uint32_t security_state);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* INTERRUPT_MGMT_H */
diff --git a/include/bl32/tsp/tsp.h b/include/bl32/tsp/tsp.h
index 18d3079..637e14a 100644
--- a/include/bl32/tsp/tsp.h
+++ b/include/bl32/tsp/tsp.h
@@ -84,7 +84,7 @@
#define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -106,6 +106,6 @@
void tsp_setup(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TSP_H */
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index eb96df0..896a03f 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -11,11 +11,11 @@
#include <common/param_header.h>
#include <lib/utils_def.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
#include <lib/cassert.h>
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#include <export/common/bl_common_exp.h>
@@ -91,7 +91,7 @@
#define __TEXT_END__ Load$$__TEXT_EPILOGUE__$$Base
#endif /* USE_ARM_LINK */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/*
* Declarations of linker defined symbols to help determine memory layout of
@@ -178,6 +178,6 @@
void bl_handle_pauth(void);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* BL_COMMON_H */
diff --git a/include/common/debug.h b/include/common/debug.h
index f8faf68..245e698 100644
--- a/include/common/debug.h
+++ b/include/common/debug.h
@@ -27,7 +27,7 @@
#define LOG_LEVEL_INFO U(40)
#define LOG_LEVEL_VERBOSE U(50)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdarg.h>
@@ -110,5 +110,5 @@
void tf_log(const char *fmt, ...) __printflike(1, 2);
void tf_log_set_max_level(unsigned int log_level);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* DEBUG_H */
diff --git a/include/common/ep_info.h b/include/common/ep_info.h
index 6cb903e..4bfa1fa 100644
--- a/include/common/ep_info.h
+++ b/include/common/ep_info.h
@@ -9,10 +9,10 @@
#include <common/param_header.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
#include <lib/cassert.h>
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#include <export/common/ep_info_exp.h>
@@ -30,7 +30,7 @@
#define SET_SECURITY_STATE(x, security) \
((x) = ((x) & ~EP_SECURITY_MASK) | (security))
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/*
* Compile time assertions related to the 'entry_point_info' structure to
@@ -41,7 +41,7 @@
__builtin_offsetof(entry_point_info_t, pc), \
assert_BL31_pc_offset_mismatch);
-#ifdef AARCH32
+#ifndef __aarch64__
CASSERT(ENTRY_POINT_INFO_LR_SVC_OFFSET ==
__builtin_offsetof(entry_point_info_t, lr_svc),
assert_entrypoint_lr_offset_error);
@@ -56,6 +56,6 @@
__builtin_offsetof(entry_point_info_t, pc), \
assert_entrypoint_and_spsr_should_be_adjacent);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* EP_INFO_H */
diff --git a/include/common/interrupt_props.h b/include/common/interrupt_props.h
index 6c6a853..07bafaa 100644
--- a/include/common/interrupt_props.h
+++ b/include/common/interrupt_props.h
@@ -7,7 +7,7 @@
#ifndef INTERRUPT_PROPS_H
#define INTERRUPT_PROPS_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* Create an interrupt property descriptor from various interrupt properties */
#define INTR_PROP_DESC(num, pri, grp, cfg) \
@@ -25,5 +25,5 @@
unsigned int intr_cfg:2;
} interrupt_prop_t;
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* INTERRUPT_PROPS_H */
diff --git a/include/common/param_header.h b/include/common/param_header.h
index b885286..4dab4e3 100644
--- a/include/common/param_header.h
+++ b/include/common/param_header.h
@@ -9,9 +9,9 @@
#include <stdbool.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#include <export/common/param_header_exp.h>
diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h
index e5e36c7..472a32a 100644
--- a/include/common/runtime_svc.h
+++ b/include/common/runtime_svc.h
@@ -20,15 +20,15 @@
* Constants to allow the assembler access a runtime service
* descriptor
*/
-#ifdef AARCH32
-#define RT_SVC_SIZE_LOG2 U(4)
-#define RT_SVC_DESC_INIT U(8)
-#define RT_SVC_DESC_HANDLE U(12)
-#else
+#ifdef __aarch64__
#define RT_SVC_SIZE_LOG2 U(5)
#define RT_SVC_DESC_INIT U(16)
#define RT_SVC_DESC_HANDLE U(24)
-#endif /* AARCH32 */
+#else
+#define RT_SVC_SIZE_LOG2 U(4)
+#define RT_SVC_DESC_INIT U(8)
+#define RT_SVC_DESC_HANDLE U(12)
+#endif /* __aarch64__ */
#define SIZEOF_RT_SVC_DESC (U(1) << RT_SVC_SIZE_LOG2)
@@ -39,7 +39,7 @@
*/
#define MAX_RT_SVCS U(128)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* Prototype for runtime service initializing function */
typedef int32_t (*rt_svc_init_t)(void);
@@ -134,5 +134,5 @@
extern uint8_t rt_svc_descs_indices[MAX_RT_SVCS];
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* RUNTIME_SVC_H */
diff --git a/include/drivers/arm/cci.h b/include/drivers/arm/cci.h
index c5ddcfd..5aea95a 100644
--- a/include/drivers/arm/cci.h
+++ b/include/drivers/arm/cci.h
@@ -100,7 +100,7 @@
#define SLAVE_IF_UNUSED -1
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -121,5 +121,5 @@
void cci_enable_snoop_dvm_reqs(unsigned int master_id);
void cci_disable_snoop_dvm_reqs(unsigned int master_id);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CCI_H */
diff --git a/include/drivers/arm/ccn.h b/include/drivers/arm/ccn.h
index 9c3abac..7f73768 100644
--- a/include/drivers/arm/ccn.h
+++ b/include/drivers/arm/ccn.h
@@ -46,7 +46,7 @@
*/
#define CCN_GET_RUN_STATE(pstate) (pstate & 0xf)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
/*
@@ -109,5 +109,5 @@
unsigned int node_id,
unsigned int reg_offset);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CCN_H */
diff --git a/include/drivers/arm/css/sds.h b/include/drivers/arm/css/sds.h
index 114ae92..db4cbaa 100644
--- a/include/drivers/arm/css/sds.h
+++ b/include/drivers/arm/css/sds.h
@@ -70,7 +70,7 @@
#define SDS_ERR_STRUCT_NOT_FOUND -3
#define SDS_ERR_STRUCT_NOT_FINALIZED -4
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
@@ -85,6 +85,6 @@
size_t size, sds_access_mode_t mode);
int sds_struct_write(uint32_t structure_id, unsigned int fld_off, void *data,
size_t size, sds_access_mode_t mode);
-#endif /*__ASSEMBLY__ */
+#endif /*__ASSEMBLER__ */
#endif /* SDS_H */
diff --git a/include/drivers/arm/fvp/fvp_pwrc.h b/include/drivers/arm/fvp/fvp_pwrc.h
index ca173f3..39e2516 100644
--- a/include/drivers/arm/fvp/fvp_pwrc.h
+++ b/include/drivers/arm/fvp/fvp_pwrc.h
@@ -35,7 +35,7 @@
#define PSYSR_INVALID U(0xffffffff)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -50,6 +50,6 @@
unsigned int fvp_pwrc_read_psysr(u_register_t mpidr);
unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* FVP_PWRC_H */
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index 6bc5101..ebcb216 100644
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -116,7 +116,7 @@
/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
#define INT_ID_MASK U(0x3ff)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdint.h>
@@ -184,5 +184,5 @@
unsigned int gicv2_set_pmr(unsigned int mask);
void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* GICV2_H */
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index 72221ac..9c72d4d 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -208,7 +208,7 @@
#define GITS_CTLR_QUIESCENT_SHIFT 31
#define GITS_CTLR_QUIESCENT_BIT BIT_32(GITS_CTLR_QUIESCENT_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdbool.h>
#include <stdint.h>
@@ -406,5 +406,5 @@
void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num);
unsigned int gicv3_set_pmr(unsigned int mask);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* GICV3_H */
diff --git a/include/drivers/arm/pl011.h b/include/drivers/arm/pl011.h
index f201f00..8733d19 100644
--- a/include/drivers/arm/pl011.h
+++ b/include/drivers/arm/pl011.h
@@ -83,7 +83,7 @@
#define CONSOLE_T_PL011_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -101,6 +101,6 @@
int console_pl011_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_pl011_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* PL011_H */
diff --git a/include/drivers/arm/sp805.h b/include/drivers/arm/sp805.h
index 551bfe4..b00ede1 100644
--- a/include/drivers/arm/sp805.h
+++ b/include/drivers/arm/sp805.h
@@ -21,7 +21,7 @@
#define SP805_CTR_RESEN (U(1) << 1)
#define SP805_CTR_INTEN (U(1) << 0)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -31,6 +31,6 @@
void sp805_stop(uintptr_t base);
void sp805_refresh(uintptr_t base, unsigned int ticks);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SP805_H */
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index 98ef0ec..32aeb03 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -93,7 +93,7 @@
#define TZC_400_REGION_SIZE U(0x20)
#define TZC_400_ACTION_OFF U(0x4)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdint.h>
@@ -154,6 +154,6 @@
tzc400_disable_filters();
}
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TZC400_H */
diff --git a/include/drivers/arm/tzc_dmc500.h b/include/drivers/arm/tzc_dmc500.h
index 24bfaeb..cce074c 100644
--- a/include/drivers/arm/tzc_dmc500.h
+++ b/include/drivers/arm/tzc_dmc500.h
@@ -121,7 +121,7 @@
/* Length of registers for configuring each region */
#define TZC_DMC500_REGION_SIZE U(0x018)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -147,5 +147,5 @@
int tzc_dmc500_verify_complete(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TZC_DMC500_H */
diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h
index d143d73..acfde26 100644
--- a/include/drivers/auth/mbedtls/mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/mbedtls_config.h
@@ -86,7 +86,7 @@
/* Memory buffer allocator options */
#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* System headers required to build mbed TLS with the current configuration */
#include <stdlib.h>
#include "mbedtls/check_config.h"
diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h
index 0a1cf77..64a062c 100644
--- a/include/drivers/cadence/cdns_uart.h
+++ b/include/drivers/cadence/cdns_uart.h
@@ -27,7 +27,7 @@
#define CONSOLE_T_CDNS_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -45,6 +45,6 @@
int console_cdns_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_cdns_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* CDNS_UART_H */
diff --git a/include/drivers/console.h b/include/drivers/console.h
index f31de95..cada771 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -28,7 +28,7 @@
/* Returned by console_xxx() if no registered console implements xxx. */
#define ERROR_NO_VALID_CONSOLE (-128)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -75,6 +75,6 @@
/* Flush all consoles registered for the current state. */
int console_flush(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CONSOLE_H */
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
index 1aa4c88..85babb8 100644
--- a/include/drivers/marvell/cache_llc.h
+++ b/include/drivers/marvell/cache_llc.h
@@ -27,7 +27,7 @@
#define LLC_EXCLUSIVE_EN 0x100
#define LLC_WAY_MASK 0xFFFFFFFF
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void llc_cache_sync(int ap_index);
void llc_flush_all(int ap_index);
void llc_clean_all(int ap_index);
diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h
index 546d9f1..b0d1ec9 100644
--- a/include/drivers/marvell/ccu.h
+++ b/include/drivers/marvell/ccu.h
@@ -10,7 +10,7 @@
#ifndef CCU_H
#define CCU_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <drivers/marvell/addr_map.h>
#endif
@@ -36,7 +36,7 @@
#define CCU_SRAM_WIN_CR CCU_WIN_CR_OFFSET(MVEBU_AP0, 1)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
int init_ccu(int);
void ccu_win_check(struct addr_map_win *win);
void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
diff --git a/include/drivers/marvell/uart/a3700_console.h b/include/drivers/marvell/uart/a3700_console.h
index 5511d96..517f01a 100644
--- a/include/drivers/marvell/uart/a3700_console.h
+++ b/include/drivers/marvell/uart/a3700_console.h
@@ -56,7 +56,7 @@
#define CONSOLE_T_A3700_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -74,6 +74,6 @@
int console_a3700_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_a3700_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* A3700_CONSOLE_H */
diff --git a/include/drivers/meson/meson_console.h b/include/drivers/meson/meson_console.h
index 5da1e3f..70e3b0b 100644
--- a/include/drivers/meson/meson_console.h
+++ b/include/drivers/meson/meson_console.h
@@ -11,7 +11,7 @@
#define CONSOLE_T_MESON_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -32,6 +32,6 @@
int console_meson_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_meson_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* MESON_CONSOLE_H */
diff --git a/include/drivers/renesas/rcar/console/console.h b/include/drivers/renesas/rcar/console/console.h
index 5bc10b7..0e4ed8f 100644
--- a/include/drivers/renesas/rcar/console/console.h
+++ b/include/drivers/renesas/rcar/console/console.h
@@ -9,7 +9,7 @@
#define CONSOLE_T_RCAR_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -27,6 +27,6 @@
int console_rcar_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_rcar_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* RCAR_PRINTF_H */
diff --git a/include/drivers/st/stm32_console.h b/include/drivers/st/stm32_console.h
index b303768..a2ad87c 100644
--- a/include/drivers/st/stm32_console.h
+++ b/include/drivers/st/stm32_console.h
@@ -11,7 +11,7 @@
#define CONSOLE_T_STM32_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -29,6 +29,6 @@
int console_stm32_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
struct console_stm32 *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* STM32_CONSOLE_H */
diff --git a/include/drivers/st/stm32_gpio.h b/include/drivers/st/stm32_gpio.h
index 4320eaf..e241f58 100644
--- a/include/drivers/st/stm32_gpio.h
+++ b/include/drivers/st/stm32_gpio.h
@@ -45,13 +45,13 @@
#define GPIO_PULL_DOWN 0x02
#define GPIO_PULL_MASK U(0x03)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int dt_set_pinctrl_config(int node);
void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
uint32_t pull, uint32_t alternate, uint8_t status);
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* STM32_GPIO_H */
diff --git a/include/drivers/ti/uart/uart_16550.h b/include/drivers/ti/uart/uart_16550.h
index 92b1ea8..32e38f0 100644
--- a/include/drivers/ti/uart/uart_16550.h
+++ b/include/drivers/ti/uart/uart_16550.h
@@ -73,7 +73,7 @@
#define CONSOLE_T_16550_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -91,6 +91,6 @@
int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_16550_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* UART_16550_H */
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
index a2f540c..1fece01 100644
--- a/include/lib/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -11,7 +11,7 @@
#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdbool.h>
#include <stdint.h>
@@ -101,5 +101,5 @@
#define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* BAKERY_LOCK_H */
diff --git a/include/lib/cpus/aarch32/cortex_a9.h b/include/lib/cpus/aarch32/cortex_a9.h
index 1fb0a92..a8c978a 100644
--- a/include/lib/cpus/aarch32/cortex_a9.h
+++ b/include/lib/cpus/aarch32/cortex_a9.h
@@ -25,7 +25,7 @@
******************************************************************************/
#define PCR p15, 0, c15, c0, 0
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <arch_helpers.h>
DEFINE_COPROCR_RW_FUNCS(pcr, PCR)
#endif
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index 204bfdd..e5ca1ba 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -41,7 +41,7 @@
#define CORTEX_A75_AMU_GROUP0_MASK U(0x7)
#define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
uint64_t cortex_a75_amu_cnt_read(int idx);
@@ -50,6 +50,6 @@
unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CORTEX_A75_H */
diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_hercules.h
index 86e8af0..b943e7a 100644
--- a/include/lib/cpus/aarch64/cortex_hercules.h
+++ b/include/lib/cpus/aarch64/cortex_hercules.h
@@ -22,4 +22,20 @@
#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
+
+/*******************************************************************************
+ * CPU Activity Monitor Unit register specific definitions.
+ ******************************************************************************/
+#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
+#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
+#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
+#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
+
+#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF)
+#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7)
+
#endif /* CORTEX_HERCULES_H */
diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h
index 921abdb..463f890 100644
--- a/include/lib/cpus/aarch64/cpuamu.h
+++ b/include/lib/cpus/aarch64/cpuamu.h
@@ -29,7 +29,7 @@
#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3
#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
uint64_t cpuamu_cnt_read(unsigned int idx);
@@ -43,6 +43,6 @@
void cpuamu_context_save(unsigned int nr_counters);
void cpuamu_context_restore(unsigned int nr_counters);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CPUAMU_H */
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index 81c076a..02657a0 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -34,11 +34,11 @@
#define DENVER_CPU_PMSTATE_C7 U(0x7)
#define DENVER_CPU_PMSTATE_MASK U(0xF)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* Disable Dynamic Code Optimisation */
void denver_disable_dco(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* DENVER_H */
diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h
index 17b2c30..7cac77e 100644
--- a/include/lib/cpus/errata_report.h
+++ b/include/lib/cpus/errata_report.h
@@ -7,7 +7,7 @@
#ifndef ERRATA_REPORT_H
#define ERRATA_REPORT_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <arch.h>
#include <arch_helpers.h>
@@ -23,7 +23,7 @@
void errata_print_msg(unsigned int status, const char *cpu, const char *id);
int errata_needs_reporting(spinlock_t *lock, uint32_t *reported);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/* Errata status */
#define ERRATA_NOT_APPLIES 0
diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h
index 86ff53a..c5567c9 100644
--- a/include/lib/el3_runtime/aarch32/context.h
+++ b/include/lib/el3_runtime/aarch32/context.h
@@ -24,7 +24,7 @@
#define CTX_NS_SCTLR U(0x1C)
#define CTX_REGS_END U(0x20)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -65,6 +65,6 @@
CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx), \
assert_core_context_regs_offset_mismatch);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CONTEXT_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 5bd0de4..a76a59b 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -207,7 +207,7 @@
#define CTX_PAUTH_REGS_END U(0)
#endif /* CTX_INCLUDE_PAUTH_REGS */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -384,6 +384,6 @@
void fpregs_context_restore(fp_regs_t *regs);
#endif
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CONTEXT_H */
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index f23f9cd..7c996d1 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -35,7 +35,7 @@
void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep);
void cm_prepare_el3_exit(uint32_t security_state);
-#ifndef AARCH32
+#ifdef __aarch64__
void cm_el1_sysregs_context_save(uint32_t security_state);
void cm_el1_sysregs_context_restore(uint32_t security_state);
void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint);
@@ -78,6 +78,6 @@
#else
void *cm_get_next_context(void);
void cm_set_next_context(void *context);
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
#endif /* CONTEXT_MGMT_H */
diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index 9e1d7f1..55db4cf 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h
@@ -11,15 +11,7 @@
#include <bl31/ehf.h>
-#ifdef AARCH32
-
-#if CRASH_REPORTING
-#error "Crash reporting is not supported in AArch32"
-#endif
-#define CPU_DATA_CPU_OPS_PTR 0x0
-#define CPU_DATA_CRASH_BUF_OFFSET 0x4
-
-#else /* AARCH32 */
+#ifdef __aarch64__
/* Offsets for the cpu_data structure */
#define CPU_DATA_CRASH_BUF_OFFSET 0x18
@@ -27,9 +19,17 @@
#define CPU_DATA_CRASH_BUF_SIZE 64
#define CPU_DATA_CPU_OPS_PTR 0x10
-#endif /* AARCH32 */
+#else /* __aarch64__ */
#if CRASH_REPORTING
+#error "Crash reporting is not supported in AArch32"
+#endif
+#define CPU_DATA_CPU_OPS_PTR 0x0
+#define CPU_DATA_CRASH_BUF_OFFSET 0x4
+
+#endif /* __aarch64__ */
+
+#if CRASH_REPORTING
#define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \
CPU_DATA_CRASH_BUF_SIZE)
#else
@@ -49,7 +49,7 @@
#define CPU_DATA_PMF_TS0_IDX 0
#endif
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <arch_helpers.h>
#include <lib/cassert.h>
@@ -84,7 +84,7 @@
* used for this.
******************************************************************************/
typedef struct cpu_data {
-#ifndef AARCH32
+#ifdef __aarch64__
void *cpu_context[2];
#endif
uintptr_t cpu_ops_ptr;
@@ -127,7 +127,7 @@
struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
-#ifndef AARCH32
+#ifdef __aarch64__
/* Return the cpu_data structure for the current CPU. */
static inline struct cpu_data *_cpu_data(void)
{
@@ -161,5 +161,5 @@
sizeof(((cpu_data_t *)0)->_m))
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CPU_DATA_H */
diff --git a/include/lib/el3_runtime/pubsub_events.h b/include/lib/el3_runtime/pubsub_events.h
index 8e4a87a..5012082 100644
--- a/include/lib/el3_runtime/pubsub_events.h
+++ b/include/lib/el3_runtime/pubsub_events.h
@@ -24,7 +24,7 @@
REGISTER_PUBSUB_EVENT(psci_suspend_pwrdown_start);
REGISTER_PUBSUB_EVENT(psci_suspend_pwrdown_finish);
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* These events are published by the AArch64 context management framework
* after the secure context is restored/saved via
@@ -40,4 +40,4 @@
*/
REGISTER_PUBSUB_EVENT(cm_entering_normal_world);
REGISTER_PUBSUB_EVENT(cm_exited_normal_world);
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h
index 98daab6..4fc8f04 100644
--- a/include/lib/extensions/ras.h
+++ b/include/lib/extensions/ras.h
@@ -68,7 +68,7 @@
.num_intrs = ARRAY_SIZE(_array), \
}
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <assert.h>
@@ -196,6 +196,6 @@
void *handle, uint64_t flags);
void ras_init(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* RAS_H */
diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h
index e9375a3..0c98c4a 100644
--- a/include/lib/extensions/ras_arch.h
+++ b/include/lib/extensions/ras_arch.h
@@ -178,7 +178,7 @@
/* I/DFSC code for synchronous external abort */
#define SYNC_EA_FSC 0x10
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <arch.h>
#include <arch_helpers.h>
@@ -256,6 +256,6 @@
/* Library functions to probe Standard Error Record */
int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data);
int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* RAS_ARCH_H */
diff --git a/include/lib/libc/aarch64/setjmp_.h b/include/lib/libc/aarch64/setjmp_.h
index 174b3eb..f880a17 100644
--- a/include/lib/libc/aarch64/setjmp_.h
+++ b/include/lib/libc/aarch64/setjmp_.h
@@ -18,13 +18,13 @@
#define JMP_SIZE (JMP_CTX_END >> 3)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
/* Jump buffer hosting x18 - x30 and sp_el0 registers */
typedef uint64_t jmp_buf[JMP_SIZE] __aligned(16);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SETJMP__H */
diff --git a/include/lib/libc/setjmp.h b/include/lib/libc/setjmp.h
index 5661201..be8e2c0 100644
--- a/include/lib/libc/setjmp.h
+++ b/include/lib/libc/setjmp.h
@@ -9,12 +9,12 @@
#include <setjmp_.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
int setjmp(jmp_buf env);
__dead2 void longjmp(jmp_buf env, int val);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SETJMP_H */
diff --git a/include/lib/libfdt/fdt.h b/include/lib/libfdt/fdt.h
index 74961f9..ef7c86b 100644
--- a/include/lib/libfdt/fdt.h
+++ b/include/lib/libfdt/fdt.h
@@ -52,7 +52,7 @@
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct fdt_header {
fdt32_t magic; /* magic word FDT_MAGIC */
@@ -90,7 +90,7 @@
char data[0];
};
-#endif /* !__ASSEMBLY */
+#endif /* !__ASSEMBLER__ */
#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */
#define FDT_TAGSIZE sizeof(fdt32_t)
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index fe279d4..04e5e3d 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -166,7 +166,7 @@
#define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT)
#define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0))
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -348,6 +348,6 @@
void __dead2 psci_power_down_wfi(void);
void psci_arch_setup(void);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* PSCI_H */
diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h
index 53d7711..76c1a8d 100644
--- a/include/lib/psci/psci_lib.h
+++ b/include/lib/psci/psci_lib.h
@@ -9,7 +9,7 @@
#include <common/ep_info.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdint.h>
@@ -89,6 +89,6 @@
void psci_register_spd_pm_hook(const spd_pm_ops_t *pm);
void psci_prepare_next_non_secure_ctx(
entry_point_info_t *next_image_info);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* PSCI_LIB_H */
diff --git a/include/lib/runtime_instr.h b/include/lib/runtime_instr.h
index f5a3f13..303f27e 100644
--- a/include/lib/runtime_instr.h
+++ b/include/lib/runtime_instr.h
@@ -17,9 +17,9 @@
#define RT_INSTR_EXIT_CFLUSH U(5)
#define RT_INSTR_TOTAL_IDS U(6)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
PMF_DECLARE_CAPTURE_TIMESTAMP(rt_instr_svc)
PMF_DECLARE_GET_TIMESTAMP(rt_instr_svc)
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* RUNTIME_INSTR_H */
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index 94c39d2..76e6023 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -87,7 +87,7 @@
#define SMC_FROM_SECURE (U(0) << 0)
#define SMC_FROM_NON_SECURE (U(1) << 0)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -155,5 +155,5 @@
smc_uuid_word((_uuid).node[2], (_uuid).node[3], \
(_uuid).node[4], (_uuid).node[5]))
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* SMCCC_H */
diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h
index fcd36e8..0bf3ee0 100644
--- a/include/lib/spinlock.h
+++ b/include/lib/spinlock.h
@@ -7,7 +7,7 @@
#ifndef SPINLOCK_H
#define SPINLOCK_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
diff --git a/include/lib/utils.h b/include/lib/utils.h
index 6748454..cdb125c 100644
--- a/include/lib/utils.h
+++ b/include/lib/utils.h
@@ -11,7 +11,7 @@
* C code should be put in this part of the header to avoid breaking ASM files
* or linker scripts including it.
*/
-#if !(defined(__LINKER__) || defined(__ASSEMBLY__))
+#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
#include <stddef.h>
#include <stdint.h>
@@ -91,6 +91,6 @@
/* Helper to invoke the function defined by DEFINE_LOAD_SYM_ADDR() */
#define LOAD_ADDR_OF(_name) (typeof(_name) *) load_addr_## _name()
-#endif /* !(defined(__LINKER__) || defined(__ASSEMBLY__)) */
+#endif /* !(defined(__LINKER__) || defined(__ASSEMBLER__)) */
#endif /* UTILS_H */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 41f71e8..35ae33a 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -21,10 +21,10 @@
#define BIT_32(nr) (U(1) << (nr))
#define BIT_64(nr) (ULL(1) << (nr))
-#ifdef AARCH32
-#define BIT BIT_32
-#else
+#ifdef __aarch64__
#define BIT BIT_64
+#else
+#define BIT BIT_32
#endif
/*
@@ -32,7 +32,7 @@
* position @h. For example
* GENMASK_64(39, 21) gives us the 64bit vector 0x000000ffffe00000.
*/
-#if defined(__LINKER__) || defined(__ASSEMBLY__)
+#if defined(__LINKER__) || defined(__ASSEMBLER__)
#define GENMASK_32(h, l) \
(((0xFFFFFFFF) << (l)) & (0xFFFFFFFF >> (32 - 1 - (h))))
@@ -46,10 +46,10 @@
(((~UINT64_C(0)) << (l)) & (~UINT64_C(0) >> (64 - 1 - (h))))
#endif
-#ifdef AARCH32
-#define GENMASK GENMASK_32
-#else
+#ifdef __aarch64__
#define GENMASK GENMASK_64
+#else
+#define GENMASK GENMASK_32
#endif
/*
@@ -109,10 +109,10 @@
((_u32) > (UINT32_MAX - (_inc)))
/* Register size of the current architecture. */
-#ifdef AARCH32
-#define REGSZ U(4)
-#else
+#ifdef __aarch64__
#define REGSZ U(8)
+#else
+#define REGSZ U(4)
#endif
/*
diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h
index 85effca..abdf1b6 100644
--- a/include/lib/xlat_tables/xlat_mmu_helpers.h
+++ b/include/lib/xlat_tables/xlat_mmu_helpers.h
@@ -50,7 +50,7 @@
#define MMU_CFG_TTBR0 2
#define MMU_CFG_PARAM_MAX 3
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdbool.h>
#include <stdint.h>
@@ -65,14 +65,7 @@
const uint64_t *base_table, unsigned long long max_pa,
uintptr_t max_va, int xlat_regime);
-#ifdef AARCH32
-/* AArch32 specific translation table API */
-void enable_mmu_svc_mon(unsigned int flags);
-void enable_mmu_hyp(unsigned int flags);
-
-void enable_mmu_direct_svc_mon(unsigned int flags);
-void enable_mmu_direct_hyp(unsigned int flags);
-#else
+#ifdef __aarch64__
/* AArch64 specific translation table APIs */
void enable_mmu_el1(unsigned int flags);
void enable_mmu_el2(unsigned int flags);
@@ -81,11 +74,18 @@
void enable_mmu_direct_el1(unsigned int flags);
void enable_mmu_direct_el2(unsigned int flags);
void enable_mmu_direct_el3(unsigned int flags);
-#endif /* AARCH32 */
+#else
+/* AArch32 specific translation table API */
+void enable_mmu_svc_mon(unsigned int flags);
+void enable_mmu_hyp(unsigned int flags);
+
+void enable_mmu_direct_svc_mon(unsigned int flags);
+void enable_mmu_direct_hyp(unsigned int flags);
+#endif /* __aarch64__ */
bool xlat_arch_is_granule_size_supported(size_t size);
size_t xlat_arch_get_max_supported_granule_size(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* XLAT_MMU_HELPERS_H */
diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h
index 9e2543f..082bb5e 100644
--- a/include/lib/xlat_tables/xlat_tables.h
+++ b/include/lib/xlat_tables/xlat_tables.h
@@ -9,7 +9,7 @@
#include <lib/xlat_tables/xlat_tables_defs.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
@@ -88,5 +88,5 @@
size_t size, unsigned int attr);
void mmap_add(const mmap_region_t *mm);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* XLAT_TABLES_H */
diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h
index 7237534..0ce0cac 100644
--- a/include/lib/xlat_tables/xlat_tables_arch.h
+++ b/include/lib/xlat_tables/xlat_tables_arch.h
@@ -7,10 +7,10 @@
#ifndef XLAT_TABLES_ARCH_H
#define XLAT_TABLES_ARCH_H
-#ifdef AARCH32
-#include "aarch32/xlat_tables_aarch32.h"
-#else
+#ifdef __aarch64__
#include "aarch64/xlat_tables_aarch64.h"
+#else
+#include "aarch32/xlat_tables_aarch32.h"
#endif
/*
diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index 000811f..76cfc0b 100644
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h
@@ -62,7 +62,7 @@
#define OSH (U(0x2) << 6)
#define ISH (U(0x3) << 6)
-#ifdef AARCH64
+#ifdef __aarch64__
/* Guarded Page bit */
#define GP (ULL(1) << 50)
#endif
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h
index 5551426..0e09998 100644
--- a/include/lib/xlat_tables/xlat_tables_v2.h
+++ b/include/lib/xlat_tables/xlat_tables_v2.h
@@ -10,7 +10,7 @@
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <lib/xlat_tables/xlat_tables_v2_helpers.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
@@ -364,5 +364,5 @@
uint32_t *attr);
int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* XLAT_TABLES_V2_H */
diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
index 6a1be32..b17b71a 100644
--- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h
+++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
@@ -16,7 +16,7 @@
#error "Do not include this header file directly. Include xlat_tables_v2.h instead."
#endif
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdbool.h>
#include <stddef.h>
@@ -160,6 +160,6 @@
.initialized = false, \
}
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* XLAT_TABLES_V2_HELPERS_H */
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
index f982b57..4637b67 100644
--- a/include/plat/arm/board/common/board_css_def.h
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -29,7 +29,7 @@
#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
#define BOARD_CSS_PLAT_TYPE_FVP 0x03
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <lib/mmio.h>
@@ -37,7 +37,7 @@
((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#define MAX_IO_DEVICES 3
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index ead1a8b..53bd13f 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -434,7 +434,7 @@
#endif
#endif
-#if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME
+#if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME
/*******************************************************************************
* BL32 specific defines for EL3 runtime in AArch32 mode
******************************************************************************/
@@ -498,17 +498,17 @@
# else
# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
# endif
-#endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */
+#endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */
/*
* BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
* SPD and no SPM, as they are the only ones that can be used as BL32.
*/
-#if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME)
+#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME
# if defined(SPD_none) && !ENABLE_SPM
# undef BL32_BASE
# endif /* defined(SPD_none) && !ENABLE_SPM */
-#endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */
+#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */
/*******************************************************************************
* FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index c8260e8..07a46c5 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -69,7 +69,7 @@
void arm_setup_romlib(void);
-#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
+#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
/*
* Use this macro to instantiate lock before it is used in below
* arm_lock_xxx() macros
@@ -102,7 +102,7 @@
#define arm_lock_get()
#define arm_lock_release()
-#endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */
+#endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */
#if ARM_RECOM_STATE_ID_ENC
/*
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index ec28db0..2adf11d 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -136,7 +136,7 @@
#define SPIDEN_INT_CLR_SHIFT 6
#define SPIDEN_SEL_SET_SHIFT 7
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* SSC_VERSION related accessors */
@@ -150,7 +150,7 @@
(((val) >> SSC_VERSION_CONFIG_SHIFT) & \
SSC_VERSION_CONFIG_MASK)
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/*************************************************************************
* Required platform porting definitions common to all
diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
index 66c88ba..14ae603 100644
--- a/include/plat/common/common_def.h
+++ b/include/plat/common/common_def.h
@@ -20,13 +20,13 @@
/*
* Platform binary types for linking
*/
-#ifdef AARCH32
-#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
-#define PLATFORM_LINKER_ARCH arm
-#else
+#ifdef __aarch64__
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
-#endif /* AARCH32 */
+#else
+#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
+#define PLATFORM_LINKER_ARCH arm
+#endif /* __aarch64__ */
/*
* Generic platform constants
diff --git a/include/plat/marvell/a3700/common/marvell_def.h b/include/plat/marvell/a3700/common/marvell_def.h
index 229b8b0..eb13ba8 100644
--- a/include/plat/marvell/a3700/common/marvell_def.h
+++ b/include/plat/marvell/a3700/common/marvell_def.h
@@ -12,7 +12,7 @@
#include <arch.h>
#include <common/tbbr/tbbr_img_def.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/common_def.h>
/****************************************************************************
diff --git a/include/plat/marvell/a3700/common/plat_marvell.h b/include/plat/marvell/a3700/common/plat_marvell.h
index 8b8b53f..ea7cdcd 100644
--- a/include/plat/marvell/a3700/common/plat_marvell.h
+++ b/include/plat/marvell/a3700/common/plat_marvell.h
@@ -13,7 +13,7 @@
#include <common/bl_common.h>
#include <lib/cassert.h>
#include <lib/el3_runtime/cpu_data.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
/*
* Extern declarations common to Marvell standard platforms
diff --git a/include/plat/marvell/a8k/common/marvell_def.h b/include/plat/marvell/a8k/common/marvell_def.h
index 5ba90f7..4eda01f 100644
--- a/include/plat/marvell/a8k/common/marvell_def.h
+++ b/include/plat/marvell/a8k/common/marvell_def.h
@@ -12,7 +12,7 @@
#include <arch.h>
#include <common/tbbr/tbbr_img_def.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/common_def.h>
/******************************************************************************
diff --git a/include/plat/marvell/a8k/common/plat_marvell.h b/include/plat/marvell/a8k/common/plat_marvell.h
index 65d4de8..5d805a7 100644
--- a/include/plat/marvell/a8k/common/plat_marvell.h
+++ b/include/plat/marvell/a8k/common/plat_marvell.h
@@ -13,7 +13,7 @@
#include <lib/cassert.h>
#include <lib/el3_runtime/cpu_data.h>
#include <lib/utils.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
/*
* Extern declarations common to Marvell standard platforms
diff --git a/include/services/spm_svc.h b/include/services/spm_svc.h
index 57912e8..a3723a0 100644
--- a/include/services/spm_svc.h
+++ b/include/services/spm_svc.h
@@ -63,7 +63,7 @@
#endif /* SPM_MM */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -85,6 +85,6 @@
#endif /* SPM_MM */
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SPM_SVC_H */
diff --git a/lib/cpus/aarch64/cortex_hercules.S b/lib/cpus/aarch64/cortex_hercules.S
index 25287de..4e04814 100644
--- a/lib/cpus/aarch64/cortex_hercules.S
+++ b/lib/cpus/aarch64/cortex_hercules.S
@@ -16,6 +16,35 @@
#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-Hercules
+ * -------------------------------------------------
+ */
+#if ENABLE_AMU
+func cortex_hercules_reset_func
+ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
+ mrs x0, actlr_el3
+ bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ msr actlr_el3, x0
+
+ /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
+ mrs x0, actlr_el2
+ bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ msr actlr_el2, x0
+
+ /* Enable group0 counters */
+ mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
+ msr CPUAMCNTENSET0_EL0, x0
+
+ /* Enable group1 counters */
+ mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
+ msr CPUAMCNTENSET1_EL0, x0
+ isb
+
+ ret
+endfunc cortex_hercules_reset_func
+#endif
+
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
@@ -60,6 +89,12 @@
ret
endfunc cortex_hercules_cpu_reg_dump
+#if ENABLE_AMU
+#define HERCULES_RESET_FUNC cortex_hercules_reset_func
+#else
+#define HERCULES_RESET_FUNC CPU_NO_RESET_FUNC
+#endif
+
declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
- CPU_NO_RESET_FUNC, \
+ HERCULES_RESET_FUNC, \
cortex_hercules_core_pwr_dwn
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index aeb3560..f43b217 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c
@@ -18,9 +18,9 @@
#ifdef IMAGE_BL1
# define BL_STRING "BL1"
-#elif defined(AARCH64) && defined(IMAGE_BL31)
+#elif defined(__aarch64__) && defined(IMAGE_BL31)
# define BL_STRING "BL31"
-#elif defined(AARCH32) && defined(IMAGE_BL32)
+#elif !defined(__arch64__) && defined(IMAGE_BL32)
# define BL_STRING "BL32"
#elif defined(IMAGE_BL2) && BL2_AT_EL3
# define BL_STRING "BL2"
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index cc13fc1..f906f51 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -167,10 +167,10 @@
unsigned int their_bakery_data;
me = plat_my_core_pos();
-#ifdef AARCH32
- is_cached = read_sctlr() & SCTLR_C_BIT;
-#else
+#ifdef __aarch64__
is_cached = read_sctlr_el3() & SCTLR_C_BIT;
+#else
+ is_cached = read_sctlr() & SCTLR_C_BIT;
#endif
/* Get a ticket */
@@ -228,10 +228,10 @@
void bakery_lock_release(bakery_lock_t *lock)
{
bakery_info_t *my_bakery_info;
-#ifdef AARCH32
- unsigned int is_cached = read_sctlr() & SCTLR_C_BIT;
-#else
+#ifdef __aarch64__
unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT;
+#else
+ unsigned int is_cached = read_sctlr() & SCTLR_C_BIT;
#endif
my_bakery_info = get_bakery_info(plat_my_core_pos(), lock);
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index f7392fd..2a40793 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -176,7 +176,7 @@
*/
if (!tee_validate_header(header)) {
INFO("Invalid OPTEE header, set legacy mode.\n");
-#ifdef AARCH64
+#ifdef __aarch64__
header_ep->args.arg0 = MODE_RW_64;
#else
header_ep->args.arg0 = MODE_RW_32;
@@ -222,7 +222,7 @@
if (header->arch == 0) {
header_ep->args.arg0 = MODE_RW_32;
} else {
-#ifdef AARCH64
+#ifdef __aarch64__
header_ep->args.arg0 = MODE_RW_64;
#else
ERROR("Cannot boot an AArch64 OP-TEE\n");
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 3f5e989..5d24356 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -619,57 +619,11 @@
* This function determines the full entrypoint information for the requested
* PSCI entrypoint on power on/resume and returns it.
******************************************************************************/
-#ifdef AARCH32
+#ifdef __aarch64__
static int psci_get_ns_ep_info(entry_point_info_t *ep,
uintptr_t entrypoint,
u_register_t context_id)
{
- u_register_t ep_attr;
- unsigned int aif, ee, mode;
- u_register_t scr = read_scr();
- u_register_t ns_sctlr, sctlr;
-
- /* Switch to non secure state */
- write_scr(scr | SCR_NS_BIT);
- isb();
- ns_sctlr = read_sctlr();
-
- sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr;
-
- /* Return to original state */
- write_scr(scr);
- isb();
- ee = 0;
-
- ep_attr = NON_SECURE | EP_ST_DISABLE;
- if (sctlr & SCTLR_EE_BIT) {
- ep_attr |= EP_EE_BIG;
- ee = 1;
- }
- SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
-
- ep->pc = entrypoint;
- zeromem(&ep->args, sizeof(ep->args));
- ep->args.arg0 = context_id;
-
- mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
-
- /*
- * TODO: Choose async. exception bits if HYP mode is not
- * implemented according to the values of SCR.{AW, FW} bits
- */
- aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT;
-
- ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif);
-
- return PSCI_E_SUCCESS;
-}
-
-#else
-static int psci_get_ns_ep_info(entry_point_info_t *ep,
- uintptr_t entrypoint,
- u_register_t context_id)
-{
u_register_t ep_attr, sctlr;
unsigned int daif, ee, mode;
u_register_t ns_scr_el3 = read_scr_el3();
@@ -722,7 +676,53 @@
return PSCI_E_SUCCESS;
}
-#endif
+#else /* !__aarch64__ */
+static int psci_get_ns_ep_info(entry_point_info_t *ep,
+ uintptr_t entrypoint,
+ u_register_t context_id)
+{
+ u_register_t ep_attr;
+ unsigned int aif, ee, mode;
+ u_register_t scr = read_scr();
+ u_register_t ns_sctlr, sctlr;
+
+ /* Switch to non secure state */
+ write_scr(scr | SCR_NS_BIT);
+ isb();
+ ns_sctlr = read_sctlr();
+
+ sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr;
+
+ /* Return to original state */
+ write_scr(scr);
+ isb();
+ ee = 0;
+
+ ep_attr = NON_SECURE | EP_ST_DISABLE;
+ if (sctlr & SCTLR_EE_BIT) {
+ ep_attr |= EP_EE_BIG;
+ ee = 1;
+ }
+ SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
+
+ ep->pc = entrypoint;
+ zeromem(&ep->args, sizeof(ep->args));
+ ep->args.arg0 = context_id;
+
+ mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
+
+ /*
+ * TODO: Choose async. exception bits if HYP mode is not
+ * implemented according to the values of SCR.{AW, FW} bits
+ */
+ aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT;
+
+ ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif);
+
+ return PSCI_E_SUCCESS;
+}
+
+#endif /* __aarch64__ */
/*******************************************************************************
* This function validates the entrypoint with the platform layer if the
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 60c1458..cec9404 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -15,7 +15,7 @@
WRAPPER_DIR = ../../$(BUILD_PLAT)/libwrapper
LIBS = -lmbedtls -lfdt -lc
INC = $(INCLUDES:-I%=-I../../%)
-PPFLAGS = $(INC) $(DEFINES) -P -D__ASSEMBLY__ -D__LINKER__ -MD -MP -MT $(BUILD_DIR)/romlib.ld
+PPFLAGS = $(INC) $(DEFINES) -P -x assembler-with-cpp -D__LINKER__ -MD -MP -MT $(BUILD_DIR)/romlib.ld
OBJS = $(BUILD_DIR)/jmptbl.o $(BUILD_DIR)/init.o
MAPFILE = ../../$(BUILD_PLAT)/romlib/romlib.map
diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c
index bf3ae1e..f4b64b3 100644
--- a/lib/xlat_tables_v2/xlat_tables_context.c
+++ b/lib/xlat_tables_v2/xlat_tables_context.c
@@ -136,48 +136,48 @@
#define MAX_PHYS_ADDR tf_xlat_ctx.max_pa
#endif
-#ifdef AARCH32
+#ifdef __aarch64__
-void enable_mmu_svc_mon(unsigned int flags)
+void enable_mmu_el1(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
- enable_mmu_direct_svc_mon(flags);
+ enable_mmu_direct_el1(flags);
}
-void enable_mmu_hyp(unsigned int flags)
+void enable_mmu_el2(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
tf_xlat_ctx.va_max_address, EL2_REGIME);
- enable_mmu_direct_hyp(flags);
+ enable_mmu_direct_el2(flags);
}
-#else
-
-void enable_mmu_el1(unsigned int flags)
+void enable_mmu_el3(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
- tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
- enable_mmu_direct_el1(flags);
+ tf_xlat_ctx.va_max_address, EL3_REGIME);
+ enable_mmu_direct_el3(flags);
}
-void enable_mmu_el2(unsigned int flags)
+#else /* !__aarch64__ */
+
+void enable_mmu_svc_mon(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
- tf_xlat_ctx.va_max_address, EL2_REGIME);
- enable_mmu_direct_el2(flags);
+ tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
+ enable_mmu_direct_svc_mon(flags);
}
-void enable_mmu_el3(unsigned int flags)
+void enable_mmu_hyp(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
- tf_xlat_ctx.va_max_address, EL3_REGIME);
- enable_mmu_direct_el3(flags);
+ tf_xlat_ctx.va_max_address, EL2_REGIME);
+ enable_mmu_direct_hyp(flags);
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c
index 761d00c..232142e 100644
--- a/lib/xlat_tables_v2/xlat_tables_utils.c
+++ b/lib/xlat_tables_v2/xlat_tables_utils.c
@@ -97,7 +97,7 @@
printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
-#ifdef AARCH64
+#ifdef __aarch64__
/* Check Guarded Page bit */
if ((desc & GP) != 0ULL) {
printf("-GP");
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 2d41b2d..b89d87e 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -273,7 +273,7 @@
$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
$$(ECHO) " PP $$<"
- $$(Q)$$(CPP) $$(CPPFLAGS) -P -D__ASSEMBLY__ -D__LINKER__ $(MAKE_DEP) -D$(IMAGE) -o $$@ $$<
+ $$(Q)$$(CPP) $$(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) -P -x assembler-with-cpp -D__LINKER__ $(MAKE_DEP) -D$(IMAGE) -o $$@ $$<
-include $(DEP)
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index b885b47..36cd500 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -81,7 +81,7 @@
MAP_DEVICE0,
MAP_DEVICE1,
ARM_MAP_NS_DRAM1,
-#ifdef AARCH64
+#ifdef __aarch64__
ARM_MAP_DRAM2,
#endif
#ifdef SPD_tspd
@@ -150,7 +150,7 @@
#endif
#ifdef IMAGE_BL32
const mmap_region_t plat_arm_mmap[] = {
-#ifdef AARCH32
+#ifndef __aarch64__
ARM_MAP_SHARED_RAM,
ARM_V2M_MAP_MEM_PROTECT,
#endif
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 207cd31..4f26277 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -120,7 +120,7 @@
#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
#endif
-#ifdef AARCH32
+#ifndef __aarch64__
/*
* Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
@@ -259,7 +259,7 @@
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifdef AARCH64
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index b3b3672..4e575e1 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -331,7 +331,7 @@
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifdef AARCH64
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index d693c26..83aeeb4 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -291,7 +291,7 @@
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifdef AARCH64
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c
index 118c19a..98c5d3c 100644
--- a/plat/arm/board/juno/juno_common.c
+++ b/plat/arm/board/juno/juno_common.c
@@ -37,7 +37,7 @@
CSS_MAP_DEVICE,
SOC_CSS_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
-#ifdef AARCH64
+#ifdef __aarch64__
ARM_MAP_DRAM2,
#endif
#ifdef SPD_tspd
@@ -74,7 +74,7 @@
#endif
#ifdef IMAGE_BL32
const mmap_region_t plat_arm_mmap[] = {
-#ifdef AARCH32
+#ifndef __aarch64__
ARM_MAP_SHARED_RAM,
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
index ff583a9..7348bf5 100644
--- a/plat/arm/board/n1sdp/include/platform_def.h
+++ b/plat/arm/board/n1sdp/include/platform_def.h
@@ -34,7 +34,7 @@
* space the physical & virtual address space limits are extended to
* 40-bits.
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
#else
diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h
index c62cda8..50b04f0 100644
--- a/plat/arm/board/rde1edge/include/platform_def.h
+++ b/plat/arm/board/rde1edge/include/platform_def.h
@@ -29,7 +29,7 @@
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h
index 2c7b8bd..580ab8e 100644
--- a/plat/arm/board/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/rdn1edge/include/platform_def.h
@@ -30,7 +30,7 @@
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h
index 883403b..f00146f 100644
--- a/plat/arm/board/sgi575/include/platform_def.h
+++ b/plat/arm/board/sgi575/include/platform_def.h
@@ -30,7 +30,7 @@
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
diff --git a/plat/arm/board/sgm775/include/platform_def.h b/plat/arm/board/sgm775/include/platform_def.h
index 3e1fdd1..27d1b33 100644
--- a/plat/arm/board/sgm775/include/platform_def.h
+++ b/plat/arm/board/sgm775/include/platform_def.h
@@ -15,7 +15,7 @@
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
diff --git a/plat/arm/board/sgm775/tsp/tsp-sgm775.mk b/plat/arm/board/sgm775/tsp/tsp-sgm775.mk
new file mode 100644
index 0000000..129b586
--- /dev/null
+++ b/plat/arm/board/sgm775/tsp/tsp-sgm775.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/css/sgm/tsp/tsp-sgm.mk
\ No newline at end of file
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 8905bb0..b19a7c3 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -121,11 +121,11 @@
};
setup_page_tables(bl_regions, plat_arm_get_mmap());
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el3(0);
-#endif /* AARCH32 */
+#else
+ enable_mmu_svc_mon(0);
+#endif /* __aarch64__ */
arm_setup_romlib();
}
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c
index 0c01c87..97b5a88 100644
--- a/plat/arm/common/arm_bl2_el3_setup.c
+++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -83,10 +83,10 @@
setup_page_tables(bl_regions, plat_arm_get_mmap());
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el3(0);
+#else
+ enable_mmu_svc_mon(0);
#endif
}
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 32617f6..cdf87ca 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -128,10 +128,10 @@
setup_page_tables(bl_regions, plat_arm_get_mmap());
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el1(0);
+#else
+ enable_mmu_svc_mon(0);
#endif
arm_setup_romlib();
@@ -153,7 +153,7 @@
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
#ifdef SPD_opteed
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c
index 9f44b9e..3614c7d 100644
--- a/plat/arm/common/arm_bl2u_setup.c
+++ b/plat/arm/common/arm_bl2u_setup.c
@@ -83,10 +83,10 @@
setup_page_tables(bl_regions, plat_arm_get_mmap());
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el1(0);
+#else
+ enable_mmu_svc_mon(0);
#endif
arm_setup_romlib();
}
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index f5ce4d2..bc0cf9a 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -59,7 +59,7 @@
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t arm_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
@@ -97,7 +97,7 @@
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
/*******************************************************************************
* Configures access to the system counter timer module.
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index 93bebf3..7f4957f 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -83,8 +83,8 @@
* can use GIC system registers to manage interrupts and does
* not need GIC interface base addresses to be configured.
*/
-#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
- (defined(IMAGE_BL31) && !defined(AARCH32))
+#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
+ (defined(__aarch64__) && defined(IMAGE_BL31))
gicv3_driver_init(&arm_gic_data);
#endif
}
diff --git a/plat/arm/common/arm_nor_psci_mem_protect.c b/plat/arm/common/arm_nor_psci_mem_protect.c
index 3a70059..b9181eb 100644
--- a/plat/arm/common/arm_nor_psci_mem_protect.c
+++ b/plat/arm/common/arm_nor_psci_mem_protect.c
@@ -26,7 +26,7 @@
static mem_region_t arm_ram_ranges[] = {
{DRAM1_NS_IMAGE_LIMIT, DRAM1_PROTECTED_SIZE},
-#ifdef AARCH64
+#ifdef __aarch64__
{ARM_DRAM2_BASE, 1u << ONE_GB_SHIFT},
#endif
};
diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
index cb87baf..c95f452 100644
--- a/plat/arm/common/arm_pm.c
+++ b/plat/arm/common/arm_pm.c
@@ -116,7 +116,7 @@
(ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
return 0;
}
-#ifndef AARCH32
+#ifdef __aarch64__
if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint <
(ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) {
return 0;
diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/execution_state_switch.c
index d471130..00ac16e 100644
--- a/plat/arm/common/execution_state_switch.c
+++ b/plat/arm/common/execution_state_switch.c
@@ -40,7 +40,7 @@
void *handle)
{
/* Execution state can be switched only if EL3 is AArch64 */
-#ifdef AARCH64
+#ifdef __aarch64__
bool caller_64, thumb = false, from_el2;
unsigned int el, endianness;
u_register_t spsr, pc, scr, sctlr;
@@ -173,7 +173,7 @@
SMC_RET1(handle, STATE_SW_E_PARAM);
exec_denied:
-#endif
+#endif /* __aarch64__ */
/* State switch denied */
SMC_RET1(handle, STATE_SW_E_DENIED);
}
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index 032a1f4..a9cc852 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -187,7 +187,7 @@
/* Platform ID address */
#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* SSC_VERSION related accessors */
/* Returns the part number of the platform */
#define GET_SGI_PART_NUM \
@@ -195,7 +195,7 @@
/* Returns the configuration number of the platform */
#define GET_SGI_CONFIG_NUM \
GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/*******************************************************************************
* Memprotect definitions
diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h
index 8581844..f349c19 100644
--- a/plat/arm/css/sgm/include/sgm_base_platform_def.h
+++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h
@@ -51,7 +51,7 @@
/* Platform ID address */
#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* SSC_VERSION related accessors */
/* Returns the part number of the platform */
#define GET_PLAT_PART_NUM \
@@ -59,7 +59,7 @@
/* Returns the configuration number of the platform */
#define GET_PLAT_CONFIG_NUM \
GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/*************************************************************************
@@ -134,11 +134,6 @@
#endif
/*
- * tspd support is conditional so enable this for CSS sgm platforms.
- */
-#define SPD_tspd
-
-/*
* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
* SCP_BL2 size plus a little space for growth.
*/
diff --git a/plat/arm/css/sgm/tsp/tsp-sgm.mk b/plat/arm/css/sgm/tsp/tsp-sgm.mk
index a9e4131..de5e5b7 100644
--- a/plat/arm/css/sgm/tsp/tsp-sgm.mk
+++ b/plat/arm/css/sgm/tsp/tsp-sgm.mk
@@ -6,6 +6,6 @@
BL32_SOURCES += ${SGM_GIC_SOURCES} \
${CSS_SGM_BASE}/sgm_plat_config.c \
- plat/arm/board/sgm/tsp/sgm_tsp_setup.c
+ plat/arm/css/sgm/tsp/sgm_tsp_setup.c
include plat/arm/common/tsp/arm_tsp.mk
diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c
index f5ed6fc..4a8a7ee 100644
--- a/plat/common/plat_gicv3.c
+++ b/plat/common/plat_gicv3.c
@@ -300,7 +300,7 @@
#pragma weak plat_ic_end_of_interrupt
/* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */
-#ifdef AARCH32
+#ifndef __aarch64__
#define IS_IN_EL1() IS_IN_SECURE()
#endif
diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c
index 1a29d9c..16bec79 100644
--- a/plat/common/plat_psci_common.c
+++ b/plat/common/plat_psci_common.c
@@ -20,10 +20,10 @@
#define MHZ_TICKS_PER_SEC 1000000U
/* Maximum time-stamp value read from architectural counters */
-#ifdef AARCH32
-#define MAX_TS UINT32_MAX
-#else
+#ifdef __aarch64__
#define MAX_TS UINT64_MAX
+#else
+#define MAX_TS UINT32_MAX
#endif
/* Following are used as ID's to capture time-stamp */
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index c57fea9..2f96efc 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -77,7 +77,7 @@
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t hikey_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
@@ -112,7 +112,7 @@
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
int hikey_bl2_handle_post_image_load(unsigned int image_id)
{
@@ -125,7 +125,7 @@
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
#ifdef SPD_opteed
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
diff --git a/plat/hisilicon/hikey/include/hikey_layout.h b/plat/hisilicon/hikey/include/hikey_layout.h
index a87648e..4b8dc53 100644
--- a/plat/hisilicon/hikey/include/hikey_layout.h
+++ b/plat/hisilicon/hikey/include/hikey_layout.h
@@ -113,7 +113,7 @@
#endif
/* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
#ifdef SPD_none
#undef BL32_BASE
#endif /* SPD_none */
diff --git a/plat/hisilicon/hikey/include/hisi_pwrc.h b/plat/hisilicon/hikey/include/hisi_pwrc.h
index f1cc297..cbb4651 100644
--- a/plat/hisilicon/hikey/include/hisi_pwrc.h
+++ b/plat/hisilicon/hikey/include/hisi_pwrc.h
@@ -7,7 +7,7 @@
#ifndef HISI_PWRC_H
#define HISI_PWRC_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void hisi_pwrc_set_cluster_wfi(unsigned int id);
void hisi_pwrc_set_core_bx_addr(unsigned int core,
@@ -17,6 +17,6 @@
unsigned int cluster);
int hisi_pwrc_setup(void);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* HISI_PWRC_H */
diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
index 7102de8..fc9ddab 100644
--- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
@@ -168,7 +168,7 @@
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t hikey960_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
@@ -203,7 +203,7 @@
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
int hikey960_bl2_handle_post_image_load(unsigned int image_id)
{
@@ -216,7 +216,7 @@
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
#ifdef SPD_opteed
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h
index 7c3c102..f6edad6 100644
--- a/plat/hisilicon/hikey960/include/platform_def.h
+++ b/plat/hisilicon/hikey960/include/platform_def.h
@@ -95,7 +95,7 @@
#endif
/* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
#ifdef SPD_none
#undef BL32_BASE
#endif /* SPD_none */
diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c
index 11403b0..cc9d975 100644
--- a/plat/hisilicon/poplar/bl2_plat_setup.c
+++ b/plat/hisilicon/poplar/bl2_plat_setup.c
@@ -54,7 +54,7 @@
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t poplar_get_spsr_for_bl33_entry(void)
{
unsigned long el_status;
@@ -93,7 +93,7 @@
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
int poplar_bl2_handle_post_image_load(unsigned int image_id)
{
@@ -107,7 +107,7 @@
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
#ifdef SPD_opteed
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h
index 8f7a155..9783f8d 100644
--- a/plat/hisilicon/poplar/include/platform_def.h
+++ b/plat/hisilicon/poplar/include/platform_def.h
@@ -107,7 +107,7 @@
#endif
/* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
#ifdef SPD_none
#undef BL32_BASE
#endif /* SPD_none */
diff --git a/plat/imx/common/include/imx8_lpuart.h b/plat/imx/common/include/imx8_lpuart.h
index 63449e7..0ea284f 100644
--- a/plat/imx/common/include/imx8_lpuart.h
+++ b/plat/imx/common/include/imx8_lpuart.h
@@ -50,7 +50,7 @@
#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
#define LPUART_BAUD_M10_MASK (0x20000000U)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -61,6 +61,6 @@
int console_lpuart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_lpuart_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* IMX8_LPUART_H */
diff --git a/plat/imx/common/include/imx_clock.h b/plat/imx/common/include/imx_clock.h
index ce245ad..d75dcff 100644
--- a/plat/imx/common/include/imx_clock.h
+++ b/plat/imx/common/include/imx_clock.h
@@ -1,6 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IMX_CLOCK_H
@@ -819,6 +818,8 @@
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD1_DIV2 ((BIT(26) | BIT(25) | BIT(24))
+#define WDOG_DEFAULT_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
/* Target CSI_MCLK_CLK_ROOT */
diff --git a/plat/imx/common/include/imx_io_mux.h b/plat/imx/common/include/imx_io_mux.h
index 9b30421..d588cfd 100644
--- a/plat/imx/common/include/imx_io_mux.h
+++ b/plat/imx/common/include/imx_io_mux.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,7 @@
#define IMX_IO_MUX_H
#include <stdint.h>
+#include <lib/utils_def.h>
/*
* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
@@ -20,7 +21,10 @@
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET 0x0020
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET 0x0024
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET 0x0028
+
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET 0x002C
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B BIT(0)
+
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET 0x0030
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET 0x0034
@@ -121,8 +125,24 @@
#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET 0x0154
#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET 0x0158
#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET 0x015C
+
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET 0x0160
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT0_I2C4_SCL 0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT2_WDOG4_WDOG_B BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT3_CSI_PIXCLK (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT4_USB_OTG1_ID BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT5_GPIO4_IO14 (BIT(2) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT6_EPDC_VCOM0 (BIT(2) | BIT(1))
+
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET 0x0164
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT0_I2C4_SDA 0x0
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA BIT(0)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT2_WDOG4_WDOG_RST_B_DEB BIT(1)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT3_CSI_MCLK (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT4_USB_OTG2_ID BIT(2)
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT5_GPIO4_IO15 (BIT(1) | BIT(0))
+#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT6_EPDC_VCOM1 (BIT(2) | BIT(1))
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET 0x0168
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK 0x00
@@ -165,6 +185,7 @@
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET 0x01C4
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET 0x01C8
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET 0x01CC
+
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET 0x01D0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET 0x01D4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET 0x01D8
@@ -391,6 +412,7 @@
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET 0x0434
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET 0x0438
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET 0x043C
+
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET 0x0440
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET 0x0444
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET 0x0448
@@ -403,6 +425,19 @@
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET 0x0464
#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET 0x0468
#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET 0x046C
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_0_X1 0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4 BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_2_X2 BIT(1)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6 (BIT(1) | BIT(0))
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4 BIT(0)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW BIT(2)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_FAST 0
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_HYS BIT(3)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PE BIT(4)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PD_100K (0 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_5K (1 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K (2 << 5)
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_100K (3 << 5)
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0470
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0474
@@ -588,7 +623,15 @@
#define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET 0x0708
#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET 0x070C
#define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET 0x0710
+
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET 0x0714
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SCL_ALT1 0x00
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SDA_ALT1 BIT(0)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_RX_DATA_ALT2 BIT(1)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_TX_BCLK_ALT2 (BIT(1) | BIT(0))
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO06_ALT3 BIT(2)
+#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO07_ALT3 (BIT(2) | BIT(1))
+
#define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET 0x0718
#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET 0x071C
#define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET 0x0720
diff --git a/plat/imx/common/include/imx_uart.h b/plat/imx/common/include/imx_uart.h
index 1b52e2f..cc1b531 100644
--- a/plat/imx/common/include/imx_uart.h
+++ b/plat/imx/common/include/imx_uart.h
@@ -9,7 +9,7 @@
#include <drivers/console.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
typedef struct {
console_t console;
@@ -18,6 +18,6 @@
int console_imx_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_uart_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* IMX_UART_H */
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
new file mode 100644
index 0000000..849ddcd
--- /dev/null
+++ b/plat/imx/imx7/common/imx7.mk
@@ -0,0 +1,110 @@
+#
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Architecture
+$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
+
+TF_CFLAGS += -mfpu=neon
+ASFLAGS += -mfpu=neon
+
+# Platform
+PLAT_INCLUDES := -Idrivers/imx/uart \
+ -Iplat/imx/common/include \
+ -Iplat/imx/imx7/include \
+ -Idrivers/imx/timer \
+ -Idrivers/imx/usdhc \
+
+# Translation tables library
+include lib/xlat_tables_v2/xlat_tables.mk
+
+BL2_SOURCES += common/desc_image_load.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/mmc/mmc.c \
+ drivers/io/io_block.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ drivers/imx/timer/imx_gpt.c \
+ drivers/imx/uart/imx_uart.c \
+ drivers/imx/uart/imx_crash_uart.S \
+ lib/aarch32/arm32_aeabi_divmod.c \
+ lib/aarch32/arm32_aeabi_divmod_a32.S \
+ lib/cpus/aarch32/cortex_a7.S \
+ lib/optee/optee_utils.c \
+ plat/imx/common/imx_aips.c \
+ plat/imx/common/imx_caam.c \
+ plat/imx/common/imx_clock.c \
+ plat/imx/common/imx_csu.c \
+ plat/imx/common/imx_io_mux.c \
+ plat/imx/common/imx_snvs.c \
+ plat/imx/common/imx_wdog.c \
+ plat/imx/common/imx7_clock.c \
+ plat/imx/imx7/common/imx7_bl2_mem_params_desc.c \
+ plat/imx/imx7/common/imx7_bl2_el3_common.c \
+ plat/imx/imx7/common/imx7_helpers.S \
+ plat/imx/imx7/common/imx7_image_load.c \
+ plat/imx/imx7/common/imx7_io_storage.c \
+ plat/imx/common/aarch32/imx_uart_console.S \
+ ${XLAT_TABLES_LIB_SRCS}
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+
+include drivers/auth/mbedtls/mbedtls_crypto.mk
+include drivers/auth/mbedtls/mbedtls_x509.mk
+
+AUTH_SOURCES := drivers/auth/auth_mod.c \
+ drivers/auth/crypto_mod.c \
+ drivers/auth/img_parser_mod.c \
+ drivers/auth/tbbr/tbbr_cot.c
+
+BL2_SOURCES += ${AUTH_SOURCES} \
+ plat/common/tbbr/plat_tbbr.c \
+ plat/imx/imx7/common/imx7_trusted_boot.c \
+ plat/imx/imx7/common/imx7_rotpk.S
+
+ROT_KEY = $(BUILD_PLAT)/rot_key.pem
+ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
+
+$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
+$(eval $(call MAKE_LIB_DIRS))
+
+$(BUILD_PLAT)/bl2/imx7_rotpk.o: $(ROTPK_HASH)
+
+certificates: $(ROT_KEY)
+
+$(ROT_KEY): | $(BUILD_PLAT)
+ @echo " OPENSSL $@"
+ @if [ ! -f $(ROT_KEY) ]; then \
+ openssl genrsa 2048 > $@ 2>/dev/null; \
+ fi
+
+$(ROTPK_HASH): $(ROT_KEY)
+ @echo " OPENSSL $@"
+ $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ openssl dgst -sha256 -binary > $@ 2>/dev/null
+endif
+
+# Add the build options to pack BLx images and kernel device tree
+# in the FIP if the platform requires.
+ifneq ($(BL2),)
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
+endif
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
+endif
+ifneq ($(HW_CONFIG),)
+$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
+endif
+
+# Verify build config
+# -------------------
+
+ifeq (${ARCH},aarch64)
+ $(error Error: AArch64 not supported on i.mx7)
+endif
diff --git a/plat/imx/imx7/common/imx7_bl2_el3_common.c b/plat/imx/imx7/common/imx7_bl2_el3_common.c
new file mode 100644
index 0000000..a1e2aaf
--- /dev/null
+++ b/plat/imx/imx7/common/imx7_bl2_el3_common.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <drivers/mmc.h>
+#include <lib/xlat_tables/xlat_mmu_helpers.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <lib/mmio.h>
+#include <lib/optee_utils.h>
+#include <lib/utils.h>
+
+#include <imx_aips.h>
+#include <imx_caam.h>
+#include <imx_clock.h>
+#include <imx_csu.h>
+#include <imx_gpt.h>
+#include <imx_uart.h>
+#include <imx_snvs.h>
+#include <imx_wdog.h>
+#include <imx7_def.h>
+
+#ifndef AARCH32_SP_OPTEE
+#error "Must build with OPTEE support included"
+#endif
+
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+ return IMX7_UBOOT_BASE;
+}
+
+static uint32_t imx7_get_spsr_for_bl32_entry(void)
+{
+ return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
+ DISABLE_ALL_EXCEPTIONS);
+}
+
+static uint32_t imx7_get_spsr_for_bl33_entry(void)
+{
+ return SPSR_MODE32(MODE32_svc,
+ plat_get_ns_image_entrypoint() & 0x1,
+ SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+ int err = 0;
+ bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+ bl_mem_params_node_t *hw_cfg_mem_params = NULL;
+
+ bl_mem_params_node_t *pager_mem_params = NULL;
+ bl_mem_params_node_t *paged_mem_params = NULL;
+
+ assert(bl_mem_params);
+
+ switch (image_id) {
+ case BL32_IMAGE_ID:
+ pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ assert(pager_mem_params);
+
+ paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+ assert(paged_mem_params);
+
+ err = parse_optee_header(&bl_mem_params->ep_info,
+ &pager_mem_params->image_info,
+ &paged_mem_params->image_info);
+ if (err != 0)
+ WARN("OPTEE header parse error.\n");
+
+ /*
+ * When ATF loads the DTB the address of the DTB is passed in
+ * arg2, if an hw config image is present use the base address
+ * as DTB address an pass it as arg2
+ */
+ hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
+
+ bl_mem_params->ep_info.args.arg0 =
+ bl_mem_params->ep_info.args.arg1;
+ bl_mem_params->ep_info.args.arg1 = 0;
+ if (hw_cfg_mem_params)
+ bl_mem_params->ep_info.args.arg2 =
+ hw_cfg_mem_params->image_info.image_base;
+ else
+ bl_mem_params->ep_info.args.arg2 = 0;
+ bl_mem_params->ep_info.args.arg3 = 0;
+ bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl32_entry();
+ break;
+
+ case BL33_IMAGE_ID:
+ /* AArch32 only core: OP-TEE expects NSec EP in register LR */
+ pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
+ assert(pager_mem_params);
+ pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
+
+ /* BL33 expects to receive the primary CPU MPID (through r0) */
+ bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
+ bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl33_entry();
+ break;
+
+ default:
+ /* Do nothing in default case */
+ break;
+ }
+
+ return err;
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+ /* Setup the MMU here */
+}
+
+static void imx7_setup_system_counter(void)
+{
+ unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
+
+ /* Set the frequency table index to our target frequency */
+ write_cntfrq(freq);
+
+ /* Enable system counter @ frequency table index 0, halt on debug */
+ mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
+ CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
+}
+
+static void imx7_setup_wdog_clocks(void)
+{
+ uint32_t wdog_en_bits = (uint32_t)WDOG_DEFAULT_CLK_SELECT;
+
+ imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
+ imx_clock_enable_wdog(0);
+ imx_clock_enable_wdog(1);
+ imx_clock_enable_wdog(2);
+ imx_clock_enable_wdog(3);
+}
+
+
+/*
+ * bl2_el3_early_platform_setup()
+ * MMU off
+ */
+void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+ u_register_t arg3, u_register_t arg4)
+{
+ static console_imx_uart_t console;
+ int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME;
+
+ /* Initialize common components */
+ imx_aips_init();
+ imx_csu_init();
+ imx_snvs_init();
+ imx_gpt_ops_init(GPT1_BASE_ADDR);
+ imx_clock_init();
+ imx7_setup_system_counter();
+ imx7_setup_wdog_clocks();
+
+ /* Platform specific setup */
+ imx7_platform_setup(arg1, arg2, arg3, arg4);
+
+ /* Init UART, clock should be enabled in imx7_platform_setup() */
+ console_imx_uart_register(PLAT_IMX7_BOOT_UART_BASE,
+ PLAT_IMX7_BOOT_UART_CLK_IN_HZ,
+ PLAT_IMX7_CONSOLE_BAUDRATE,
+ &console);
+ console_set_scope(&console.console, console_scope);
+
+ /* Open handles to persistent storage */
+ plat_imx7_io_setup();
+
+ /* Setup higher-level functionality CAAM, RTC etc */
+ imx_caam_init();
+ imx_wdog_init();
+
+ /* Print out the expected memory map */
+ VERBOSE("\tOPTEE 0x%08x-0x%08x\n", IMX7_OPTEE_BASE, IMX7_OPTEE_LIMIT);
+ VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
+ VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
+ VERBOSE("\tFIP 0x%08x-0x%08x\n", IMX7_FIP_BASE, IMX7_FIP_LIMIT);
+ VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", IMX7_DTB_OVERLAY_BASE, IMX7_DTB_OVERLAY_LIMIT);
+ VERBOSE("\tDTB 0x%08x-0x%08x\n", IMX7_DTB_BASE, IMX7_DTB_LIMIT);
+ VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", IMX7_UBOOT_BASE, IMX7_UBOOT_LIMIT);
+}
+
+/*
+ * bl2_platform_setup()
+ * MMU on - enabled by bl2_el3_plat_arch_setup()
+ */
+void bl2_platform_setup(void)
+{
+}
diff --git a/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c
similarity index 83%
rename from plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c
rename to plat/imx/imx7/common/imx7_bl2_mem_params_desc.c
index c670d42..f9b2983 100644
--- a/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c
+++ b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,8 +22,8 @@
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
image_info_t, 0),
- .image_info.image_base = WARP7_OPTEE_BASE,
- .image_info.image_max_size = WARP7_OPTEE_SIZE,
+ .image_info.image_base = IMX7_OPTEE_BASE,
+ .image_info.image_max_size = IMX7_OPTEE_SIZE,
.next_handoff_image_id = BL33_IMAGE_ID,
},
@@ -36,8 +36,8 @@
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
- .image_info.image_base = WARP7_OPTEE_BASE,
- .image_info.image_max_size = WARP7_OPTEE_SIZE,
+ .image_info.image_base = IMX7_OPTEE_BASE,
+ .image_info.image_max_size = IMX7_OPTEE_SIZE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
@@ -70,8 +70,8 @@
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
- .image_info.image_base = WARP7_UBOOT_BASE,
- .image_info.image_max_size = WARP7_UBOOT_SIZE,
+ .image_info.image_base = IMX7_UBOOT_BASE,
+ .image_info.image_max_size = IMX7_UBOOT_SIZE,
# endif /* PRELOADED_BL33_BASE */
.next_handoff_image_id = INVALID_IMAGE_ID,
diff --git a/plat/imx/imx7/warp7/aarch32/warp7_helpers.S b/plat/imx/imx7/common/imx7_helpers.S
similarity index 82%
rename from plat/imx/imx7/warp7/aarch32/warp7_helpers.S
rename to plat/imx/imx7/common/imx7_helpers.S
index 3695b32..661fd29 100644
--- a/plat/imx/imx7/warp7/aarch32/warp7_helpers.S
+++ b/plat/imx/imx7/common/imx7_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ * Copyright (c) Linaro 2018-2019 Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -35,14 +35,14 @@
endfunc plat_get_my_entrypoint
func plat_crash_console_init
- mov_imm r0, PLAT_WARP7_BOOT_UART_BASE
- mov_imm r1, PLAT_WARP7_BOOT_UART_CLK_IN_HZ
- mov_imm r2, PLAT_WARP7_CONSOLE_BAUDRATE
+ mov_imm r0, PLAT_IMX7_BOOT_UART_BASE
+ mov_imm r1, PLAT_IMX7_BOOT_UART_CLK_IN_HZ
+ mov_imm r2, PLAT_IMX7_CONSOLE_BAUDRATE
b imx_crash_uart_init
endfunc plat_crash_console_init
func plat_crash_console_putc
- mov_imm r1, PLAT_WARP7_BOOT_UART_BASE
+ mov_imm r1, PLAT_IMX7_BOOT_UART_BASE
b imx_crash_uart_putc
endfunc plat_crash_console_putc
diff --git a/plat/imx/imx7/warp7/warp7_image_load.c b/plat/imx/imx7/common/imx7_image_load.c
similarity index 100%
rename from plat/imx/imx7/warp7/warp7_image_load.c
rename to plat/imx/imx7/common/imx7_image_load.c
diff --git a/plat/imx/imx7/warp7/warp7_io_storage.c b/plat/imx/imx7/common/imx7_io_storage.c
similarity index 93%
rename from plat/imx/imx7/warp7/warp7_io_storage.c
rename to plat/imx/imx7/common/imx7_io_storage.c
index fcfb503..977181d 100644
--- a/plat/imx/imx7/warp7/warp7_io_storage.c
+++ b/plat/imx/imx7/common/imx7_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,21 +19,21 @@
static const io_dev_connector_t *fip_dev_con;
static uintptr_t fip_dev_handle;
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
static const io_dev_connector_t *mmc_dev_con;
static uintptr_t mmc_dev_handle;
static const io_block_spec_t mmc_fip_spec = {
- .offset = WARP7_FIP_MMC_BASE,
- .length = WARP7_FIP_SIZE
+ .offset = IMX7_FIP_MMC_BASE,
+ .length = IMX7_FIP_SIZE
};
static const io_block_dev_spec_t mmc_dev_spec = {
/* It's used as temp buffer in block driver. */
.buffer = {
- .offset = WARP7_FIP_BASE,
+ .offset = IMX7_FIP_BASE,
/* do we need a new value? */
- .length = WARP7_FIP_SIZE
+ .length = IMX7_FIP_SIZE
},
.ops = {
.read = mmc_read_blocks,
@@ -49,8 +49,8 @@
static uintptr_t memmap_dev_handle;
static const io_block_spec_t fip_block_spec = {
- .offset = WARP7_FIP_BASE,
- .length = WARP7_FIP_SIZE
+ .offset = IMX7_FIP_BASE,
+ .length = IMX7_FIP_SIZE
};
static int open_memmap(const uintptr_t spec);
#endif
@@ -106,7 +106,7 @@
};
static const struct plat_io_policy policies[] = {
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
[FIP_IMAGE_ID] = {
&mmc_dev_handle,
(uintptr_t)&mmc_fip_spec,
@@ -190,7 +190,7 @@
return result;
}
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
static int open_mmc(const uintptr_t spec)
{
int result;
@@ -240,11 +240,11 @@
return result;
}
-void plat_warp7_io_setup(void)
+void plat_imx7_io_setup(void)
{
int result __unused;
-#ifndef WARP7_FIP_MMAP
+#ifndef IMX7_FIP_MMAP
result = register_io_dev_block(&mmc_dev_con);
assert(result == 0);
diff --git a/plat/imx/imx7/common/imx7_rotpk.S b/plat/imx/imx7/common/imx7_rotpk.S
new file mode 100644
index 0000000..8bd53c2
--- /dev/null
+++ b/plat/imx/imx7/common/imx7_rotpk.S
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ .global imx7_rotpk_hash
+ .global imx7_rotpk_hash_end
+imx7_rotpk_hash:
+ /* DER header */
+ .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
+ .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
+ /* SHA256 */
+ .incbin ROTPK_HASH
+imx7_rotpk_hash_end:
diff --git a/plat/imx/imx7/warp7/warp7_trusted_boot.c b/plat/imx/imx7/common/imx7_trusted_boot.c
similarity index 80%
rename from plat/imx/imx7/warp7/warp7_trusted_boot.c
rename to plat/imx/imx7/common/imx7_trusted_boot.c
index 6a00224..cd27128 100644
--- a/plat/imx/imx7/warp7/warp7_trusted_boot.c
+++ b/plat/imx/imx7/common/imx7_trusted_boot.c
@@ -6,13 +6,13 @@
#include <plat/common/platform.h>
-extern char warp7_rotpk_hash[], warp7_rotpk_hash_end[];
+extern char imx7_rotpk_hash[], imx7_rotpk_hash_end[];
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
unsigned int *flags)
{
- *key_ptr = warp7_rotpk_hash;
- *key_len = warp7_rotpk_hash_end - warp7_rotpk_hash;
+ *key_ptr = imx7_rotpk_hash;
+ *key_len = imx7_rotpk_hash_end - imx7_rotpk_hash;
*flags = ROTPK_IS_HASH;
return 0;
diff --git a/plat/imx/imx7/include/imx7_def.h b/plat/imx/imx7/include/imx7_def.h
new file mode 100644
index 0000000..77a8ca3
--- /dev/null
+++ b/plat/imx/imx7/include/imx7_def.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX7_DEF_H
+#define IMX7_DEF_H
+
+#include <stdint.h>
+
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_imx7_io_setup(void);
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
+ u_register_t arg3, u_register_t arg4);
+
+#endif /*IMX7_DEF_H */
diff --git a/plat/imx/imx7/picopi/include/platform_def.h b/plat/imx/imx7/picopi/include/platform_def.h
new file mode 100644
index 0000000..1af1d0c
--- /dev/null
+++ b/plat/imx/imx7/picopi/include/platform_def.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <plat/common/common_def.h>
+
+#define PLATFORM_STACK_SIZE 0x1000
+
+#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
+#define PLATFORM_CLUSTER_COUNT 1
+#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
+
+#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
+
+#define PICOPI_PRIMARY_CPU 0
+
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
+
+#define PLAT_MAX_RET_STATE 1
+#define PLAT_MAX_OFF_STATE 2
+
+/* Local power state for power domains in Run state. */
+#define PLAT_LOCAL_STATE_RUN 0
+
+/* Local power state for retention. Valid only for CPU power domains */
+#define PLAT_LOCAL_STATE_RET 1
+
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains.
+ */
+#define PLAT_LOCAL_STATE_OFF 2
+
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ * i.MX7 has a 32 byte cacheline size
+ * i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01/2018 pg 298
+ */
+#define CACHE_WRITEBACK_SHIFT 4
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+/*
+ * Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
+ */
+#define BOOT_ROM_BASE 0x00000000
+#define BOOT_ROM_SIZE 0x00020000
+
+#define OCRAM_S_BASE 0x00180000
+#define OCRAM_S_SIZE 0x00008000
+
+/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
+#define DRAM_BASE 0x80000000
+#define DRAM_SIZE 0x20000000
+#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
+
+/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
+#define IMX7_OPTEE_SIZE 0x02000000
+#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE)
+#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
+
+/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
+#define BL2_RAM_SIZE 0x00100000
+#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE)
+#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
+#define SHARED_RAM_SIZE 0x00001000
+#define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE)
+#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE)
+
+/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
+#define IMX7_UBOOT_SIZE 0x00100000
+#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
+#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
+
+/* Define FIP image absolute location 0x80000000 - 0x80100000 */
+#define IMX7_FIP_SIZE 0x00100000
+#define IMX7_FIP_BASE (DRAM_BASE)
+#define IMX7_FIP_LIMIT (IMX7_FIP_BASE + IMX7_FIP_SIZE)
+
+/* Define FIP image location at 1MB offset */
+#define IMX7_FIP_MMC_BASE (1024 * 1024)
+
+/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
+#define IMX7_DTB_SIZE 0x00100000
+#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
+#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE)
+
+/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
+#define IMX7_DTB_OVERLAY_SIZE 0x00001000
+#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT
+#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \
+ IMX7_DTB_OVERLAY_SIZE)
+/*
+ * BL2 specific defines.
+ *
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
+#define BL2_BASE BL2_RAM_BASE
+#define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
+
+/*
+ * BL3-2/OPTEE
+ */
+# define BL32_BASE IMX7_OPTEE_BASE
+# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
+
+/*
+ * BL3-3/U-BOOT
+ */
+#define BL33_BASE IMX7_UBOOT_BASE
+#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
+
+/*
+ * ATF's view of memory
+ *
+ * 0xa0000000 +-----------------+
+ * | DDR | BL32/OPTEE
+ * 0x9e000000 +-----------------+
+ * | DDR | BL23 ATF
+ * 0x9df00000 +-----------------+
+ * | DDR | Shared MBOX RAM
+ * 0x9de00000 +-----------------+
+ * | DDR | Unallocated
+ * 0x87900000 +-----------------+
+ * | DDR | BL33/U-BOOT
+ * 0x87800000 +-----------------+
+ * | DDR | Unallocated
+ * 0x83100000 +-----------------+
+ * | DDR | DTB
+ * 0x83000000 +-----------------+
+ * | DDR | Unallocated
+ * 0x80100000 +-----------------+
+ * | DDR | FIP
+ * 0x80000000 +-----------------+
+ * | SOC I/0 |
+ * 0x00a00000 +-----------------+
+ * | OCRAM | Not used
+ * 0x00900000 +-----------------+
+ * | SOC I/0 |
+ * 0x00188000 +-----------------+
+ * | OCRAM_S | Not used
+ * 0x00180000 +-----------------+
+ * | SOC I/0 |
+ * 0x00020000 +-----------------+
+ * | BootROM | BL1
+ * 0x00000000 +-----------------+
+ */
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define MAX_MMAP_REGIONS 10
+#define MAX_XLAT_TABLES 6
+#define MAX_IO_DEVICES 2
+#define MAX_IO_HANDLES 3
+#define MAX_IO_BLOCK_DEVICES 1
+
+/* UART defines */
+#define PLAT_IMX7_BOOT_UART_BASE MXC_UART5_BASE
+#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000
+#define PLAT_IMX7_CONSOLE_BAUDRATE 115200
+
+/* MMC defines */
+#ifndef PLAT_PICOPI_SD
+#define PLAT_PICOPI_SD 3
+#endif
+
+#if PLAT_PICOPI_SD == 1
+#define PLAT_PICOPI_BOOT_MMC_BASE USDHC1_BASE
+#endif /* PLAT_PICOPI_SD == 1 */
+
+#if PLAT_PICOPI_SD == 2
+#define PLAT_PICOPI_BOOT_MMC_BASE USDHC2_BASE
+#endif /* PLAT_PICOPI_SD == 2 */
+
+#if PLAT_PICOPI_SD == 3
+#define PLAT_PICOPI_BOOT_MMC_BASE USDHC3_BASE
+#endif /* PLAT_PICOPI_SD == 3 */
+
+/*
+ * System counter
+ */
+#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
new file mode 100644
index 0000000..3cf5c36
--- /dev/null
+++ b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <drivers/mmc.h>
+#include <lib/utils.h>
+
+#include <imx_caam.h>
+#include <imx_clock.h>
+#include <imx_io_mux.h>
+#include <imx_uart.h>
+#include <imx_usdhc.h>
+#include <imx7_def.h>
+
+#define UART5_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M)
+
+#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
+ CCM_TARGET_POST_PODF(2))
+
+#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+ CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
+
+#define PICOPI_UART5_RX_MUX \
+ IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA
+
+#define PICOPI_UART5_TX_MUX \
+ IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA
+
+#define PICOPI_SD3_FEATURES \
+ (IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K | \
+ IOMUXC_SW_PAD_CTL_PAD_SD3_PE | \
+ IOMUXC_SW_PAD_CTL_PAD_SD3_HYS | \
+ IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW | \
+ IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6)
+
+static void picopi_setup_pinmux(void)
+{
+ /* Configure UART5 TX */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET,
+ PICOPI_UART5_TX_MUX);
+ /* Configure UART5 RX */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET,
+ PICOPI_UART5_RX_MUX);
+
+ /* Configure USDHC3 */
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET, 0);
+ imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET,
+ IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B);
+
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET,
+ PICOPI_SD3_FEATURES);
+ imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET,
+ PICOPI_SD3_FEATURES);
+}
+
+static void picopi_usdhc_setup(void)
+{
+ imx_usdhc_params_t params;
+ struct mmc_device_info info;
+
+ zeromem(¶ms, sizeof(imx_usdhc_params_t));
+ params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE;
+ params.clk_rate = 25000000;
+ params.bus_width = MMC_BUS_WIDTH_8;
+ info.mmc_dev_type = MMC_IS_EMMC;
+ imx_usdhc_init(¶ms, &info);
+}
+
+static void picopi_setup_usb_clocks(void)
+{
+ uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
+
+ imx_clock_set_usb_clk_root_bits(usb_en_bits);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
+ imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
+}
+
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
+ u_register_t arg3, u_register_t arg4)
+{
+ uint32_t uart5_en_bits = (uint32_t)UART5_CLK_SELECT;
+ uint32_t usdhc_clock_sel = PLAT_PICOPI_SD - 1;
+
+ /* Initialize clocks etc */
+ imx_clock_enable_uart(4, uart5_en_bits);
+ imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
+
+ picopi_setup_usb_clocks();
+
+ /* Setup pin-muxes */
+ picopi_setup_pinmux();
+
+ picopi_usdhc_setup();
+}
diff --git a/plat/imx/imx7/picopi/platform.mk b/plat/imx/imx7/picopi/platform.mk
new file mode 100644
index 0000000..5901001
--- /dev/null
+++ b/plat/imx/imx7/picopi/platform.mk
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Include imx7 common
+include plat/imx/imx7/common/imx7.mk
+
+# Platform
+PLAT_INCLUDES += -Iplat/imx/imx7/picopi/include \
+
+BL2_SOURCES += drivers/imx/usdhc/imx_usdhc.c \
+ plat/imx/imx7/picopi/picopi_bl2_el3_setup.c \
+
+# Build config flags
+# ------------------
+
+ARM_CORTEX_A7 := yes
+WORKAROUND_CVE_2017_5715 := 0
+
+RESET_TO_BL31 := 0
+
+# Non-TF Boot ROM
+BL2_AT_EL3 := 1
+
+# Indicate single-core
+COLD_BOOT_SINGLE_CPU := 1
+
+# Have different sections for code and rodata
+SEPARATE_CODE_AND_RODATA := 1
+
+# Use Coherent memory
+USE_COHERENT_MEM := 1
+
+# Use multi console API
+MULTI_CONSOLE_API := 1
+
+PLAT_PICOPI_UART :=5
+$(eval $(call add_define,PLAT_PICOPI_UART))
diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h
index d58382f..4f71908 100644
--- a/plat/imx/imx7/warp7/include/platform_def.h
+++ b/plat/imx/imx7/warp7/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -74,13 +74,13 @@
#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
-#define WARP7_OPTEE_SIZE 0x02000000
-#define WARP7_OPTEE_BASE (DRAM_LIMIT - WARP7_OPTEE_SIZE)
-#define WARP7_OPTEE_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
+#define IMX7_OPTEE_SIZE 0x02000000
+#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE)
+#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
#define BL2_RAM_SIZE 0x00100000
-#define BL2_RAM_BASE (WARP7_OPTEE_BASE - BL2_RAM_SIZE)
+#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE)
#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
@@ -89,28 +89,28 @@
#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE)
/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
-#define WARP7_UBOOT_SIZE 0x00100000
-#define WARP7_UBOOT_BASE (DRAM_BASE + 0x7800000)
-#define WARP7_UBOOT_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
+#define IMX7_UBOOT_SIZE 0x00100000
+#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
+#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
/* Define FIP image absolute location 0x80000000 - 0x80100000 */
-#define WARP7_FIP_SIZE 0x00100000
-#define WARP7_FIP_BASE (DRAM_BASE)
-#define WARP7_FIP_LIMIT (WARP7_FIP_BASE + WARP7_FIP_SIZE)
+#define IMX7_FIP_SIZE 0x00100000
+#define IMX7_FIP_BASE (DRAM_BASE)
+#define IMX7_FIP_LIMIT (IMX7_FIP_BASE + IMX7_FIP_SIZE)
/* Define FIP image location at 1MB offset */
-#define WARP7_FIP_MMC_BASE (1024 * 1024)
+#define IMX7_FIP_MMC_BASE (1024 * 1024)
/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
-#define WARP7_DTB_SIZE 0x00100000
-#define WARP7_DTB_BASE (DRAM_BASE + 0x03000000)
-#define WARP7_DTB_LIMIT (WARP7_DTB_BASE + WARP7_DTB_SIZE)
+#define IMX7_DTB_SIZE 0x00100000
+#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
+#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE)
/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
-#define WARP7_DTB_OVERLAY_SIZE 0x00001000
-#define WARP7_DTB_OVERLAY_BASE WARP7_DTB_LIMIT
-#define WARP7_DTB_OVERLAY_LIMIT (WARP7_DTB_OVERLAY_BASE + \
- WARP7_DTB_OVERLAY_SIZE)
+#define IMX7_DTB_OVERLAY_SIZE 0x00001000
+#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT
+#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \
+ IMX7_DTB_OVERLAY_SIZE)
/*
* BL2 specific defines.
@@ -124,14 +124,14 @@
/*
* BL3-2/OPTEE
*/
-# define BL32_BASE WARP7_OPTEE_BASE
-# define BL32_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
+# define BL32_BASE IMX7_OPTEE_BASE
+# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
/*
* BL3-3/U-BOOT
*/
-#define BL33_BASE WARP7_UBOOT_BASE
-#define BL33_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
+#define BL33_BASE IMX7_UBOOT_BASE
+#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
/*
* ATF's view of memory
@@ -189,9 +189,9 @@
#error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6"
#endif
-#define PLAT_WARP7_BOOT_UART_BASE PLAT_WARP7_UART_BASE
-#define PLAT_WARP7_BOOT_UART_CLK_IN_HZ 24000000
-#define PLAT_WARP7_CONSOLE_BAUDRATE 115200
+#define PLAT_IMX7_BOOT_UART_BASE PLAT_WARP7_UART_BASE
+#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000
+#define PLAT_IMX7_CONSOLE_BAUDRATE 115200
/* MMC defines */
#ifndef PLAT_WARP7_SD
@@ -211,13 +211,6 @@
#endif /* PLAT_WARP7_SD == 3 */
/*
- * GIC related constants
- */
-#define GICD_BASE 0x31001000
-#define GICC_BASE 0x31002000
-#define GICR_BASE 0
-
-/*
* System counter
*/
#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */
diff --git a/plat/imx/imx7/warp7/platform.mk b/plat/imx/imx7/warp7/platform.mk
index a93f5e0..ea0f001 100644
--- a/plat/imx/imx7/warp7/platform.mk
+++ b/plat/imx/imx7/warp7/platform.mk
@@ -4,106 +4,21 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-# Architecture
-$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
-
-# Tune compiler for Cortex-A7
-ifeq ($(notdir $(CC)),armclang)
- TF_CFLAGS += -mfpu=neon
- ASFLAGS += -mfpu=neon
-else ifneq ($(findstring clang,$(notdir $(CC))),)
- TF_CFLAGS += -mfpu=neon
- ASFLAGS += -mfpu=neon
-else
- TF_CFLAGS += -mfpu=neon
- ASFLAGS += -mfpu=neon
-endif
+# Include imx7 common
+include plat/imx/imx7/common/imx7.mk
# Platform
-PLAT_INCLUDES := -Idrivers/imx/uart \
- -Iplat/imx/common/include/ \
- -Iplat/imx/imx7/warp7/include \
- -Idrivers/imx/timer \
- -Idrivers/imx/usdhc \
- -Iplat/imx/imx7/include
-
-# Translation tables library
-include lib/xlat_tables_v2/xlat_tables.mk
-
-BL2_SOURCES += common/desc_image_load.c \
- drivers/delay_timer/delay_timer.c \
- drivers/mmc/mmc.c \
- drivers/io/io_block.c \
- drivers/io/io_fip.c \
- drivers/io/io_memmap.c \
- drivers/io/io_storage.c \
- drivers/imx/timer/imx_gpt.c \
- drivers/imx/uart/imx_uart.c \
- drivers/imx/uart/imx_crash_uart.S \
- drivers/imx/usdhc/imx_usdhc.c \
- lib/aarch32/arm32_aeabi_divmod.c \
- lib/aarch32/arm32_aeabi_divmod_a32.S \
- lib/cpus/aarch32/cortex_a7.S \
- lib/optee/optee_utils.c \
- plat/imx/common/imx_aips.c \
- plat/imx/common/imx_caam.c \
- plat/imx/common/imx_clock.c \
- plat/imx/common/imx_csu.c \
- plat/imx/common/imx_io_mux.c \
- plat/imx/common/imx_snvs.c \
- plat/imx/common/imx_wdog.c \
- plat/imx/common/imx7_clock.c \
- plat/imx/imx7/warp7/aarch32/warp7_helpers.S \
- plat/imx/imx7/warp7/warp7_bl2_el3_setup.c \
- plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c \
- plat/imx/imx7/warp7/warp7_io_storage.c \
- plat/imx/imx7/warp7/warp7_image_load.c \
- plat/imx/common/aarch32/imx_uart_console.S \
- ${XLAT_TABLES_LIB_SRCS}
-
-ifneq (${TRUSTED_BOARD_BOOT},0)
+PLAT_INCLUDES += -Iplat/imx/imx7/warp7/include
-include drivers/auth/mbedtls/mbedtls_crypto.mk
-include drivers/auth/mbedtls/mbedtls_x509.mk
-
-AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot.c
-
-BL2_SOURCES += ${AUTH_SOURCES} \
- plat/common/tbbr/plat_tbbr.c \
- plat/imx/imx7/warp7/warp7_trusted_boot.c \
- plat/imx/imx7/warp7/warp7_rotpk.S
-
-ROT_KEY = $(BUILD_PLAT)/rot_key.pem
-ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
-
-$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
-$(eval $(call MAKE_LIB_DIRS))
-
-$(BUILD_PLAT)/bl2/warp7_rotpk.o: $(ROTPK_HASH)
-
-certificates: $(ROT_KEY)
-
-$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- @if [ ! -f $(ROT_KEY) ]; then \
- openssl genrsa 2048 > $@ 2>/dev/null; \
- fi
-
-$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
- openssl dgst -sha256 -binary > $@ 2>/dev/null
-endif
+BL2_SOURCES += drivers/imx/usdhc/imx_usdhc.c \
+ plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
# Build config flags
# ------------------
+ARM_CORTEX_A7 := yes
WORKAROUND_CVE_2017_5715 := 0
-# Enable reset to BL31 by default
RESET_TO_BL31 := 0
# Non-TF Boot ROM
@@ -118,28 +33,5 @@
# Use Coherent memory
USE_COHERENT_MEM := 1
-# PLAT_WARP7_UART
PLAT_WARP7_UART :=1
$(eval $(call add_define,PLAT_WARP7_UART))
-
-# Add the build options to pack BLx images and kernel device tree
-# in the FIP if the platform requires.
-ifneq ($(BL2),)
-$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
-endif
-ifneq ($(BL32_EXTRA1),)
-$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
-endif
-ifneq ($(BL32_EXTRA2),)
-$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
-endif
-ifneq ($(HW_CONFIG),)
-$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
-endif
-
-# Verify build config
-# -------------------
-
-ifeq (${ARCH},aarch64)
- $(error Error: AArch64 not supported on i.mx7)
-endif
diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
index 0eedd21..935a411 100644
--- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
+++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,30 +8,17 @@
#include <platform_def.h>
-#include <arch_helpers.h>
-#include <common/bl_common.h>
#include <common/debug.h>
-#include <common/desc_image_load.h>
#include <drivers/console.h>
#include <drivers/mmc.h>
-#include <lib/xlat_tables/xlat_mmu_helpers.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/mmio.h>
-#include <lib/optee_utils.h>
#include <lib/utils.h>
-#include <imx_aips.h>
#include <imx_caam.h>
#include <imx_clock.h>
-#include <imx_csu.h>
-#include <imx_gpt.h>
#include <imx_io_mux.h>
#include <imx_uart.h>
-#include <imx_snvs.h>
#include <imx_usdhc.h>
-#include <imx_wdog.h>
-
-#include "warp7_private.h"
+#include <imx7_def.h>
#define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M)
@@ -43,102 +30,9 @@
CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
CCM_TARGET_POST_PODF(2))
-#define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
- CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
-
#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
-uintptr_t plat_get_ns_image_entrypoint(void)
-{
- return WARP7_UBOOT_BASE;
-}
-
-static uint32_t warp7_get_spsr_for_bl32_entry(void)
-{
- return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
- DISABLE_ALL_EXCEPTIONS);
-}
-
-static uint32_t warp7_get_spsr_for_bl33_entry(void)
-{
- return SPSR_MODE32(MODE32_svc,
- plat_get_ns_image_entrypoint() & 0x1,
- SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
-}
-
-#ifndef AARCH32_SP_OPTEE
-#error "Must build with OPTEE support included"
-#endif
-
-int bl2_plat_handle_post_image_load(unsigned int image_id)
-{
- int err = 0;
- bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
- bl_mem_params_node_t *hw_cfg_mem_params = NULL;
-
- bl_mem_params_node_t *pager_mem_params = NULL;
- bl_mem_params_node_t *paged_mem_params = NULL;
-
- assert(bl_mem_params);
-
- switch (image_id) {
- case BL32_IMAGE_ID:
- pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
- assert(pager_mem_params);
-
- paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
- assert(paged_mem_params);
-
- err = parse_optee_header(&bl_mem_params->ep_info,
- &pager_mem_params->image_info,
- &paged_mem_params->image_info);
- if (err != 0)
- WARN("OPTEE header parse error.\n");
-
- /*
- * When ATF loads the DTB the address of the DTB is passed in
- * arg2, if an hw config image is present use the base address
- * as DTB address an pass it as arg2
- */
- hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
-
- bl_mem_params->ep_info.args.arg0 =
- bl_mem_params->ep_info.args.arg1;
- bl_mem_params->ep_info.args.arg1 = 0;
- if (hw_cfg_mem_params)
- bl_mem_params->ep_info.args.arg2 =
- hw_cfg_mem_params->image_info.image_base;
- else
- bl_mem_params->ep_info.args.arg2 = 0;
- bl_mem_params->ep_info.args.arg3 = 0;
- bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry();
- break;
-
- case BL33_IMAGE_ID:
- /* AArch32 only core: OP-TEE expects NSec EP in register LR */
- pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
- assert(pager_mem_params);
- pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
-
- /* BL33 expects to receive the primary CPU MPID (through r0) */
- bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
- bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry();
- break;
-
- default:
- /* Do nothing in default case */
- break;
- }
-
- return err;
-}
-
-void bl2_el3_plat_arch_setup(void)
-{
- /* Setup the MMU here */
-}
-
#define WARP7_UART1_TX_MUX \
IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA
@@ -215,29 +109,6 @@
imx_usdhc_init(¶ms, &info);
}
-static void warp7_setup_system_counter(void)
-{
- unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
-
- /* Set the frequency table index to our target frequency */
- write_cntfrq(freq);
-
- /* Enable system counter @ frequency table index 0, halt on debug */
- mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
- CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
-}
-
-static void warp7_setup_wdog_clocks(void)
-{
- uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT;
-
- imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
- imx_clock_enable_wdog(0);
- imx_clock_enable_wdog(1);
- imx_clock_enable_wdog(2);
- imx_clock_enable_wdog(3);
-}
-
static void warp7_setup_usb_clocks(void)
{
uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
@@ -248,67 +119,24 @@
imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
}
-/*
- * bl2_el3_early_platform_setup()
- * MMU off
- */
-void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
- u_register_t arg3, u_register_t arg4)
+
+void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
+ u_register_t arg3, u_register_t arg4)
{
uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT;
uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT;
uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1;
- static console_imx_uart_t console;
- int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME;
- /* Initialize the AIPS */
- imx_aips_init();
- imx_csu_init();
- imx_snvs_init();
- imx_gpt_ops_init(GPT1_BASE_ADDR);
-
- /* Initialize clocks, regulators, pin-muxes etc */
- imx_clock_init();
+ /* Initialize clocks etc */
imx_clock_enable_uart(0, uart1_en_bits);
imx_clock_enable_uart(5, uart6_en_bits);
+
imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
- warp7_setup_system_counter();
- warp7_setup_wdog_clocks();
+
warp7_setup_usb_clocks();
/* Setup pin-muxes */
warp7_setup_pinmux();
- /* Init UART, storage and friends */
- console_imx_uart_register(PLAT_WARP7_BOOT_UART_BASE,
- PLAT_WARP7_BOOT_UART_CLK_IN_HZ,
- PLAT_WARP7_CONSOLE_BAUDRATE,
- &console);
- console_set_scope(&console.console, console_scope);
-
warp7_usdhc_setup();
-
- /* Open handles to persistent storage */
- plat_warp7_io_setup();
-
- /* Setup higher-level functionality CAAM, RTC etc */
- imx_caam_init();
- imx_wdog_init();
-
- /* Print out the expected memory map */
- VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT);
- VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
- VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
- VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT);
- VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", WARP7_DTB_OVERLAY_BASE, WARP7_DTB_OVERLAY_LIMIT);
- VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT);
- VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT);
-}
-
-/*
- * bl2_platform_setup()
- * MMU on - enabled by bl2_el3_plat_arch_setup()
- */
-void bl2_platform_setup(void)
-{
}
diff --git a/plat/imx/imx7/warp7/warp7_private.h b/plat/imx/imx7/warp7/warp7_private.h
deleted file mode 100644
index cb6d900..0000000
--- a/plat/imx/imx7/warp7/warp7_private.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WARP7_PRIVATE_H
-#define WARP7_PRIVATE_H
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void plat_warp7_io_setup(void);
-
-#endif /* WARP7_PRIVATE_H */
diff --git a/plat/imx/imx7/warp7/warp7_rotpk.S b/plat/imx/imx7/warp7/warp7_rotpk.S
deleted file mode 100644
index f74b6d25b..0000000
--- a/plat/imx/imx7/warp7/warp7_rotpk.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
- .global warp7_rotpk_hash
- .global warp7_rotpk_hash_end
-warp7_rotpk_hash:
- /* DER header */
- .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
- .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
- /* SHA256 */
- .incbin ROTPK_HASH
-warp7_rotpk_hash_end:
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 03fba8a..c8765e8 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -97,7 +97,7 @@
const mmap_region_t plat_agilex_mmap[] = {
MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
- MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
MT_NON_CACHEABLE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index 21a3708..fcc4620 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -111,16 +111,21 @@
}
const mmap_region_t plat_stratix10_mmap[] = {
- MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
- MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
- MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
+ MT_MEMORY | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
+ MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
MT_NON_CACHEABLE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
- MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
- {0},
+ MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
+ MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
+ MT_DEVICE | MT_RW | MT_NS),
+ {0}
};
/*******************************************************************************
@@ -142,7 +147,7 @@
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE),
#endif
- {0},
+ {0}
};
setup_page_tables(bl_regions, plat_stratix10_mmap);
diff --git a/plat/layerscape/common/include/ls_16550.h b/plat/layerscape/common/include/ls_16550.h
index b0b1856..cb4514f 100644
--- a/plat/layerscape/common/include/ls_16550.h
+++ b/plat/layerscape/common/include/ls_16550.h
@@ -63,7 +63,7 @@
#define CONSOLE_T_16550_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -81,6 +81,6 @@
int console_ls_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_ls_16550_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* LS_16550_H */
diff --git a/plat/layerscape/common/ls_bl1_setup.c b/plat/layerscape/common/ls_bl1_setup.c
index 163b35c..fff065e 100644
--- a/plat/layerscape/common/ls_bl1_setup.c
+++ b/plat/layerscape/common/ls_bl1_setup.c
@@ -59,11 +59,11 @@
#endif
);
VERBOSE("After setup the page tables\n");
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el3(0);
-#endif /* AARCH32 */
+#else
+ enable_mmu_svc_mon(0);
+#endif /* __aarch64__ */
VERBOSE("After MMU enabled\n");
}
diff --git a/plat/layerscape/common/ls_bl2_setup.c b/plat/layerscape/common/ls_bl2_setup.c
index 192eaec..35f42e1 100644
--- a/plat/layerscape/common/ls_bl2_setup.c
+++ b/plat/layerscape/common/ls_bl2_setup.c
@@ -54,10 +54,10 @@
#endif
);
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el1(0);
+#else
+ enable_mmu_svc_mon(0);
#endif
}
@@ -74,7 +74,7 @@
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry();
break;
diff --git a/plat/layerscape/common/ls_common.c b/plat/layerscape/common/ls_common.c
index 3b42909..23c0d00 100644
--- a/plat/layerscape/common/ls_common.c
+++ b/plat/layerscape/common/ls_common.c
@@ -143,7 +143,7 @@
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t ls_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
@@ -181,7 +181,7 @@
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
/*******************************************************************************
* Returns Layerscape platform specific memory map regions.
diff --git a/plat/marvell/a3700/common/a3700_common.mk b/plat/marvell/a3700/common/a3700_common.mk
index 64cd433..1e27567 100644
--- a/plat/marvell/a3700/common/a3700_common.mk
+++ b/plat/marvell/a3700/common/a3700_common.mk
@@ -13,6 +13,7 @@
PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common
MARVELL_DRV_BASE := drivers/marvell
MARVELL_COMMON_BASE := $(MARVELL_PLAT_BASE)/common
+HANDLE_EA_EL3_FIRST := 1
include $(MARVELL_PLAT_BASE)/marvell.mk
@@ -107,6 +108,7 @@
$(PLAT_COMMON_BASE)/dram_win.c \
$(PLAT_COMMON_BASE)/io_addr_dec.c \
$(PLAT_COMMON_BASE)/marvell_plat_config.c \
+ $(PLAT_COMMON_BASE)/a3700_ea.c \
$(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \
$(MARVELL_COMMON_BASE)/marvell_ddr_info.c \
$(MARVELL_COMMON_BASE)/marvell_gicv3.c \
diff --git a/plat/marvell/a3700/common/a3700_ea.c b/plat/marvell/a3700/common/a3700_ea.c
new file mode 100644
index 0000000..dd46beb
--- /dev/null
+++ b/plat/marvell/a3700/common/a3700_ea.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2019 Repk repk@triplefau.lt
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <arch_helpers.h>
+
+#define ADVK_SERROR_SYNDROME 0xbf000002
+
+void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
+ void *handle, uint64_t flags)
+{
+ if (syndrome != ADVK_SERROR_SYNDROME) {
+ ERROR("Unhandled External Abort received on 0x%lx at EL3!\n",
+ read_mpidr_el1());
+ ERROR(" exception reason=%u syndrome=0x%llx\n", ea_reason,
+ syndrome);
+ panic();
+ }
+}
diff --git a/plat/marvell/a3700/common/include/platform_def.h b/plat/marvell/a3700/common/include/platform_def.h
index 16865c4..591f045 100644
--- a/plat/marvell/a3700/common/include/platform_def.h
+++ b/plat/marvell/a3700/common/include/platform_def.h
@@ -8,9 +8,9 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdio.h>
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#include <board_marvell_def.h>
#include <mvebu_def.h>
diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h
index 3f6154e..b9c2e0e 100644
--- a/plat/marvell/a8k/common/include/platform_def.h
+++ b/plat/marvell/a8k/common/include/platform_def.h
@@ -8,9 +8,9 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdio.h>
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#include <common/interrupt_props.h>
#include <drivers/arm/gic_common.h>
diff --git a/plat/marvell/common/aarch64/marvell_common.c b/plat/marvell/common/aarch64/marvell_common.c
index ea0902c..21a62d4 100644
--- a/plat/marvell/common/aarch64/marvell_common.c
+++ b/plat/marvell/common/aarch64/marvell_common.c
@@ -13,7 +13,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat_marvell.h>
diff --git a/plat/marvell/common/marvell_common.mk b/plat/marvell/common/marvell_common.mk
index 5c8e804..f41d7a4 100644
--- a/plat/marvell/common/marvell_common.mk
+++ b/plat/marvell/common/marvell_common.mk
@@ -20,12 +20,13 @@
LLC_ENABLE := 1
$(eval $(call add_define,LLC_ENABLE))
+include lib/xlat_tables_v2/xlat_tables.mk
+
PLAT_INCLUDES += -I$(MARVELL_PLAT_INCLUDE_BASE)/common \
-I$(MARVELL_PLAT_INCLUDE_BASE)/common/aarch64
-PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
- lib/xlat_tables/aarch64/xlat_tables.c \
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \
$(MARVELL_PLAT_BASE)/common/aarch64/marvell_common.c \
$(MARVELL_PLAT_BASE)/common/aarch64/marvell_helpers.S \
$(MARVELL_COMMON_BASE)/marvell_console.c
diff --git a/plat/mediatek/mt8183/drivers/mcsi/mcsi.h b/plat/mediatek/mt8183/drivers/mcsi/mcsi.h
index 8a588bf..863e7da 100644
--- a/plat/mediatek/mt8183/drivers/mcsi/mcsi.h
+++ b/plat/mediatek/mt8183/drivers/mcsi/mcsi.h
@@ -85,7 +85,7 @@
#define CCI_CLK_CTRL (MCUCFG_BASE + 0x660)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <plat/common/common_def.h>
#include <stdint.h>
@@ -112,5 +112,5 @@
void cci_init_sf(void);
unsigned long cci_reg_access(unsigned int op, unsigned long offset, unsigned long val);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* MCSI_H */
diff --git a/plat/meson/gxl/gxl_bl31_setup.c b/plat/meson/gxl/gxl_bl31_setup.c
index f8ce660..b1da794 100644
--- a/plat/meson/gxl/gxl_bl31_setup.c
+++ b/plat/meson/gxl/gxl_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#include <common/interrupt_props.h>
#include <plat/common/platform.h>
#include <platform_def.h>
+#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include "gxl_private.h"
@@ -100,12 +101,19 @@
enable_mmu_el3(0);
}
+static inline bool gxl_scp_ready(void)
+{
+ return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT));
+}
+
static inline void gxl_scp_boot(void)
{
scpi_upload_scp_fw(bl30_image_info.image_base,
bl30_image_info.image_size, 0);
scpi_upload_scp_fw(bl301_image_info.image_base,
bl301_image_info.image_size, 1);
+ while (!gxl_scp_ready())
+ ;
}
/*******************************************************************************
diff --git a/plat/meson/gxl/gxl_def.h b/plat/meson/gxl/gxl_def.h
index ada2656..089fa8d 100644
--- a/plat/meson/gxl/gxl_def.h
+++ b/plat/meson/gxl/gxl_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -91,6 +91,12 @@
#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C)
+#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C)
+#define GXBB_AO_RTI_SCP_READY_OFF U(0x14)
+#define GXBB_A0_RTI_SCP_READY_MASK U(3)
+#define GXBB_AO_RTI_SCP_IS_READY(v) \
+ ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \
+ GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK)
#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
diff --git a/plat/meson/gxl/gxl_pm.c b/plat/meson/gxl/gxl_pm.c
index d9b69ef..4a5d26e 100644
--- a/plat/meson/gxl/gxl_pm.c
+++ b/plat/meson/gxl/gxl_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,20 +27,29 @@
static uintptr_t gxbb_sec_entrypoint;
static volatile uint32_t gxbb_cpu0_go;
-static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value)
+static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
{
unsigned int core = plat_gxbb_calc_core_pos(mpidr);
uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
mmio_write_64(cpu_mailbox_addr, value);
- flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t));
}
+static void gxl_pm_reset(u_register_t mpidr)
+{
+ unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+ uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8;
+
+ mmio_write_32(cpu_mailbox_addr, 0);
+}
+
static void __dead2 gxbb_system_reset(void)
{
INFO("BL31: PSCI_SYSTEM_RESET\n");
+ u_register_t mpidr = read_mpidr_el1();
uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3);
+ int ret;
NOTICE("BL31: Reboot reason: 0x%x\n", status);
@@ -50,13 +59,15 @@
mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status);
- int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
+ ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
if (ret != 0) {
- ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret);
+ ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret);
panic();
}
+ gxl_pm_reset(mpidr);
+
wfi();
ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n");
@@ -67,14 +78,18 @@
{
INFO("BL31: PSCI_SYSTEM_OFF\n");
- unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
+ u_register_t mpidr = read_mpidr_el1();
+ int ret;
+
+ ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
if (ret != 0) {
- ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret);
+ ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret);
panic();
}
- gxbb_program_mailbox(read_mpidr_el1(), 0);
+ gxl_pm_set_reset_addr(mpidr, 0);
+ gxl_pm_reset(mpidr);
wfi();
@@ -101,7 +116,7 @@
return PSCI_E_SUCCESS;
}
- gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint);
+ gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint);
scpi_set_css_power_state(mpidr,
SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
dmbsy();
@@ -133,10 +148,6 @@
{
u_register_t mpidr = read_mpidr_el1();
unsigned int core = plat_gxbb_calc_core_pos(mpidr);
- uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4);
-
- mmio_write_32(addr, 0xFFFFFFFF);
- flush_dcache_range(addr, sizeof(uint32_t));
gicv2_cpuif_disable();
@@ -151,7 +162,8 @@
static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
*target_state)
{
- unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+ u_register_t mpidr = read_mpidr_el1();
+ unsigned int core = plat_gxbb_calc_core_pos(mpidr);
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
if (core == GXBB_PRIMARY_CPU) {
@@ -162,10 +174,19 @@
VERBOSE("BL31: CPU0 resumed.\n");
- write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT);
+ /*
+ * Because setting CPU0's warm reset entrypoint through PSCI
+ * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem
+ * to work, jump to it manually.
+ * In order to avoid an assert, mmu has to be disabled.
+ */
+ disable_mmu_el3();
+ ((void(*)(void))gxbb_sec_entrypoint)();
}
dsbsy();
+ gxl_pm_set_reset_addr(mpidr, 0);
+ gxl_pm_reset(mpidr);
for (;;)
wfi();
diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index 9cbadd3..a4085e2 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -9,7 +9,7 @@
#include <tegra_def.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <lib/mmio.h>
#include <stdint.h>
@@ -173,6 +173,6 @@
******************************************************************************/
void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* MEMCTRL_V2_H */
diff --git a/plat/nvidia/tegra/include/tegra_platform.h b/plat/nvidia/tegra/include/tegra_platform.h
index b9c3782..d83ce48 100644
--- a/plat/nvidia/tegra/include/tegra_platform.h
+++ b/plat/nvidia/tegra/include/tegra_platform.h
@@ -30,7 +30,7 @@
#define TEGRA_CHIPID_TEGRA21 U(0x21)
#define TEGRA_CHIPID_TEGRA18 U(0x18)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/*
* Tegra chip ID major/minor identifiers
@@ -57,6 +57,6 @@
bool tegra_platform_is_unit_fpga(void);
bool tegra_platform_is_virt_dev_kit(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TEGRA_PLATFORM_H */
diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c
index b582151..67f3327 100644
--- a/plat/qemu/qemu_bl1_setup.c
+++ b/plat/qemu/qemu_bl1_setup.c
@@ -41,10 +41,10 @@
* does basic initialization. Later architectural setup (bl1_arch_setup())
* does not do anything platform specific.
*****************************************************************************/
-#ifdef AARCH32
-#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
-#else
+#ifdef __aarch64__
#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
#endif
void bl1_plat_arch_setup(void)
diff --git a/plat/qemu/qemu_bl2_mem_params_desc.c b/plat/qemu/qemu_bl2_mem_params_desc.c
index ba6a4db..a01f2dc 100644
--- a/plat/qemu/qemu_bl2_mem_params_desc.c
+++ b/plat/qemu/qemu_bl2_mem_params_desc.c
@@ -35,7 +35,7 @@
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#else /* EL3_PAYLOAD_BASE */
-#ifdef AARCH64
+#ifdef __aarch64__
/* Fill BL31 related information */
{ .image_id = BL31_IMAGE_ID,
@@ -59,10 +59,10 @@
.next_handoff_image_id = BL33_IMAGE_ID,
# endif
},
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
# ifdef QEMU_LOAD_BL32
-#ifdef AARCH64
+#ifdef __aarch64__
#define BL32_EP_ATTRIBS (SECURE | EXECUTABLE)
#define BL32_IMG_ATTRIBS 0
#else
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index b8ca895..4c97c8d 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -81,10 +81,10 @@
/* TODO Initialize timer */
}
-#ifdef AARCH32
-#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
-#else
+#ifdef __aarch64__
#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
#endif
void bl2_plat_arch_setup(void)
@@ -101,7 +101,7 @@
******************************************************************************/
static uint32_t qemu_get_spsr_for_bl32_entry(void)
{
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL3-2 image.
@@ -119,7 +119,7 @@
static uint32_t qemu_get_spsr_for_bl33_entry(void)
{
uint32_t spsr;
-#ifdef AARCH64
+#ifdef __aarch64__
unsigned int mode;
/* Figure out what mode we enter the non-secure world in */
diff --git a/plat/qemu/qemu_common.c b/plat/qemu/qemu_common.c
index aee8321..56bf953 100644
--- a/plat/qemu/qemu_common.c
+++ b/plat/qemu/qemu_common.c
@@ -132,11 +132,11 @@
}
/* Define EL1 and EL3 variants of the function initialising the MMU */
-#ifdef AARCH32
-DEFINE_CONFIGURE_MMU_EL(svc_mon)
-#else
+#ifdef __aarch64__
DEFINE_CONFIGURE_MMU_EL(el1)
DEFINE_CONFIGURE_MMU_EL(el3)
+#else
+DEFINE_CONFIGURE_MMU_EL(svc_mon)
#endif
diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h
index bbe4a54..b7f0ca1 100644
--- a/plat/renesas/rcar/include/platform_def.h
+++ b/plat/renesas/rcar/include/platform_def.h
@@ -7,7 +7,7 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdlib.h>
#endif
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 66b6185..714a8bf 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -7,7 +7,7 @@
#ifndef PLAT_PRIVATE_H
#define PLAT_PRIVATE_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -60,16 +60,7 @@
/******************************************************************************
* Function and variable prototypes
*****************************************************************************/
-#ifdef AARCH32
-void plat_configure_mmu_svc_mon(unsigned long total_base,
- unsigned long total_size,
- unsigned long,
- unsigned long,
- unsigned long,
- unsigned long);
-
-void rockchip_plat_mmu_svc_mon(void);
-#else
+#ifdef __aarch64__
void plat_configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long,
@@ -78,6 +69,15 @@
unsigned long);
void rockchip_plat_mmu_el3(void);
+#else
+void plat_configure_mmu_svc_mon(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long,
+ unsigned long,
+ unsigned long,
+ unsigned long);
+
+void rockchip_plat_mmu_svc_mon(void);
#endif
void plat_cci_init(void);
@@ -140,7 +140,7 @@
uint32_t rockchip_get_uart_base(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/******************************************************************************
* cpu up status
diff --git a/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h
index b22ddc2..34af29a 100644
--- a/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h
+++ b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h
@@ -26,7 +26,7 @@
#define PM_WARM_BOOT_SHT 0
#define PM_WARM_BOOT_BIT (1 << PM_WARM_BOOT_SHT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct psram_data_t {
uint64_t sp;
@@ -50,6 +50,6 @@
extern void *sys_sleep_flag_sram;
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif
diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c
index a5ed766..0a2515d 100644
--- a/plat/rockchip/px30/drivers/pmu/pmu.c
+++ b/plat/rockchip/px30/drivers/pmu/pmu.c
@@ -626,13 +626,13 @@
/* select pvtm as 32k source */
mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0),
- BITS_WITH_WMASK(1, 0x3, 14));
+ BITS_WITH_WMASK(1, 0x3U, 14));
}
static void pvtm_32k_config_restore(void)
{
mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0),
- ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3, 14));
+ ddr_data.pmu_cru_clksel_con0 | BITS_WMSK(0x3U, 14));
mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,
WITH_16BITS_WMSK(ddr_data.pgrf_pvtm_con[0]));
@@ -869,7 +869,7 @@
static inline void pll_pwr_ctr(uint32_t pll_base, uint32_t pll_id, uint32_t pd)
{
mmio_write_32(pll_base + PLL_CON(1),
- BITS_WITH_WMASK(1, 1, 15));
+ BITS_WITH_WMASK(1, 1U, 15));
if (pd)
mmio_write_32(pll_base + PLL_CON(1),
BITS_WITH_WMASK(1, 1, 14));
diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk
index e947682..ee85cd3 100644
--- a/plat/rockchip/px30/platform.mk
+++ b/plat/rockchip/px30/platform.mk
@@ -30,11 +30,13 @@
plat/common/aarch64/crash_console_helpers.S \
${RK_PLAT}/common/rockchip_gicv2.c
-PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
+PLAT_BL_COMMON_SOURCES := lib/bl_aux_params/bl_aux_params.c \
+ lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
plat/common/plat_psci_common.c
BL31_SOURCES += ${RK_GIC_SOURCES} \
+ common/desc_image_load.c \
drivers/arm/cci/cci.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c
index bf78a14..440e6aa 100644
--- a/plat/socionext/uniphier/uniphier_bl31_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl31_setup.c
@@ -35,7 +35,7 @@
{
void *from_bl2;
- from_bl2 = (void *) arg0;
+ from_bl2 = (void *)arg0;
bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
@@ -76,7 +76,7 @@
/* Enable and initialize the System level generic timer */
mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
- CNTCR_FCREQ(0U) | CNTCR_EN);
+ CNTCR_FCREQ(0U) | CNTCR_EN);
}
void bl31_plat_arch_setup(void)
diff --git a/plat/socionext/uniphier/uniphier_gicv3.c b/plat/socionext/uniphier/uniphier_gicv3.c
index 5148e8f..266efe7 100644
--- a/plat/socionext/uniphier/uniphier_gicv3.c
+++ b/plat/socionext/uniphier/uniphier_gicv3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,34 +21,34 @@
/* SGI0 */
INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI6 */
INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* G1S interrupts */
/* Timer */
INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_LEVEL),
+ GIC_INTR_CFG_LEVEL),
/* SGI1 */
INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI2 */
INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI3 */
INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI4 */
INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI5 */
INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI7 */
INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE)
+ GIC_INTR_CFG_EDGE)
};
static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c
index 451e84f..b456bc5 100644
--- a/plat/socionext/uniphier/uniphier_io_storage.c
+++ b/plat/socionext/uniphier/uniphier_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -331,7 +331,7 @@
assert(image_id < ARRAY_SIZE(uniphier_io_policies));
- *dev_handle = *(uniphier_io_policies[image_id].dev_handle);
+ *dev_handle = *uniphier_io_policies[image_id].dev_handle;
*image_spec = uniphier_io_policies[image_id].image_spec;
init_params = uniphier_io_policies[image_id].init_params;
diff --git a/plat/socionext/uniphier/uniphier_nand.c b/plat/socionext/uniphier/uniphier_nand.c
index 271aa0f..27e10e4 100644
--- a/plat/socionext/uniphier/uniphier_nand.c
+++ b/plat/socionext/uniphier/uniphier_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,8 +16,6 @@
#include "uniphier.h"
-#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-
#define NAND_CMD_READ0 0
#define NAND_CMD_READSTART 0x30
@@ -166,7 +164,7 @@
int pages_per_block = nand->pages_per_block;
int page_size = nand->page_size;
int blocks_to_skip = lba / pages_per_block;
- int pages_to_read = DIV_ROUND_UP(size, page_size);
+ int pages_to_read = div_round_up(size, page_size);
int page = lba % pages_per_block;
int block = 0;
uintptr_t p = buf;
diff --git a/plat/socionext/uniphier/uniphier_psci.c b/plat/socionext/uniphier/uniphier_psci.c
index ce11aa7..464252d 100644
--- a/plat/socionext/uniphier/uniphier_psci.c
+++ b/plat/socionext/uniphier/uniphier_psci.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,9 +14,9 @@
#define UNIPHIER_ROM_RSV0 0x59801200
#define UNIPHIER_SLFRSTSEL 0x61843010
-#define UNIPHIER_SLFRSTSEL_MASK (0x3 << 0)
+#define UNIPHIER_SLFRSTSEL_MASK GENMASK(1, 0)
#define UNIPHIER_SLFRSTCTL 0x61843014
-#define UNIPHIER_SLFRSTCTL_RST (1 << 0)
+#define UNIPHIER_SLFRSTCTL_RST BIT(0)
#define MPIDR_AFFINITY_INVALID ((u_register_t)-1)
@@ -58,7 +58,7 @@
const psci_power_state_t *target_state)
{
/*
- * The Boot ROM cannot distinguish warn and cold resets.
+ * The Boot ROM cannot distinguish warm and cold resets.
* Instead of the CPU reset, fake it.
*/
uniphier_holding_pen_release = MPIDR_AFFINITY_INVALID;
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 94c4c5b..37941aa 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -14,7 +14,7 @@
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <drivers/st/stm32mp1_clk.h>
#include <boot_api.h>
@@ -40,7 +40,7 @@
#endif
/* DDR power initializations */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
enum ddr_type {
STM32MP_DDR3,
STM32MP_LPDDR2,
@@ -254,7 +254,7 @@
#define TAMP_BASE U(0x5C00A000)
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
-#if !(defined(__LINKER__) || defined(__ASSEMBLY__))
+#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
static inline uint32_t tamp_bkpr(uint32_t idx)
{
return TAMP_BKP_REGISTER_BASE + (idx << 2);
diff --git a/services/spd/opteed/opteed_private.h b/services/spd/opteed/opteed_private.h
index 847b9c5..242154f 100644
--- a/services/spd/opteed/opteed_private.h
+++ b/services/spd/opteed/opteed_private.h
@@ -79,7 +79,7 @@
#define OPTEED_C_RT_CTX_SIZE 0x60
#define OPTEED_C_RT_CTX_ENTRIES (OPTEED_C_RT_CTX_SIZE >> DWORD_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -157,6 +157,6 @@
extern optee_context_t opteed_sp_context[OPTEED_CORE_COUNT];
extern uint32_t opteed_rw;
extern struct optee_vectors *optee_vector_table;
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* OPTEED_PRIVATE_H */
diff --git a/services/spd/tlkd/tlkd_private.h b/services/spd/tlkd/tlkd_private.h
index 53f9e20..5d5d0e8 100644
--- a/services/spd/tlkd/tlkd_private.h
+++ b/services/spd/tlkd/tlkd_private.h
@@ -71,7 +71,7 @@
#define TLKD_C_RT_CTX_SIZE 0x60
#define TLKD_C_RT_CTX_ENTRIES (TLKD_C_RT_CTX_SIZE >> DWORD_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -119,6 +119,6 @@
uint64_t pc,
tlk_context_t *tlk_ctx);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* TLKD_PRIVATE_H */
diff --git a/services/spd/tspd/tspd_private.h b/services/spd/tspd/tspd_private.h
index 50f3b87..a81eb21 100644
--- a/services/spd/tspd/tspd_private.h
+++ b/services/spd/tspd/tspd_private.h
@@ -126,7 +126,7 @@
#define TSPD_SP_CTX_SIZE 0x90
#define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -227,6 +227,6 @@
extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT];
extern tsp_vectors_t *tsp_vectors;
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* TSPD_PRIVATE_H */
diff --git a/services/std_svc/sdei/sdei_private.h b/services/std_svc/sdei/sdei_private.h
index 8cc66e7..44a7301 100644
--- a/services/std_svc/sdei/sdei_private.h
+++ b/services/std_svc/sdei/sdei_private.h
@@ -22,7 +22,7 @@
#include <services/sdei.h>
#include <setjmp.h>
-#ifdef AARCH32
+#ifndef __aarch64__
# error SDEI is implemented only for AArch64 systems
#endif
diff --git a/services/std_svc/spm/spm_private.h b/services/std_svc/spm/spm_private.h
index 740fee5..efc91cb 100644
--- a/services/std_svc/spm/spm_private.h
+++ b/services/std_svc/spm/spm_private.h
@@ -32,7 +32,7 @@
/* Value returned by spm_sp_synchronous_entry() when a partition is preempted */
#define SPM_SECURE_PARTITION_PREEMPTED U(0x1234)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -114,6 +114,6 @@
int spm_response_get(uint16_t client_id, uint16_t handle, uint32_t token,
u_register_t *x1, u_register_t *x2, u_register_t *x3);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SPM_PRIVATE_H */
diff --git a/services/std_svc/spm_mm/spm_private.h b/services/std_svc/spm_mm/spm_private.h
index 8e94a28..ba94a4d 100644
--- a/services/std_svc/spm_mm/spm_private.h
+++ b/services/std_svc/spm_mm/spm_private.h
@@ -29,7 +29,7 @@
#define SP_C_RT_CTX_SIZE 0x60
#define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -66,6 +66,6 @@
u_register_t pages_count,
u_register_t smc_attributes);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SPM_PRIVATE_H */