Merge pull request #444 from jcastillo-arm/jc/tbb_wdog
Jc/tbb wdog
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index bbc7f1b..2835320 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -130,16 +130,6 @@
mov x21, x0
mov x0, #INTR_ID_UNAVAILABLE
-#if IMF_READ_INTERRUPT_ID
- /*
- * Read the id of the highest priority pending interrupt. If
- * no interrupt is asserted then return to where we came from.
- */
- mov x19, #INTR_ID_UNAVAILABLE
- bl plat_ic_get_pending_interrupt_id
- cmp x19, x0
- b.eq interrupt_exit_\label
-#endif
/* Set the current security state in the 'flags' parameter */
mrs x2, scr_el3
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 04e1542..a31c1f4 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -60,13 +60,6 @@
BL31_LINKERFILE := bl31/bl31.ld.S
-# Flag used by the generic interrupt management framework to determine if
-# upon the assertion of an interrupt, it should pass the interrupt id or not
-IMF_READ_INTERRUPT_ID := 0
-
-$(eval $(call assert_boolean,IMF_READ_INTERRUPT_ID))
-$(eval $(call add_define,IMF_READ_INTERRUPT_ID))
-
# Flag used to inidicate if Crash reporting via console should be included
# in BL3-1. This defaults to being present in DEBUG builds only
ifndef CRASH_REPORTING
diff --git a/docs/interrupt-framework-design.md b/docs/interrupt-framework-design.md
index cee29a3..53707ae 100644
--- a/docs/interrupt-framework-design.md
+++ b/docs/interrupt-framework-design.md
@@ -293,11 +293,9 @@
void *handle,
void *cookie);
-The value of the `id` parameter depends upon the definition of the
-`IMF_READ_INTERRUPT_ID` build time flag. When the flag is defined, `id` contains
-the number of the highest priority pending interrupt of the type that this
-handler was registered for. When the flag is not defined `id` contains
-`INTR_ID_UNAVAILABLE`.
+The `id` is parameter is reserved and could be used in the future for passing
+the interrupt id of the highest pending interrupt only if there is a foolproof
+way of determining the id. Currently it contains `INTR_ID_UNAVAILABLE`.
The `flags` parameter contains miscellaneous information as follows.
@@ -583,11 +581,10 @@
irrecoverable error condition.
6. Calling the registered handler function for the interrupt type generated.
- The firmware also determines the interrupt id if the IMF_READ_INTERRUPT_ID
- build time flag is set. The id is set to `INTR_ID_UNAVAILABLE` if the flag
- is not set. The id along with the current security state and a reference to
- the `cpu_context_t` structure for the current security state are passed to
- the handler function as its arguments.
+ The `id` parameter is set to `INTR_ID_UNAVAILABLE` currently. The id along
+ with the current security state and a reference to the `cpu_context_t`
+ structure for the current security state are passed to the handler function
+ as its arguments.
The handler function returns a reference to the per-cpu `cpu_context_t`
structure for the target security state.
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 6c6122a..e5b4a9c 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -1488,9 +1488,8 @@
Return : uint32_t
This API returns the id of the highest priority pending interrupt at the
-platform IC. The IMF passes the id returned by this API to the registered
-handler for the pending interrupt if the `IMF_READ_INTERRUPT_ID` build time flag
-is set. INTR_ID_UNAVAILABLE is returned when there is no interrupt pending.
+platform IC. INTR_ID_UNAVAILABLE is returned when there is no interrupt
+pending.
ARM standard platforms read the _Highest Priority Pending Interrupt
Register_ (`GICC_HPPIR`) to determine the id of the pending interrupt. The id
diff --git a/docs/user-guide.md b/docs/user-guide.md
index 9f9d0a5..bcdc645 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -251,11 +251,6 @@
is used to determine the number of valid slave interfaces available in the
ARM CCI driver. Default is 400 (that is, CCI-400).
-* `IMF_READ_INTERRUPT_ID`: Boolean flag used by the interrupt management
- framework to enable passing of the interrupt id to its handler. The id is
- read using a platform GIC API. `INTR_ID_UNAVAILABLE` is passed instead if
- this option set to 0. Default is 0.
-
* `RESET_TO_BL31`: Enable BL3-1 entrypoint as the CPU reset vector instead
of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
entrypoint) or 1 (CPU reset to BL3-1 entrypoint).
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 923c333..8682fd1 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -124,7 +124,8 @@
assert(from_bl2 == NULL);
assert(plat_params_from_bl2 == NULL);
- /* Populate entry point information for BL3-2 and BL3-3 */
+#ifdef BL32_BASE
+ /* Populate entry point information for BL3-2 */
SET_PARAM_HEAD(&bl32_image_ep_info,
PARAM_EP,
VERSION_1,
@@ -132,7 +133,9 @@
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+#endif /* BL32_BASE */
+ /* Populate entry point information for BL3-3 */
SET_PARAM_HEAD(&bl33_image_ep_info,
PARAM_EP,
VERSION_1,
@@ -161,10 +164,11 @@
ARM_BL31_PLAT_PARAM_VAL);
/*
- * Copy BL3-2 and BL3-3 entry point information.
+ * Copy BL3-2 (if populated by BL2) and BL3-3 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
- bl32_image_ep_info = *from_bl2->bl32_ep_info;
+ if (from_bl2->bl32_ep_info)
+ bl32_image_ep_info = *from_bl2->bl32_ep_info;
bl33_image_ep_info = *from_bl2->bl33_ep_info;
#endif
}
diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c
index fefc8a7..7796fc4 100644
--- a/services/spd/opteed/opteed_main.c
+++ b/services/spd/opteed/opteed_main.c
@@ -85,11 +85,6 @@
/* Check the security state when the exception was generated */
assert(get_interrupt_src_ss(flags) == NON_SECURE);
-#if IMF_READ_INTERRUPT_ID
- /* Check the security status of the interrupt */
- assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1);
-#endif
-
/* Sanity check the pointer to this cpu's context */
assert(handle == cm_get_context(NON_SECURE));
diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c
index b8b67fa..6223160 100644
--- a/services/spd/tspd/tspd_main.c
+++ b/services/spd/tspd/tspd_main.c
@@ -106,11 +106,6 @@
/* Check the security state when the exception was generated */
assert(get_interrupt_src_ss(flags) == NON_SECURE);
-#if IMF_READ_INTERRUPT_ID
- /* Check the security status of the interrupt */
- assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1);
-#endif
-
/* Sanity check the pointer to this cpu's context */
assert(handle == cm_get_context(NON_SECURE));
@@ -173,10 +168,6 @@
/* Check the security state when the exception was generated */
assert(get_interrupt_src_ss(flags) == SECURE);
-#if IMF_READ_INTERRUPT_ID
- /* Check the security status of the interrupt */
- assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_NS);
-#endif
/*
* Disable the routing of NS interrupts from secure world to EL3 while
* interrupted on this core.