Merge "feat(neoverse): enable NEOVERSE_Nx_EXTERNAL_LLC flag" into integration
diff --git a/Makefile b/Makefile
index 81143e4..a107785 100644
--- a/Makefile
+++ b/Makefile
@@ -308,6 +308,10 @@
# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523
TF_CFLAGS += $(call cc_option, --param=min-pagesize=0)
+ifeq ($(HARDEN_SLS), 1)
+ TF_CFLAGS_aarch64 += $(call cc_option, -mharden-sls=all)
+endif
+
else
# using clang
WARNINGS += -Wshift-overflow -Wshift-sign-overflow \
@@ -1185,6 +1189,7 @@
GENERATE_COT \
GICV2_G0_FOR_EL3 \
HANDLE_EA_EL3_FIRST_NS \
+ HARDEN_SLS \
HW_ASSISTED_COHERENCY \
MEASURED_BOOT \
DRTM_SUPPORT \
diff --git a/changelog.yaml b/changelog.yaml
index 1467ab4..c5e157d 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -569,6 +569,9 @@
- rockchip/rk3399
- rk3399/suspend
+ - title: RK3328
+ scope: rk3328
+
- title: Socionext
scope: socionext
diff --git a/docs/design/auth-framework.rst b/docs/design/auth-framework.rst
index 597f955..281f35f 100644
--- a/docs/design/auth-framework.rst
+++ b/docs/design/auth-framework.rst
@@ -254,8 +254,8 @@
REGISTER_CRYPTO_LIB(_name,
_init,
_verify_signature,
- _calc_hash,
_verify_hash,
+ _calc_hash,
_auth_decrypt,
_convert_pk);
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 599aed9..7ca0300 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -671,6 +671,19 @@
MARCH_DIRECTIVE := -march=armv8.5-a
+- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build
+ options to the compiler currently supporting only of the options.
+ GCC documentation:
+ https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls
+
+ An example usage:
+
+ .. code:: make
+
+ HARDEN_SLS := 1
+
+ This option defaults to 0.
+
- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
specifies a file that contains the Non-Trusted World private key in PEM
format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 3ff0aaf..8829fcb 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -150,6 +150,10 @@
# Enable Handoff protocol using transfer lists
TRANSFER_LIST := 0
+# Enables support for the gcc compiler option "-mharden-sls=all".
+# By default, disables all SLS hardening.
+HARDEN_SLS := 0
+
# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
# The default value is sha256.
HASH_ALG := sha256
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index a01192d..ff7d971 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -77,6 +77,11 @@
#define PLAT_UART1_BASE (0xFFC02100)
/*******************************************************************************
+ * WDT related constants
+ ******************************************************************************/
+#define WDT_BASE (0xFFD00200)
+
+/*******************************************************************************
* GIC related constants
******************************************************************************/
#define PLAT_GIC_BASE (0xFFFC0000)
diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index a2fafd2..3912ba8 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -84,7 +84,8 @@
PLAT_BAUDRATE, &console);
/* Store magic number */
- mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ);
+ // TODO: Temp workaround to ungate testing
+ // mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ);
}
void bl2_el3_plat_arch_setup(void)
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index f637a91..597612f 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -98,6 +98,11 @@
#define PLAT_UART1_BASE (0x10C02100)
/*******************************************************************************
+ * WDT related constants
+ ******************************************************************************/
+#define WDT_BASE (0x10D00200)
+
+/*******************************************************************************
* GIC related constants
******************************************************************************/
#define PLAT_GIC_BASE (0x1D000000)
diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
index da8a8bd..6d8825f 100644
--- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
+++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
@@ -634,8 +634,9 @@
int cad_qspi_read_bank(uint8_t *buffer, uint32_t offset, uint32_t size)
{
int status;
- uint32_t read_count = 0, *read_data;
+ uint32_t read_count = 0;
int level = 1, count = 0, i;
+ uint8_t *read_data;
status = cad_qspi_indirect_read_start_bank(offset, size);
@@ -647,11 +648,11 @@
level = CAD_QSPI_SRAMFILL_INDRDPART(
mmio_read_32(CAD_QSPI_OFFSET +
CAD_QSPI_SRAMFILL));
- read_data = (uint32_t *)(buffer + read_count);
+ read_data = (uint8_t *)(buffer + read_count);
for (i = 0; i < level; ++i)
- *read_data++ = mmio_read_32(CAD_QSPIDATA_OFST);
+ *read_data++ = mmio_read_8(CAD_QSPIDATA_OFST);
- read_count += level * sizeof(uint32_t);
+ read_count += level * sizeof(uint8_t);
count++;
} while (level > 0);
}
diff --git a/plat/intel/soc/common/drivers/wdt/watchdog.h b/plat/intel/soc/common/drivers/wdt/watchdog.h
index 4ee4cff..940ebf3 100644
--- a/plat/intel/soc/common/drivers/wdt/watchdog.h
+++ b/plat/intel/soc/common/drivers/wdt/watchdog.h
@@ -7,11 +7,8 @@
#ifndef CAD_WATCHDOG_H
#define CAD_WATCHDOG_H
-#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
-#define WDT_BASE (0x10D00200)
-#else
-#define WDT_BASE (0xFFD00200)
-#endif
+#include "socfpga_plat_def.h"
+
#define WDT_REG_SIZE_OFFSET (0x4)
#define WDT_MIN_CYCLES (65536)
#define WDT_PERIOD (20)
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index a06bbc4..ae0229f 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -78,6 +78,11 @@
#define PLAT_UART1_BASE (0xFFC02100)
/*******************************************************************************
+ * WDT related constants
+ ******************************************************************************/
+#define WDT_BASE (0xFFD00200)
+
+/*******************************************************************************
* GIC related constants
******************************************************************************/
#define PLAT_GIC_BASE (0xFFFC0000)
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index 03da8d9..112604f 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -76,6 +76,11 @@
#define PLAT_UART1_BASE (0xFFC02100)
/*******************************************************************************
+ * WDT related constants
+ ******************************************************************************/
+#define WDT_BASE (0xFFD00200)
+
+/*******************************************************************************
* GIC related constants
******************************************************************************/
#define PLAT_GIC_BASE (0xFFFC0000)
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 5b4766d..f96e18b 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -65,6 +65,7 @@
# Enable workarounds for selected Cortex-A53 errata
ERRATA_A53_855873 := 1
+ERRATA_A53_1530924 := 1
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
$(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))
diff --git a/plat/xilinx/common/include/plat_fdt.h b/plat/xilinx/common/include/plat_fdt.h
index a1ee1e1..47a678c 100644
--- a/plat/xilinx/common/include/plat_fdt.h
+++ b/plat/xilinx/common/include/plat_fdt.h
@@ -9,4 +9,8 @@
void prepare_dtb(void);
+#if defined(XILINX_OF_BOARD_DTB_ADDR)
+int32_t is_valid_dtb(void *fdt);
+#endif
+
#endif /* PLAT_FDT_H */
diff --git a/plat/xilinx/common/plat_console.c b/plat/xilinx/common/plat_console.c
index 0c0e74b..b84912a 100644
--- a/plat/xilinx/common/plat_console.c
+++ b/plat/xilinx/common/plat_console.c
@@ -18,6 +18,7 @@
#include <drivers/console.h>
#include <libfdt.h>
#include <plat_console.h>
+#include <plat_fdt.h>
#include <platform_def.h>
#include <plat_private.h>
@@ -108,7 +109,7 @@
{
uintptr_t base_addr;
const char *com;
- uint32_t ret = 0;
+ int32_t ret = 0;
com = fdt_getprop(dtb, node, "compatible", NULL);
if (com != NULL) {
@@ -143,16 +144,10 @@
*/
static int fdt_get_uart_info(dt_uart_info_t *info)
{
- int node, ret = 0;
+ int node = 0, ret = 0;
void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
- if (fdt_check_header(dtb) != 0) {
- ERROR("Can't read DT at %p\n", dtb);
- ret = -FDT_ERR_NOTFOUND;
- goto error;
- }
-
- ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE);
+ ret = is_valid_dtb(dtb);
if (ret < 0) {
ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
ret = -FDT_ERR_NOTFOUND;
@@ -183,9 +178,9 @@
*
* Return: On success, it returns 0; on failure, it returns an error+reason.
*/
-static int check_fdt_uart_info(dt_uart_info_t *info)
+static int32_t check_fdt_uart_info(dt_uart_info_t *info)
{
- uint32_t ret = 0;
+ int32_t ret = 0;
if (info->status == 0) {
ret = -ENODEV;
@@ -224,7 +219,7 @@
static void setup_runtime_console(uint32_t clock, dt_uart_info_t *info)
{
static console_t bl31_runtime_console;
- uint32_t rc;
+ int32_t rc;
#if defined(PLAT_zynqmp)
rc = console_cdns_register(info->base,
@@ -265,6 +260,7 @@
rc = fdt_get_uart_info(uart_info);
if (rc < 0) {
rc = -FDT_ERR_NOTFOUND;
+ goto error;
}
if (strncmp(uart_info->compatible, DT_UART_COMPAT,
@@ -288,13 +284,14 @@
WARN("BL31: No console device found in DT.\n");
}
+error:
return rc;
}
#endif
void setup_console(void)
{
- uint32_t rc;
+ int32_t rc;
uint32_t uart_clk = get_uart_clk();
#if defined(PLAT_zynqmp)
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index de5d1a1..ebcc31b 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -13,6 +13,79 @@
#include <plat_fdt.h>
#include <platform_def.h>
+#if defined(XILINX_OF_BOARD_DTB_ADDR)
+
+#define FIT_CONFS_PATH "/configurations"
+
+static uint8_t is_fit_image(void *dtb)
+{
+ int64_t confs_noffset;
+ uint8_t status = 0;
+
+ confs_noffset = fdt_path_offset(dtb, FIT_CONFS_PATH);
+ /*confs_noffset is only present on FIT image */
+ if (confs_noffset < 0) {
+ status = 0;
+ } else {
+ status = 1;
+ }
+
+ return status;
+}
+
+int32_t is_valid_dtb(void *fdt)
+{
+ int32_t ret = 0;
+
+ if (fdt_check_header(fdt) != 0) {
+ ERROR("Can't read DT at %p\n", fdt);
+ ret = -FDT_ERR_NOTFOUND;
+ goto error;
+ }
+
+ ret = fdt_open_into(fdt, fdt, XILINX_OF_BOARD_DTB_MAX_SIZE);
+ if (ret < 0) {
+ ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
+ ret = -FDT_ERR_NOTFOUND;
+ goto error;
+ }
+
+ if (is_fit_image(fdt) != 0U) {
+ WARN("FIT image detected, TF-A will not update DTB for DDR address space\n");
+ ret = -FDT_ERR_NOTFOUND;
+ }
+error:
+ return ret;
+}
+
+static int add_mmap_dynamic_region(unsigned long long base_pa, uintptr_t base_va,
+ size_t size, unsigned int attr)
+{
+ int ret = 0;
+#if defined(PLAT_XLAT_TABLES_DYNAMIC)
+ ret = mmap_add_dynamic_region(base_pa, base_va, size, attr);
+ if (ret != 0) {
+ WARN("Failed to add dynamic region for dtb: error %d\n",
+ ret);
+ }
+#endif
+ return ret;
+}
+
+static int remove_mmap_dynamic_region(uintptr_t base_va, size_t size)
+{
+ int ret = 0;
+#if defined(PLAT_XLAT_TABLES_DYNAMIC)
+ ret = mmap_remove_dynamic_region(base_va, size);
+ if (ret != 0) {
+ WARN("Failed to remove dynamic region for dtb:error %d\n",
+ ret);
+ }
+#endif
+ return ret;
+}
+#endif
+
void prepare_dtb(void)
{
#if defined(XILINX_OF_BOARD_DTB_ADDR)
@@ -24,75 +97,44 @@
if (!IS_TFA_IN_OCM(BL31_BASE)) {
-#if defined(PLAT_XLAT_TABLES_DYNAMIC)
- map_ret = mmap_add_dynamic_region((unsigned long long)dtb,
- (uintptr_t)dtb,
- XILINX_OF_BOARD_DTB_MAX_SIZE,
- MT_MEMORY | MT_RW | MT_NS);
- if (map_ret != 0) {
- WARN("Failed to add dynamic region for dtb: error %d\n",
- map_ret);
- }
-#endif
-
- if (!map_ret) {
+ map_ret = add_mmap_dynamic_region((unsigned long long)dtb,
+ (uintptr_t)dtb,
+ XILINX_OF_BOARD_DTB_MAX_SIZE,
+ MT_MEMORY | MT_RW | MT_NS);
+ if (map_ret == 0) {
/* Return if no device tree is detected */
- if (fdt_check_header(dtb) != 0) {
- NOTICE("Can't read DT at %p\n", dtb);
- } else {
- ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE);
-
- if (ret < 0) {
- ERROR("Invalid Device Tree at %p: error %d\n",
- dtb, ret);
- } else {
-
- if (dt_add_psci_node(dtb)) {
- WARN("Failed to add PSCI Device Tree node\n");
- }
-
- if (dt_add_psci_cpu_enable_methods(dtb)) {
- WARN("Failed to add PSCI cpu enable methods in DT\n");
- }
-
- /* Reserve memory used by Trusted Firmware. */
- ret = fdt_add_reserved_memory(dtb,
- "tf-a",
- BL31_BASE,
- BL31_LIMIT
- -
- BL31_BASE);
- if (ret < 0) {
- WARN("Failed to add reserved memory nodes for BL31 to DT.\n");
- }
-
- ret = fdt_pack(dtb);
- if (ret < 0) {
- WARN("Failed to pack dtb at %p: error %d\n",
- dtb, ret);
- }
- flush_dcache_range((uintptr_t)dtb,
- fdt_blob_size(dtb));
+ if (is_valid_dtb(dtb) == 0) {
+ if (dt_add_psci_node(dtb)) {
+ WARN("Failed to add PSCI Device Tree node\n");
+ }
- INFO("Changed device tree to advertise PSCI and reserved memories.\n");
+ if (dt_add_psci_cpu_enable_methods(dtb)) {
+ WARN("Failed to add PSCI cpu enable methods in DT\n");
+ }
+ /* Reserve memory used by Trusted Firmware. */
+ ret = fdt_add_reserved_memory(dtb, "tf-a",
+ BL31_BASE,
+ BL31_LIMIT - BL31_BASE);
+ if (ret < 0) {
+ WARN("Failed to add reserved memory nodes for BL31 to DT.\n");
}
- }
- }
+ ret = fdt_pack(dtb);
+ if (ret < 0) {
+ WARN("Failed to pack dtb at %p: error %d\n", dtb, ret);
+ }
+ flush_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
+ INFO("Changed device tree to advertise PSCI and reserved memories.\n");
+ }
-#if defined(PLAT_XLAT_TABLES_DYNAMIC)
- if (!map_ret) {
- ret = mmap_remove_dynamic_region((uintptr_t)dtb,
- XILINX_OF_BOARD_DTB_MAX_SIZE);
+ ret = remove_mmap_dynamic_region((uintptr_t)dtb,
+ XILINX_OF_BOARD_DTB_MAX_SIZE);
if (ret != 0) {
- WARN("Failed to remove dynamic region for dtb:error %d\n",
- ret);
+ WARN("Failed to remove mmap dynamic regions.\n");
}
}
-#endif
}
-
#endif
}