Merge changes from topic "jc/cpu_feat" into integration
* changes:
feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKED
feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED
diff --git a/fdts/stm32mp15-ddr3-1x2Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-1x2Gb-1066-binG.dtsi
new file mode 100644
index 0000000..332d1bf
--- /dev/null
+++ b/fdts/stm32mp15-ddr3-1x2Gb-1066-binG.dtsi
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+/*
+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
+ * DDR type: DDR3 / DDR3L
+ * DDR width: 16bits
+ * DDR density: 4Gb
+ * System frequency: 533000Khz
+ * Relaxed Timing Mode: false
+ * Address mapping type: RBC
+ *
+ * Save Date: 2020.02.20, save Time: 18:45:20
+ */
+
+#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
+#define DDR_MEM_SPEED 533000
+#define DDR_MEM_SIZE 0x10000000
+
+#define DDR_MSTR 0x00041401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0040008B
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B1214
+#define DDR_DRAMTMG1 0x000A041C
+#define DDR_DRAMTMG2 0x0608090F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x08040608
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02060105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00000C01
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100C03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100C03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_ADDRMAP1 0x00151515
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x1F000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x03030303
+#define DDR_ADDRMAP6 0x0F0F0303
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022AA5B
+#define DDR_PTR1 0x04841104
+#define DDR_PTR2 0x042DA068
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200011F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x38D488D0
+#define DDR_DTPR1 0x098B00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000840
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000248
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x00000038
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE80
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE80
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
+
+#include "stm32mp15-ddr.dtsi"
diff --git a/fdts/stm32mp151a-prtt1a-fw-config.dts b/fdts/stm32mp151a-prtt1a-fw-config.dts
new file mode 100644
index 0000000..1bbae4e
--- /dev/null
+++ b/fdts/stm32mp151a-prtt1a-fw-config.dts
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2023, Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
+ */
+
+#define DDR_SIZE 0x10000000 /* 256 MB */
+#include "stm32mp15-fw-config.dtsi"
diff --git a/fdts/stm32mp151a-prtt1a.dts b/fdts/stm32mp151a-prtt1a.dts
new file mode 100644
index 0000000..be9bdae
--- /dev/null
+++ b/fdts/stm32mp151a-prtt1a.dts
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023, Protonic Holland - All Rights Reserved
+ * Author: David Jander <david@protonic.nl>
+ */
+/dts-v1/;
+
+#include "stm32mp151.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxad-pinctrl.dtsi"
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-ddr3-1x2Gb-1066-binG.dtsi"
+
+/ {
+ model = "Protonic PRTT1A";
+ compatible = "prt,prtt1a", "st,stm32mp151";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ mmc0 = &sdmmc1;
+ mmc1 = &sdmmc2;
+ serial0 = &uart4;
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xC0000000 0x10000000>;
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+ secure-status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <104000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&qspi_bk1_pins_a {
+ pins1 {
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+};
+
+&rcc {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSI
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pkcs = <
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_DISABLED
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_PLL4P
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_LSI
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_PLL4P
+ CLK_FDCAN_PLL4R
+ CLK_SAI1_PLL3Q
+ CLK_SAI2_PLL3Q
+ CLK_SAI3_PLL3Q
+ CLK_SAI4_PLL3Q
+ CLK_RNG1_LSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSI
+ >;
+
+ /* VCO = 1300.0 MHz => P = 650 (CPU) */
+ pll1: st,pll@0 {
+ compatible = "st,stm32mp1-pll";
+ reg = <0>;
+ cfg = <2 80 0 0 0 PQR(1,0,0)>;
+ frac = <0x800>;
+ };
+
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+ pll2: st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
+ cfg = <2 65 1 0 0 PQR(1,1,1)>;
+ frac = <0x1400>;
+ };
+
+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+ pll3: st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
+ cfg = <1 33 1 16 36 PQR(1,1,1)>;
+ frac = <0x1a04>;
+ };
+
+ /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
+ pll4: st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
+ cfg = <1 39 3 11 4 PQR(1,1,1)>;
+ };
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&sdmmc1_b4_pins_a {
+ pins1 {
+ bias-pull-up;
+ };
+ pins2 {
+ bias-pull-up;
+ };
+};
+
+/* NOTE: Although the PRTT1A does not have an eMMC, we declare it
+ * anyway, in order to be able to use the same binary for the
+ * PRTT1C also. All involved pins are N.C. on PRTT1A/S for that
+ * reason, so it should do no harm. All inputs configured with
+ * pull-ups to avoid floating inputs. */
+&sdmmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&sdmmc2_b4_pins_a {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ };
+};
+
+&sdmmc2_d47_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
+
+&uart4_pins_a {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+};
diff --git a/plat/xilinx/common/include/pm_api_sys.h b/plat/xilinx/common/include/pm_api_sys.h
index e7b1567..baed43d 100644
--- a/plat/xilinx/common/include/pm_api_sys.h
+++ b/plat/xilinx/common/include/pm_api_sys.h
@@ -40,6 +40,7 @@
uint8_t enable, uint32_t flag);
enum pm_ret_status pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag,
uint32_t ack);
+void pm_client_set_wakeup_sources(uint32_t node_id);
enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param,
uint32_t value, uint32_t flag);
enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param,
diff --git a/plat/xilinx/common/include/pm_client.h b/plat/xilinx/common/include/pm_client.h
index eae1d98..8bf4ae3 100644
--- a/plat/xilinx/common/include/pm_client.h
+++ b/plat/xilinx/common/include/pm_client.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,10 @@
void pm_client_abort_suspend(void);
void pm_client_wakeup(const struct pm_proc *proc);
+#if !defined(PLAT_zynqmp)
+enum pm_device_node_idx irq_to_pm_node_idx(uint32_t irq);
+#endif
+
/* Global variables to be set in pm_client.c */
extern const struct pm_proc *primary_proc;
diff --git a/plat/xilinx/common/include/pm_defs.h b/plat/xilinx/common/include/pm_defs.h
index eae1f84..0188443 100644
--- a/plat/xilinx/common/include/pm_defs.h
+++ b/plat/xilinx/common/include/pm_defs.h
@@ -30,9 +30,9 @@
#define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0)
#define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1)
-#define PERIPH_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, \
- XPM_NODESUBCL_DEV_PERIPH, \
- XPM_NODETYPE_DEV_PERIPH, (IDX))
+#define PERIPH_DEVID(IDX) NODEID((uint32_t)XPM_NODECLASS_DEVICE, \
+ (uint32_t)XPM_NODESUBCL_DEV_PERIPH, \
+ (uint32_t)XPM_NODETYPE_DEV_PERIPH, (IDX))
#define PM_GET_CALLBACK_DATA 0xa01U
#define PM_GET_TRUSTZONE_VERSION 0xa03U
@@ -46,13 +46,6 @@
#define PM_LOAD_PDI 0x701U
#define PM_LOAD_GET_HANDOFF_PARAMS 0x70BU
-/* IOCTL IDs for clock driver */
-#define IOCTL_SET_PLL_FRAC_MODE 8U
-#define IOCTL_GET_PLL_FRAC_MODE 9U
-#define IOCTL_SET_PLL_FRAC_DATA 10U
-#define IOCTL_GET_PLL_FRAC_DATA 11U
-#define IOCTL_SET_SGI 25U
-
/* System shutdown macros */
#define XPM_SHUTDOWN_TYPE_SHUTDOWN 0U
#define XPM_SHUTDOWN_TYPE_RESET 1U
@@ -66,6 +59,44 @@
* Enum definitions
********************************************************************/
+//ioctl id
+enum {
+ IOCTL_GET_RPU_OPER_MODE = 0,
+ IOCTL_SET_RPU_OPER_MODE = 1,
+ IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
+ IOCTL_TCM_COMB_CONFIG = 3,
+ IOCTL_SET_TAPDELAY_BYPASS = 4,
+ IOCTL_SET_SGMII_MODE = 5,
+ IOCTL_SD_DLL_RESET = 6,
+ IOCTL_SET_SD_TAPDELAY = 7,
+ /* Ioctl for clock driver */
+ IOCTL_SET_PLL_FRAC_MODE = 8,
+ IOCTL_GET_PLL_FRAC_MODE = 9,
+ IOCTL_SET_PLL_FRAC_DATA = 10,
+ IOCTL_GET_PLL_FRAC_DATA = 11,
+ IOCTL_WRITE_GGS = 12,
+ IOCTL_READ_GGS = 13,
+ IOCTL_WRITE_PGGS = 14,
+ IOCTL_READ_PGGS = 15,
+ /* IOCTL for ULPI reset */
+ IOCTL_ULPI_RESET = 16,
+ /* Set healthy bit value */
+ IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+ IOCTL_AFI = 18,
+ /* Probe counter read/write */
+ IOCTL_PROBE_COUNTER_READ = 19,
+ IOCTL_PROBE_COUNTER_WRITE = 20,
+ IOCTL_OSPI_MUX_SELECT = 21,
+ /* IOCTL for USB power request */
+ IOCTL_USB_SET_STATE = 22,
+ /* IOCTL to get last reset reason */
+ IOCTL_GET_LAST_RESET_REASON = 23,
+ /* AI engine NPI ISR clear */
+ IOCTL_AIE_ISR_CLEAR = 24,
+ /* Register SGI to TF-A */
+ IOCTL_SET_SGI = 25,
+};
+
/**
* @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL
* @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL
diff --git a/plat/xilinx/common/include/pm_node.h b/plat/xilinx/common/include/pm_node.h
index 0d5616c..b6c2d81 100644
--- a/plat/xilinx/common/include/pm_node.h
+++ b/plat/xilinx/common/include/pm_node.h
@@ -18,10 +18,10 @@
#define NODE_SUBCLASS_SHIFT 20U
#define NODE_TYPE_SHIFT 14U
#define NODE_INDEX_SHIFT 0U
-#define NODE_CLASS_MASK_BITS 0x3F
-#define NODE_SUBCLASS_MASK_BITS 0x3F
-#define NODE_TYPE_MASK_BITS 0x3F
-#define NODE_INDEX_MASK_BITS 0x3FFF
+#define NODE_CLASS_MASK_BITS GENMASK_32(5, 0)
+#define NODE_SUBCLASS_MASK_BITS GENMASK_32(5, 0)
+#define NODE_TYPE_MASK_BITS GENMASK_32(5, 0)
+#define NODE_INDEX_MASK_BITS GENMASK_32(13, 0)
#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
#define NODE_SUBCLASS_MASK (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
#define NODE_TYPE_MASK (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
diff --git a/plat/xilinx/common/pm_service/pm_api_sys.c b/plat/xilinx/common/pm_service/pm_api_sys.c
index 6ff61af..c36a0ec 100644
--- a/plat/xilinx/common/pm_service/pm_api_sys.c
+++ b/plat/xilinx/common/pm_service/pm_api_sys.c
@@ -10,14 +10,20 @@
* IPI interrupts
*/
+#include <drivers/arm/gic_common.h>
+#include <lib/mmio.h>
+#include <lib/utils.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <pm_api_sys.h>
+#include <pm_client.h>
#include <pm_common.h>
+#include <pm_defs.h>
#include <pm_ipi.h>
-#include <plat/common/platform.h>
-#include "pm_api_sys.h"
-#include "pm_client.h"
-#include "pm_defs.h"
#include "pm_svc_main.h"
+#define NUM_GICD_ISENABLER ((IRQ_MAX >> 5U) + 1U)
+
/* default shutdown/reboot scope is system(2) */
static uint32_t pm_shutdown_scope = XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM;
@@ -34,6 +40,57 @@
/* PM API functions */
/**
+ * pm_client_set_wakeup_sources - Set all devices with enabled interrupts as
+ * wake sources in the XilPM.
+ * @node_id: Node id of processor
+ */
+void pm_client_set_wakeup_sources(uint32_t node_id)
+{
+ uint32_t reg_num, device_id;
+ uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX] = {0U};
+ uint32_t isenabler1 = PLAT_GICD_BASE_VALUE + GICD_ISENABLER + 4U;
+
+ zeromem(&pm_wakeup_nodes_set, (u_register_t)sizeof(pm_wakeup_nodes_set));
+
+ for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
+ uint32_t base_irq = reg_num << ISENABLER_SHIFT;
+ uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2));
+
+ if (reg == 0U) {
+ continue;
+ }
+
+ while (reg != 0U) {
+ enum pm_device_node_idx node_idx;
+ uint32_t idx, irq, lowest_set = reg & (-reg);
+ enum pm_ret_status ret;
+
+ idx = (uint32_t)__builtin_ctz(lowest_set);
+ irq = base_irq + idx;
+
+ if (irq > IRQ_MAX) {
+ break;
+ }
+
+ node_idx = irq_to_pm_node_idx(irq);
+ reg &= ~lowest_set;
+
+ if (node_idx > XPM_NODEIDX_DEV_MIN) {
+ if (pm_wakeup_nodes_set[node_idx] == 0U) {
+ /* Get device ID from node index */
+ device_id = PERIPH_DEVID((uint32_t)node_idx);
+ ret = pm_set_wakeup_source(node_id,
+ device_id, 1U,
+ SECURE_FLAG);
+ pm_wakeup_nodes_set[node_idx] = (ret == PM_RET_SUCCESS) ?
+ 1U : 0U;
+ }
+ }
+ }
+ }
+}
+
+/**
* pm_handle_eemi_call() - PM call for processor to send eemi payload
* @flag 0 - Call from secure source
* 1 - Call from non-secure source
@@ -404,7 +461,7 @@
PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_QUERY_DATA, qid,
arg1, arg2, arg3);
- ret = pm_feature_check(PM_QUERY_DATA, &version[0], flag);
+ ret = pm_feature_check((uint32_t)PM_QUERY_DATA, &version[0], flag);
if (ret == PM_RET_SUCCESS) {
fw_api_version = version[0] & 0xFFFFU;
if ((fw_api_version == 2U) &&
@@ -458,10 +515,10 @@
ret = pm_pll_get_mode(arg1, value, flag);
break;
case IOCTL_SET_PLL_FRAC_DATA:
- ret = pm_pll_set_param(arg1, PM_PLL_PARAM_DATA, arg2, flag);
+ ret = pm_pll_set_param(arg1, (uint32_t)PM_PLL_PARAM_DATA, arg2, flag);
break;
case IOCTL_GET_PLL_FRAC_DATA:
- ret = pm_pll_get_param(arg1, PM_PLL_PARAM_DATA, value, flag);
+ ret = pm_pll_get_param(arg1, (uint32_t)PM_PLL_PARAM_DATA, value, flag);
break;
case IOCTL_SET_SGI:
/* Get the sgi number */
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index 6fd7f0d..1bd2192 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -168,7 +168,7 @@
switch (api_id) {
- case PM_IOCTL:
+ case (uint32_t)PM_IOCTL:
{
uint32_t value = 0U;
@@ -181,7 +181,7 @@
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
}
- case PM_QUERY_DATA:
+ case (uint32_t)PM_QUERY_DATA:
{
uint32_t data[PAYLOAD_ARG_CNT] = { 0 };
@@ -192,7 +192,7 @@
(uint64_t)data[1] | ((uint64_t)data[2] << 32U));
}
- case PM_FEATURE_CHECK:
+ case (uint32_t)PM_FEATURE_CHECK:
{
uint32_t result[PAYLOAD_ARG_CNT] = {0U};
@@ -230,25 +230,25 @@
switch (api_id) {
- case PM_SELF_SUSPEND:
+ case (uint32_t)PM_SELF_SUSPEND:
ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], security_flag);
SMC_RET1(handle, (u_register_t)ret);
- case PM_FORCE_POWERDOWN:
+ case (uint32_t)PM_FORCE_POWERDOWN:
ret = pm_force_powerdown(pm_arg[0], pm_arg[1], security_flag);
SMC_RET1(handle, (u_register_t)ret);
- case PM_REQ_SUSPEND:
+ case (uint32_t)PM_REQ_SUSPEND:
ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], security_flag);
SMC_RET1(handle, (u_register_t)ret);
- case PM_ABORT_SUSPEND:
+ case (uint32_t)PM_ABORT_SUSPEND:
ret = pm_abort_suspend(pm_arg[0], security_flag);
SMC_RET1(handle, (u_register_t)ret);
- case PM_SYSTEM_SHUTDOWN:
+ case (uint32_t)PM_SYSTEM_SHUTDOWN:
ret = pm_system_shutdown(pm_arg[0], pm_arg[1], security_flag);
SMC_RET1(handle, (u_register_t)ret);
@@ -330,7 +330,7 @@
* receive only 4 words from TF-A. So, this needs to be handled separately
* than other eemi calls.
*/
- if (api_id == PM_QUERY_DATA) {
+ if (api_id == (uint32_t)PM_QUERY_DATA) {
if ((pm_arg[0] == XPM_QID_CLOCK_GET_NAME ||
pm_arg[0] == XPM_QID_PINCTRL_GET_FUNCTION_NAME) &&
ret == PM_RET_SUCCESS) {
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index e47a6b5..bd23bfb 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -102,4 +102,6 @@
INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
+#define IRQ_MAX 142U
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index 7910d8f..ecec405 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -25,8 +25,6 @@
#include "pm_defs.h"
#define UNDEFINED_CPUID (~0)
-#define IRQ_MAX 142U
-#define NUM_GICD_ISENABLER ((IRQ_MAX >> 5U) + 1U)
DEFINE_BAKERY_LOCK(pm_client_secure_lock);
@@ -52,114 +50,83 @@
const struct pm_proc *primary_proc = &pm_procs_all[0];
-/* Interrupt to PM node index map */
-static enum pm_device_node_idx irq_node_map[IRQ_MAX + 1] = {
- [13] = XPM_NODEIDX_DEV_GPIO,
- [14] = XPM_NODEIDX_DEV_I2C_0,
- [15] = XPM_NODEIDX_DEV_I2C_1,
- [16] = XPM_NODEIDX_DEV_SPI_0,
- [17] = XPM_NODEIDX_DEV_SPI_1,
- [18] = XPM_NODEIDX_DEV_UART_0,
- [19] = XPM_NODEIDX_DEV_UART_1,
- [20] = XPM_NODEIDX_DEV_CAN_FD_0,
- [21] = XPM_NODEIDX_DEV_CAN_FD_1,
- [22] = XPM_NODEIDX_DEV_USB_0,
- [23] = XPM_NODEIDX_DEV_USB_0,
- [24] = XPM_NODEIDX_DEV_USB_0,
- [25] = XPM_NODEIDX_DEV_USB_0,
- [26] = XPM_NODEIDX_DEV_USB_0,
- [37] = XPM_NODEIDX_DEV_TTC_0,
- [38] = XPM_NODEIDX_DEV_TTC_0,
- [39] = XPM_NODEIDX_DEV_TTC_0,
- [40] = XPM_NODEIDX_DEV_TTC_1,
- [41] = XPM_NODEIDX_DEV_TTC_1,
- [42] = XPM_NODEIDX_DEV_TTC_1,
- [43] = XPM_NODEIDX_DEV_TTC_2,
- [44] = XPM_NODEIDX_DEV_TTC_2,
- [45] = XPM_NODEIDX_DEV_TTC_2,
- [46] = XPM_NODEIDX_DEV_TTC_3,
- [47] = XPM_NODEIDX_DEV_TTC_3,
- [48] = XPM_NODEIDX_DEV_TTC_3,
- [56] = XPM_NODEIDX_DEV_GEM_0,
- [57] = XPM_NODEIDX_DEV_GEM_0,
- [58] = XPM_NODEIDX_DEV_GEM_1,
- [59] = XPM_NODEIDX_DEV_GEM_1,
- [60] = XPM_NODEIDX_DEV_ADMA_0,
- [61] = XPM_NODEIDX_DEV_ADMA_1,
- [62] = XPM_NODEIDX_DEV_ADMA_2,
- [63] = XPM_NODEIDX_DEV_ADMA_3,
- [64] = XPM_NODEIDX_DEV_ADMA_4,
- [65] = XPM_NODEIDX_DEV_ADMA_5,
- [66] = XPM_NODEIDX_DEV_ADMA_6,
- [67] = XPM_NODEIDX_DEV_ADMA_7,
- [74] = XPM_NODEIDX_DEV_USB_0,
- [126] = XPM_NODEIDX_DEV_SDIO_0,
- [127] = XPM_NODEIDX_DEV_SDIO_0,
- [128] = XPM_NODEIDX_DEV_SDIO_1,
- [129] = XPM_NODEIDX_DEV_SDIO_1,
- [142] = XPM_NODEIDX_DEV_RTC,
-};
-
/**
* irq_to_pm_node_idx - Get PM node index corresponding to the interrupt number
* @irq: Interrupt number
*
* Return: PM node index corresponding to the specified interrupt
*/
-static enum pm_device_node_idx irq_to_pm_node_idx(uint32_t irq)
-{
- assert(irq <= IRQ_MAX);
- return irq_node_map[irq];
-}
-
-/**
- * pm_client_set_wakeup_sources - Set all devices with enabled interrupts as
- * wake sources in the LibPM.
- * @node_id: Node id of processor
- */
-static void pm_client_set_wakeup_sources(uint32_t node_id)
+enum pm_device_node_idx irq_to_pm_node_idx(uint32_t irq)
{
- uint32_t reg_num;
- uint32_t device_id;
- uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX] = { 0U };
- uintptr_t isenabler1 = PLAT_GICD_BASE_VALUE + GICD_ISENABLER + 4;
+ enum pm_device_node_idx dev_idx = XPM_NODEIDX_DEV_MIN;
- for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
- uint32_t base_irq = reg_num << ISENABLER_SHIFT;
- uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2));
-
- if (reg == 0U) {
- continue;
- }
-
- while (reg != 0U) {
- enum pm_device_node_idx node_idx;
- uint32_t idx, irq, lowest_set = reg & (-reg);
- enum pm_ret_status ret;
-
- idx = __builtin_ctz(lowest_set);
- irq = base_irq + idx;
-
- if (irq > IRQ_MAX) {
- break;
- }
-
- node_idx = irq_to_pm_node_idx(irq);
- reg &= ~lowest_set;
+ assert(irq <= IRQ_MAX);
- if (node_idx > XPM_NODEIDX_DEV_MIN && node_idx < XPM_NODEIDX_DEV_MAX) {
- if (pm_wakeup_nodes_set[node_idx] == 0U) {
- /* Get device ID from node index */
- device_id = PERIPH_DEVID(node_idx);
- ret = pm_set_wakeup_source(node_id,
- device_id, 1,
- SECURE_FLAG);
- pm_wakeup_nodes_set[node_idx] = (ret == PM_RET_SUCCESS) ?
- 1 : 0;
- }
- }
- }
+ switch (irq) {
+ case 13:
+ dev_idx = XPM_NODEIDX_DEV_GPIO;
+ break;
+ case 14:
+ dev_idx = XPM_NODEIDX_DEV_I2C_0;
+ break;
+ case 15:
+ dev_idx = XPM_NODEIDX_DEV_I2C_1;
+ break;
+ case 16:
+ dev_idx = XPM_NODEIDX_DEV_SPI_0;
+ break;
+ case 17:
+ dev_idx = XPM_NODEIDX_DEV_SPI_1;
+ break;
+ case 18:
+ dev_idx = XPM_NODEIDX_DEV_UART_0;
+ break;
+ case 19:
+ dev_idx = XPM_NODEIDX_DEV_UART_1;
+ break;
+ case 20:
+ dev_idx = XPM_NODEIDX_DEV_CAN_FD_0;
+ break;
+ case 21:
+ dev_idx = XPM_NODEIDX_DEV_CAN_FD_1;
+ break;
+ case 22:
+ case 23:
+ case 24:
+ case 25:
+ case 26:
+ dev_idx = XPM_NODEIDX_DEV_USB_0;
+ break;
+ case 37:
+ case 38:
+ case 39:
+ dev_idx = XPM_NODEIDX_DEV_TTC_0;
+ break;
+ case 40:
+ case 41:
+ case 42:
+ dev_idx = XPM_NODEIDX_DEV_TTC_1;
+ break;
+ case 43:
+ case 44:
+ case 45:
+ dev_idx = XPM_NODEIDX_DEV_TTC_2;
+ break;
+ case 46:
+ case 47:
+ case 48:
+ dev_idx = XPM_NODEIDX_DEV_TTC_3;
+ break;
+ case 56:
+ case 57:
+ dev_idx = XPM_NODEIDX_DEV_GEM_0;
+ break;
+ default:
+ dev_idx = XPM_NODEIDX_DEV_MIN;
+ break;
}
+
+ return dev_idx;
}
/**
diff --git a/plat/xilinx/versal_net/include/plat_private.h b/plat/xilinx/versal_net/include/plat_private.h
index fc4a6fd..ca4ed1d 100644
--- a/plat/xilinx/versal_net/include/plat_private.h
+++ b/plat/xilinx/versal_net/include/plat_private.h
@@ -43,6 +43,4 @@
*/
int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler);
-#define IOCTL_OSPI_MUX_SELECT (21U)
-
#endif /* PLAT_PRIVATE_H */
diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index 4ce2cc8..f74cb1e 100644
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -114,4 +114,6 @@
INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
+#define IRQ_MAX 200U
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c
index 328100b..2741d47 100644
--- a/plat/xilinx/versal_net/pm_service/pm_client.c
+++ b/plat/xilinx/versal_net/pm_service/pm_client.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -168,6 +168,133 @@
}
/**
+ * irq_to_pm_node_idx - Get PM node index corresponding to the interrupt number
+ * @irq: Interrupt number
+ *
+ * Return: PM node index corresponding to the specified interrupt
+ */
+enum pm_device_node_idx irq_to_pm_node_idx(uint32_t irq)
+{
+ enum pm_device_node_idx dev_idx = XPM_NODEIDX_DEV_MIN;
+
+ assert(irq <= IRQ_MAX);
+
+ switch (irq) {
+ case 20:
+ dev_idx = XPM_NODEIDX_DEV_GPIO;
+ break;
+ case 21:
+ dev_idx = XPM_NODEIDX_DEV_I2C_0;
+ break;
+ case 22:
+ dev_idx = XPM_NODEIDX_DEV_I2C_1;
+ break;
+ case 23:
+ dev_idx = XPM_NODEIDX_DEV_SPI_0;
+ break;
+ case 24:
+ dev_idx = XPM_NODEIDX_DEV_SPI_1;
+ break;
+ case 25:
+ dev_idx = XPM_NODEIDX_DEV_UART_0;
+ break;
+ case 26:
+ dev_idx = XPM_NODEIDX_DEV_UART_1;
+ break;
+ case 27:
+ dev_idx = XPM_NODEIDX_DEV_CAN_FD_0;
+ break;
+ case 28:
+ dev_idx = XPM_NODEIDX_DEV_CAN_FD_1;
+ break;
+ case 29:
+ case 30:
+ case 31:
+ case 32:
+ case 33:
+ case 98:
+ dev_idx = XPM_NODEIDX_DEV_USB_0;
+ break;
+ case 34:
+ case 35:
+ case 36:
+ case 37:
+ case 38:
+ case 99:
+ dev_idx = XPM_NODEIDX_DEV_USB_1;
+ break;
+ case 39:
+ case 40:
+ dev_idx = XPM_NODEIDX_DEV_GEM_0;
+ break;
+ case 41:
+ case 42:
+ dev_idx = XPM_NODEIDX_DEV_GEM_1;
+ break;
+ case 43:
+ case 44:
+ case 45:
+ dev_idx = XPM_NODEIDX_DEV_TTC_0;
+ break;
+ case 46:
+ case 47:
+ case 48:
+ dev_idx = XPM_NODEIDX_DEV_TTC_1;
+ break;
+ case 49:
+ case 50:
+ case 51:
+ dev_idx = XPM_NODEIDX_DEV_TTC_2;
+ break;
+ case 52:
+ case 53:
+ case 54:
+ dev_idx = XPM_NODEIDX_DEV_TTC_3;
+ break;
+ case 72:
+ dev_idx = XPM_NODEIDX_DEV_ADMA_0;
+ break;
+ case 73:
+ dev_idx = XPM_NODEIDX_DEV_ADMA_1;
+ break;
+ case 74:
+ dev_idx = XPM_NODEIDX_DEV_ADMA_2;
+ break;
+ case 75:
+ dev_idx = XPM_NODEIDX_DEV_ADMA_3;
+ break;
+ case 76:
+ dev_idx = XPM_NODEIDX_DEV_ADMA_4;
+ break;
+ case 77:
+ dev_idx = XPM_NODEIDX_DEV_ADMA_5;
+ break;
+ case 78:
+ dev_idx = XPM_NODEIDX_DEV_ADMA_6;
+ break;
+ case 79:
+ dev_idx = XPM_NODEIDX_DEV_ADMA_7;
+ break;
+ case 184:
+ case 185:
+ dev_idx = XPM_NODEIDX_DEV_SDIO_0;
+ break;
+ case 186:
+ case 187:
+ dev_idx = XPM_NODEIDX_DEV_SDIO_1;
+ break;
+ case 200:
+ dev_idx = XPM_NODEIDX_DEV_RTC;
+ break;
+ default:
+ dev_idx = XPM_NODEIDX_DEV_MIN;
+ break;
+ }
+
+ return dev_idx;
+}
+
+/**
* pm_client_suspend() - Client-specific suspend actions
*
* This function should contain any PU-specific actions
@@ -184,7 +311,9 @@
pm_client_lock_get();
- /* TODO: Set wakeup source */
+ if (state == PM_STATE_SUSPEND_TO_RAM) {
+ pm_client_set_wakeup_sources((uint32_t)proc->node_id);
+ }
val = read_cpu_pwrctrl_val();
val |= CORE_PWRDN_EN_BIT_MASK;
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
index 3b0d6ee..de93b2d 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,44 +14,6 @@
#include "pm_common.h"
-//ioctl id
-enum {
- IOCTL_GET_RPU_OPER_MODE = 0,
- IOCTL_SET_RPU_OPER_MODE = 1,
- IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
- IOCTL_TCM_COMB_CONFIG = 3,
- IOCTL_SET_TAPDELAY_BYPASS = 4,
- IOCTL_SET_SGMII_MODE = 5,
- IOCTL_SD_DLL_RESET = 6,
- IOCTL_SET_SD_TAPDELAY = 7,
- /* Ioctl for clock driver */
- IOCTL_SET_PLL_FRAC_MODE = 8,
- IOCTL_GET_PLL_FRAC_MODE = 9,
- IOCTL_SET_PLL_FRAC_DATA = 10,
- IOCTL_GET_PLL_FRAC_DATA = 11,
- IOCTL_WRITE_GGS = 12,
- IOCTL_READ_GGS = 13,
- IOCTL_WRITE_PGGS = 14,
- IOCTL_READ_PGGS = 15,
- /* IOCTL for ULPI reset */
- IOCTL_ULPI_RESET = 16,
- /* Set healthy bit value */
- IOCTL_SET_BOOT_HEALTH_STATUS = 17,
- IOCTL_AFI = 18,
- /* Probe counter read/write */
- IOCTL_PROBE_COUNTER_READ = 19,
- IOCTL_PROBE_COUNTER_WRITE = 20,
- IOCTL_OSPI_MUX_SELECT = 21,
- /* IOCTL for USB power request */
- IOCTL_USB_SET_STATE = 22,
- /* IOCTL to get last reset reason */
- IOCTL_GET_LAST_RESET_REASON = 23,
- /* AI engine NPI ISR clear */
- IOCTL_AIE_ISR_CLEAR = 24,
- /* Register SGI to ATF */
- IOCTL_REGISTER_SGI = 25,
-};
-
//RPU operation mode
#define PM_RPU_MODE_LOCKSTEP 0U
#define PM_RPU_MODE_SPLIT 1U