fix(cpus): modify the fix for Cortex-A75 erratum 764081
Apply the mitigation only for the revision and variant
mentioned in the SDEN.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN859515/latest
Change-Id: Ifda1f4cb32bdec9a9af29397ddc03bf22a7a87fc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 9115303..152c81f 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -10,6 +10,8 @@
#include <cpuamu.h>
#include <cpu_macros.S>
+.global check_erratum_cortex_a75_764081
+
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 9801245..a4515a9 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <cortex_a520.h>
#include <cortex_x4.h>
+#include <cortex_a75.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -28,3 +29,14 @@
return ERRATA_NOT_APPLIES;
}
#endif
+
+#if ERRATA_A75_764081
+bool errata_a75_764081_applies(void)
+{
+ long rev_var = cpu_get_rev_var();
+ if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
+ return true;
+ }
+ return false;
+}
+#endif /* ERRATA_A75_764081 */
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 218ad11..6210356 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -89,13 +89,13 @@
| SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
}
-#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used then set
* SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
*/
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_elx |= SCTLR_IESB_BIT;
+ }
/* Store the initialised SCTLR_EL1 value in the cpu_context */
write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx);
@@ -1070,14 +1070,16 @@
if ((scr_el3 & SCR_HCE_BIT) != 0U) {
/* Initialize SCTLR_EL2 register with reset value. */
sctlr_el2 = SCTLR_EL2_RES1;
-#if ERRATA_A75_764081
+
/*
* If workaround of errata 764081 for Cortex-A75
* is used then set SCTLR_EL2.IESB to enable
* Implicit Error Synchronization Barrier.
*/
- sctlr_el2 |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_el2 |= SCTLR_IESB_BIT;
+ }
+
write_sctlr_el2(sctlr_el2);
} else {
/*