fix(intel): add HPS remapper to remap base address for SDM
Remap base address for SDM to access DRAM.
Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index 3912ba8..5c15148 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -86,6 +86,11 @@
/* Store magic number */
// TODO: Temp workaround to ungate testing
// mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ);
+
+ if (!intel_mailbox_is_fpga_not_ready()) {
+ socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
+ FPGA2SOC_MASK | F2SDRAM0_MASK);
+ }
}
void bl2_el3_plat_arch_setup(void)
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 9a58cdb..582afc3 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -142,6 +142,8 @@
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7 0x274
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
+#define SOCFPGA_SYSMGR_SDM_BE_AWADDR_REMAP 0x280
+#define SOCFPGA_SYSMGR_SDM_BE_ARADDR_REMAP 0x284
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index 29fbf92..3e44833 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -243,6 +243,10 @@
int intel_mailbox_get_config_status(uint32_t cmd, bool init_done);
int intel_mailbox_is_fpga_not_ready(void);
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+void intel_smmu_hps_remapper_init(uint64_t *mem);
+#endif
+
int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_rsu_update(uint32_t *flash_offset);
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 58a9967..8e279b8 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -229,6 +229,10 @@
request_type = BITSTREAM_AUTH;
}
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ intel_smmu_hps_remapper_init(0U);
+#endif
+
mailbox_clear_response();
mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
@@ -310,6 +314,10 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ intel_smmu_hps_remapper_init(&mem);
+#endif
+
for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
@@ -711,6 +719,24 @@
return INTEL_SIP_SMC_STATUS_OK;
}
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+/* SMMU HPS Remapper */
+void intel_smmu_hps_remapper_init(uint64_t *mem)
+{
+ /* Read out Bit 1 value */
+ uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02);
+
+ if (remap == 0x00) {
+ /* Update DRAM Base address for SDM SMMU */
+ mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE);
+ mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE);
+ *mem = *mem - DRAM_BASE;
+ } else {
+ *mem = *mem - DRAM_BASE;
+ }
+}
+#endif
+
/*
* This function is responsible for handling all SiP calls from the NS world
*/