feat(cpus): support to update External LLC presence in Neoverse V2
The CPUECTLR_EL1.EXTLLC bit indicates that an external last level
cache(LLC) is present in the system. The default value is internal LLC.
Some systems which may have External LLC can enable the External LLC
presece with new build option 'NEOVERSE_Vx_EXTERNAL_LLC'.
Change-Id: I740947f1ef78e31626dc5b96f6d6dc6658d0120f
Signed-off-by: Younghyun Park <younghyunpark@google.com>
diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h
index 39a6607..1171e95 100644
--- a/include/lib/cpus/aarch64/neoverse_v2.h
+++ b/include/lib/cpus/aarch64/neoverse_v2.h
@@ -16,6 +16,7 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
/*******************************************************************************
* CPU Power Control register specific definitions
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index d4b3a96..3179918 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -109,6 +109,11 @@
cpu_reset_func_start neoverse_v2
/* Disable speculative loads */
msr SSBS, xzr
+
+#if NEOVERSE_Vx_EXTERNAL_LLC
+ /* Some systems may have External LLC, core needs to be made aware */
+ sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT
+#endif
cpu_reset_func_end neoverse_v2
errata_report_shim neoverse_v2