diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 001fb04..e8f9a82 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -112,19 +112,19 @@
 #define FPD_MAINCCI_SIZE	0x00100000
 
 /* APU registers and bitfields */
-#define FPD_APU_BASE		0xFD5C0000
-#define FPD_APU_CONFIG_0	(FPD_APU_BASE + 0x20)
-#define FPD_APU_RVBAR_L_0	(FPD_APU_BASE + 0x40)
-#define FPD_APU_RVBAR_H_0	(FPD_APU_BASE + 0x44)
-#define FPD_APU_PWRCTL		(FPD_APU_BASE + 0x90)
+#define FPD_APU_BASE		0xFD5C0000U
+#define FPD_APU_CONFIG_0	(FPD_APU_BASE + 0x20U)
+#define FPD_APU_RVBAR_L_0	(FPD_APU_BASE + 0x40U)
+#define FPD_APU_RVBAR_H_0	(FPD_APU_BASE + 0x44U)
+#define FPD_APU_PWRCTL		(FPD_APU_BASE + 0x90U)
 
-#define FPD_APU_CONFIG_0_VINITHI_SHIFT	8
-#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK	1
-#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK	2
+#define FPD_APU_CONFIG_0_VINITHI_SHIFT	8U
+#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK	1U
+#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK	2U
 
 /* PMC registers and bitfields */
-#define PMC_GLOBAL_BASE			0xF1110000
-#define PMC_GLOBAL_GLOB_GEN_STORAGE4	(PMC_GLOBAL_BASE + 0x40)
+#define PMC_GLOBAL_BASE			0xF1110000U
+#define PMC_GLOBAL_GLOB_GEN_STORAGE4	(PMC_GLOBAL_BASE + 0x40U)
 
 /* IPI registers and bitfields */
 #define IPI0_REG_BASE		0xFF330000