diff --git a/Makefile b/Makefile
index d605ae9..f01a9ae 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
 # Trusted Firmware Version
 #
 VERSION_MAJOR			:= 2
-VERSION_MINOR			:= 2
+VERSION_MINOR			:= 3
 
 # Default goal is build all images
 .DEFAULT_GOAL			:= all
diff --git a/docs/Makefile b/docs/Makefile
index eed3a08..3dd7ebc 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019, ARM Limited. All rights reserved.
+# Copyright (c) 2019-2020, ARM Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -7,7 +7,7 @@
 #
 
 # You can set these variables from the command line.
-SPHINXOPTS    =
+SPHINXOPTS    = -W
 SPHINXBUILD   = sphinx-build
 SPHINXPROJ    = TrustedFirmware-A
 SOURCEDIR     = .
diff --git a/docs/about/features.rst b/docs/about/features.rst
index 3441c5e..7c73952 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -73,6 +73,8 @@
    to be configured at runtime if required by the platform. It also enables
    loading of a hardware configuration (for example, a kernel device tree)
    as part of the FIP, to be passed through the firmware stages.
+   This feature is now incorporated inside the firmware configuration framework
+   (fconf), which is still flagged as experimental.
 
 -  Support for alternative boot flows, for example to support platforms where
    the EL3 Runtime Software is loaded using other firmware or a separate
@@ -86,8 +88,8 @@
    in ROM but is accessed through a jump-table that may be stored
    in read-write memory, allowing for the library code to be patched.
 
--  A prototype implementation of a Secure Partition Manager (SPM) that is based
-   on the SPCI Alpha 1 and SPRT draft specifications.
+-  Support for the Secure Partition Manager Dispatcher (SPMD) component as a
+   new standard service.
 
 -  Support for ARMv8.3 pointer authentication in the normal and secure worlds.
    The use of pointer authentication in the normal world is enabled whenever
@@ -96,8 +98,8 @@
    experimental configuration at this time and requires the
    ``BRANCH_PROTECTION`` option to be set to non-zero.
 
--  Position-Independent Executable (PIE) support. Initially for BL31 only, with
-   further support to be added in a future release.
+-  Position-Independent Executable (PIE) support. Currently for BL2, BL31, and
+   TSP, with further support to be added in a future release.
 
 Still to come
 -------------
@@ -117,11 +119,11 @@
 
 -  Ongoing security hardening, optimization and quality improvements.
 
-.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
 .. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
 .. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
 .. _Trusty Secure OS: https://source.android.com/security/trusty
 
 --------------
 
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 9e55e60..e4fb09d 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -17,8 +17,6 @@
 :G: `sandrine-bailleux-arm`_
 :M: Alexei Fedorov <alexei.fedorov@arm.com>
 :G: `AlexeiFedorov`_
-:M: György Szing <gyorgy.szing@arm.com>
-:G: `gyuri-szing`_
 :M: Manish Pandey <manish.pandey2@arm.com>
 :G: `manish-pandey-arm`_
 :M: Mark Dykes <mark.dykes@arm.com>
@@ -311,7 +309,6 @@
 .. _etienne-lms: https://github.com/etienne-lms
 .. _glneo: https://github.com/glneo
 .. _grandpaul: https://github.com/grandpaul
-.. _gyuri-szing: https://github.com/gyuri-szing
 .. _hzhuang1: https://github.com/hzhuang1
 .. _JackyBai: https://github.com/JackyBai
 .. _jenswi-linaro: https://github.com/jenswi-linaro
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index fb1e39b..f3167fb 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -42,6 +42,8 @@
 +-----------------+---------------------------+------------------------------+
 | v2.3            | 4th week of Apr '20       | 1st week of Apr '20          |
 +-----------------+---------------------------+------------------------------+
+| v2.4            | 4th week of Oct '20       | 1st week of Oct '20          |
++-----------------+---------------------------+------------------------------+
 
 Removal of Deprecated Interfaces
 --------------------------------
@@ -59,9 +61,6 @@
 +--------------------------------+-------------+---------+---------------------------------------------------------+
 | ``__ASSEMBLY__`` macro         | Oct '19     | v2.3    | Deprecated in favor of ``__ASSEMBLER__``                |
 +--------------------------------+-------------+---------+---------------------------------------------------------+
-| Prototype SPCI-based SPM       | Oct '19     | v2.2    | Based on outdated Alpha 1 spec. Will be replaced with   |
-| (services/std_svc/spm)         |             |         | alternative methods of secure partitioning support.     |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
 
 --------------
 
diff --git a/docs/change-log-upcoming.rst b/docs/change-log-upcoming.rst
index f089a5e..03806d9 100644
--- a/docs/change-log-upcoming.rst
+++ b/docs/change-log-upcoming.rst
@@ -7,7 +7,7 @@
 release code freeze.
 
 
-Upcoming Release Version 2.3
+Upcoming Release Version 2.4
 ----------------------------
 
 **Trusted Firmware-A Contributors,
@@ -20,56 +20,35 @@
 ^^^^^^^^^^^^
 
 - Arm Architecture
-   - Add support for Armv8.4-SecEL2 extension through the SPCI defined SPMD/SPMC
-     components.
-   - Build option to support EL2 context save and restore in the secure world
-     (CTX_INCLUDE_EL2_REGS).
    - Example: "Add support for Branch Target Identification (BTI)"
 
 - BL-specific
-   - Enhanced BL2 bootloader flow to load secure partitions based on firmware
-     configuration data (fconf).
+   - Example: "Enhanced BL2 bootloader flow to load secure partitions based
+     on firmware configuration data (fconf)."
 
 - Build System
-   - Add support for documentation build as a target in Makefile
-   - Add ``COT`` build option to select the chain of trust to use when the
-     Trusted Boot feature is enabled (default: ``tbbr``).
-   - Added creation and injection of secure partition packages into the FIP.
-   - Build option to support SPMC component loading and run at S-EL1
-     or S-EL2 (SPMD_SPM_AT_SEL2).
+   - Example: "Modify FVP makefile for CPUs that support both AArch64/32"
 
 - CPU Support
    - Example: "cortex-a55: Workaround for erratum 1221012"
-   - Use Speculation Barrier instruction for v8.5+ cores
 
 - Drivers
    - Example: "console: Allow the console to register multiple times"
 
 - Libraries
    - Example: "Introduce BTI support in Library at ROM (romlib)"
-   - Add Firmware Configuration Framework (fconf).
-   - Add DebugFS functionality
 
 - New Platforms Support
    - Example: "qemu/qemu_sbsa: New platform support added for QEMU SBSA platform"
 
 - Platforms
    - Example: "arm/common: Introduce wrapper functions to setup secure watchdog"
-   - plat/arm: Add support for the new `dualroot` chain of trust.
-   - plat/arm/fvp: Add support for fconf in BL31 and SP_MIN. Populate power
-     domain desciptor dynamically by leveraging fconf APIs.
 
 - PSCI
    - Example: "Adding new optional PSCI hook ``pwr_domain_on_finish_late``"
 
 - Security
    - Example: "UBSAN support and handlers"
-   - Add support for optional firmware encryption feature (experimental).
-   - Introduce a new `dualroot` chain of trust.
-   - aarch32: stop speculative execution past exception returns.
-
-- SPCI
-   - Introduced the SPM Dispatcher (SPMD) component as a new standard service.
 
 - Tools
    - Example: "fiptool: Add support to build fiptool on Windows."
@@ -103,7 +82,6 @@
    - Example: "Refactor SPSR initialisation code"
 
 - Tools
-   - sptool updated to accomodate building secure partition packages.
    - Example: "cert_create: Remove RSA PKCS#1 v1.5 support"
 
 
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 7e072a9..7befba4 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -4,6 +4,534 @@
 This document contains a summary of the new features, changes, fixes and known
 issues in each release of Trusted Firmware-A.
 
+Version 2.3
+-----------
+
+New Features
+^^^^^^^^^^^^
+
+- Arm Architecture
+   - Add support for Armv8.4-SecEL2 extension through the SPCI defined SPMD/SPMC
+     components.
+
+   - Build option to support EL2 context save and restore in the secure world
+     (CTX_INCLUDE_EL2_REGS).
+
+   - Add support for SMCCC v1.2 (introducing the new SMCCC_ARCH_SOC_ID SMC).
+     Note that the support is compliant, but the SVE registers save/restore will
+     be done as part of future S-EL2/SPM development.
+
+- BL-specific
+   - Enhanced BL2 bootloader flow to load secure partitions based on firmware
+     configuration data (fconf).
+
+   - Changes necessary to support SEPARATE_NOBITS_REGION feature
+
+   - TSP and BL2_AT_EL3: Add Position Independent Execution ``PIE`` support
+
+- Build System
+   - Add support for documentation build as a target in Makefile
+
+   - Add ``COT`` build option to select the chain of trust to use when the
+     Trusted Boot feature is enabled (default: ``tbbr``).
+
+   - Added creation and injection of secure partition packages into the FIP.
+
+   - Build option to support SPMC component loading and run at S-EL1
+     or S-EL2 (SPMD_SPM_AT_SEL2).
+
+   - Enable MTE support
+
+   - Enable Link Time Optimization in GCC
+
+   - Enable -Wredundant-decls warning check
+
+   - Makefile: Add support to optionally encrypt BL31 and BL32
+
+   - Add support to pass the nt_fw_config DTB to OP-TEE.
+
+   - Introduce per-BL ``CPPFLAGS``, ``ASFLAGS``, and ``LDFLAGS``
+
+   - build_macros: Add CREATE_SEQ function to generate sequence of numbers
+
+- CPU Support
+   - cortex-a57: Enable higher performance non-cacheable load forwarding
+
+   - Hercules: Workaround for Errata 1688305
+
+   - Klein: Support added for Klein CPU
+
+   - Matterhorn: Support added for Matterhorn CPU
+
+- Drivers
+   - auth: Add ``calc_hash`` function for hash calculation. Used for
+     authentication of images when measured boot is enabled.
+
+   - cryptocell: Add authenticated decryption framework, and support
+     for CryptoCell-713 and CryptoCell-712 RSA 3K
+
+   - gic600: Add support for multichip configuration and Clayton
+   - gicv3: Introduce makefile, Add extended PPI and SPI range,
+     Add support for probing multiple GIC Redistributor frames
+   - gicv4: Add GICv4 extension for GIC driver
+
+   - io: Add an IO abstraction layer to load encrypted firmwares
+
+   - mhu: Derive doorbell base address
+
+   - mtd: Add SPI-NOR, SPI-NAND, SPI-MEM, and raw NAND framework
+
+   - scmi: Allow use of multiple SCMI channels
+
+   - scu: Add a driver for snoop control unit
+
+- Libraries
+   - coreboot: Add memory range parsing and use generic base address
+
+   - compiler_rt: Import popcountdi2.c and popcountsi2.c files,
+     aeabi_ldivmode.S file and dependencies
+
+   - debugFS: Add DebugFS functionality
+
+   - el3_runtime: Add support for enabling S-EL2
+
+   - fconf: Add Firmware Configuration Framework (fconf) (experimental).
+
+   - libc: Add memrchr function
+
+   - locks: bakery: Use is_dcache_enabled() helper and add a DMB to
+     the 'read_cache_op' macro
+
+   - psci: Add support to enable different personality of the same soc.
+
+   - xlat_tables_v2: Add support to pass shareability attribute for
+     normal memory region, use get_current_el_maybe_constant() in
+     is_dcache_enabled(), read-only xlat tables for BL31 memory, and
+     add enable_mmu()
+
+- New Platforms Support
+   - arm/arm_fpga: New platform support added for FPGA
+
+   - arm/rddaniel: New platform support added for rd-daniel platform
+
+   - brcm/stingray: New platform support added for Broadcom stingray platform
+
+   - nvidia/tegra194: New platform support for Nvidia Tegra194 platform
+
+- Platforms
+   - allwinner: Implement PSCI system suspend using SCPI, add a msgbox
+     driver for use with SCPI, and reserve and map space for the SCP firmware
+   - allwinner: axp: Add AXP805 support
+   - allwinner: power: Add DLDO4 power rail
+
+   - amlogic: axg: Add a build flag when using ATOS as BL32 and support for
+     the A113D (AXG) platform
+
+   - arm/a5ds: Add ethernet node and L2 cache node in devicetree
+
+   - arm/common: Add support for the new `dualroot` chain of trust
+   - arm/common: Add support for SEPARATE_NOBITS_REGION
+   - arm/common: Re-enable PIE when RESET_TO_BL31=1
+   - arm/common: Allow boards to specify second DRAM Base address
+     and to define PLAT_ARM_TZC_FILTERS
+
+   - arm/cornstone700: Add support for mhuv2 and stack protector
+
+   - arm/fvp: Add support for fconf in BL31 and SP_MIN. Populate power
+     domain desciptor dynamically by leveraging fconf APIs.
+   - arm/fvp: Add Cactus/Ivy Secure Partition information and use two
+     instances of Cactus at S-EL1
+   - arm/fvp: Add support to run BL32 in TDRAM and BL31 in secure DRAM
+   - arm/fvp: Add support for GICv4 extension and BL2 hash calculation in BL1
+
+   - arm/n1sdp: Setup multichip gic routing table, update platform macros
+     for dual-chip setup, introduce platform information SDS region, add
+     support to update presence of External LLC, and enable the
+     NEOVERSE_N1_EXTERNAL_LLC flag
+
+   - arm/rdn1edge: Add support for dual-chip configuration and use
+     CREATE_SEQ helper macro to compare chip count
+
+   - arm/sgm: Always use SCMI for SGM platforms
+   - arm/sgm775: Add support for dynamic config using fconf
+
+   - arm/sgi: Add multi-chip mode parameter in HW_CONFIG dts, macros for
+     remote chip device region, chip_id and multi_chip_mode to platform
+     variant info, and introduce number of chips macro
+
+   - brcm: Add BL2 and BL31 support common across Broadcom platforms
+   - brcm: Add iproc SPI Nor flash support, spi driver, emmc driver,
+     and support to retrieve plat_toc_flags
+
+   - hisilicon: hikey960: Enable system power off callback
+
+   - intel: Enable bridge access, SiP SMC secure register access, and uboot
+     entrypoint support
+   - intel: Implement platform specific system reset 2
+   - intel: Introduce mailbox response length handling
+
+   - imx: console: Use CONSOLE_T_BASE for UART base address and generic console_t
+     data structure
+   - imx8mm: Provide uart base as build option and add the support for opteed spd
+     on imx8mq/imx8mm
+   - imx8qx: Provide debug uart num as build
+   - imx8qm: Apply clk/pinmux configuration for DEBUG_CONSOLE and provide debug
+     uart num as build param
+
+   - marvell: a8k: Implement platform specific power off and add support
+     for loading MG CM3 images
+
+   - mediatek: mt8183: Add Vmodem/Vcore DVS init level
+
+   - qemu: Support optional encryption of BL31 and BL32 images
+     and ARM_LINUX_KERNEL_AS_BL33 to pass FDT address
+   - qemu: Define ARMV7_SUPPORTS_VFP
+   - qemu: Implement PSCI_CPU_OFF and qemu_system_off via semihosting
+
+   - renesas: rcar_gen3: Add new board revision for M3ULCB
+
+   - rockchip: Enable workaround for erratum 855873, claim a macro to enable
+     hdcp feature for DP, enable power domains of rk3399 before reset, add
+     support for UART3 as serial output, and initialize reset and poweroff
+     GPIOs with known invalid value
+
+   - rpi: Implement PSCI CPU_OFF, use MMIO accessor, autodetect Mini-UART
+     vs. PL011 configuration, and allow using PL011 UART for RPi3/RPi4
+   - rpi3: Include GPIO driver in all BL stages and use same "clock-less"
+     setup scheme as RPi4
+   - rpi3/4: Add support for offlining CPUs
+
+   - st: stm32mp1: platform.mk: Support generating multiple images in one build,
+     migrate to implicit rules, derive map file name from target name, generate
+     linker script with fixed name, and use PHONY for the appropriate targets
+   - st: stm32mp1: Add support for SPI-NOR, raw NAND, and SPI-NAND boot device,
+     QSPI, FMC2 driver
+   - st: stm32mp1: Use stm32mp_get_ddr_ns_size() function, set XN attribute for
+     some areas in BL2, dynamically map DDR later and non-cacheable during its
+     test, add a function to get non-secure DDR size, add DT helper for reg by
+     name, and add compilation flags for boot devices
+
+   - socionext: uniphier: Turn on ENABLE_PIE
+
+   - ti: k3: Add PIE support
+
+   - xilinx: versal: Add set wakeup source, client wakeup, query data, request
+     wakeup, PM_INIT_FINALIZE, PM_GET_TRUSTZONE_VERSION, PM IOCTL, support for
+     suspend related, and Get_ChipID APIs
+   - xilinx: versal: Implement power down/restart related EEMI, SMC handler for
+     EEMI, PLL related PM, clock related PM, pin control related PM, reset related
+     PM, device related PM , APIs
+   - xilinx: versal: Enable ipi mailbox service
+   - xilinx: versal: Add get_api_version support and support to send PM API to PMC
+     using IPI
+   - xilinx: zynqmp: Add checksum support for IPI data, GET_CALLBACK_DATA
+     function, support to query max divisor, CLK_SET_RATE_PARENT in gem clock
+     node, support for custom type flags, LPD WDT clock to the pm_clock structure,
+     idcodes for new RFSoC silicons ZU48DR and ZU49DR, and id for new RFSoC device
+     ZU39DR
+
+- Security
+   - Use Speculation Barrier instruction for v8.5+ cores
+
+   - Add support for optional firmware encryption feature (experimental).
+
+   - Introduce a new `dualroot` chain of trust.
+
+   - aarch64: Prevent speculative execution past ERET
+   - aarch32: Stop speculative execution past exception returns.
+
+- SPCI
+   - Introduced the Secure Partition Manager Dispatcher (SPMD) component as a
+     new standard service.
+
+- Tools
+   - cert_create: Introduce CoT build option and TBBR CoT makefile,
+     and define the dualroot CoT
+
+   - encrypt_fw: Add firmware authenticated encryption tool
+
+   - memory: Add show_memory script that prints a representation
+     of the memory layout for the latest build
+
+Changed
+^^^^^^^
+
+- Arm Architecture
+   - PIE: Make call to GDT relocation fixup generalized
+
+- BL-Specific
+   - Increase maximum size of BL2 image
+
+   - BL31: Discard .dynsym .dynstr .hash sections to make ENABLE_PIE work
+   - BL31: Split into two separate memory regions
+
+   - Unify BL linker scripts and reduce code duplication.
+
+- Build System
+   - Changes to drive cert_create for dualroot CoT
+
+   - Enable -Wlogical-op always
+
+   - Enable -Wshadow always
+
+   - Refactor the warning flags
+
+   - PIE: Pass PIE options only to BL31
+
+   - Reduce space lost to object alignment
+
+   - Set lld as the default linker for Clang builds
+
+   - Remove -Wunused-const-variable and -Wpadded warning
+
+   - Remove -Wmissing-declarations warning from WARNING1 level
+
+- Drivers
+   - authentication: Necessary fix in drivers to upgrade to mbedtls-2.18.0
+
+   - console: Integrate UART base address in generic console_t
+
+   - gicv3: Change API for GICR_IPRIORITYR accessors and separate
+     GICD and GICR accessor functions
+
+   - io: Change seek offset to signed long long and panic in case
+     of io setup failure
+
+   - smmu: SMMUv3: Changed retry loop to delay timer
+
+   - tbbr: Reduce size of hash and ECDSA key buffers when possible
+
+- Library Code
+   - libc: Consolidate the size_t, unified, and NULL definitions,
+     and unify intmax_t and uintmax_t on AArch32/64
+
+   - ROMLIB: Optimize memory layout when ROMLIB is used
+
+   - xlat_tables_v2: Use ARRAY_SIZE in REGISTER_XLAT_CONTEXT_FULL_SPEC,
+     merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE},
+     and simplify end address checks in mmap_add_region_check()
+
+- Platforms
+   - allwinner: Adjust SRAM A2 base to include the ARISC vectors, clean up MMU
+     setup, reenable USE_COHERENT_MEM, remove unused include path, move the
+     NOBITS region to SRAM A1, convert AXP803 regulator setup code into a driver,
+     enable clock before resetting I2C/RSB
+   - allwinner: h6: power: Switch to using the AXP driver
+   - allwinner: a64: power: Use fdt_for_each_subnode, remove obsolete register
+     check, remove duplicate DT check, and make sunxi_turn_off_soc static
+   - allwinner: Build PMIC bus drivers only in BL31, clean up PMIC-related error
+     handling, and synchronize PMIC enumerations
+
+   - arm/a5ds: Change boot address to point to DDR address
+
+   - arm/common: Check for out-of-bound accesses in the platform io policies
+
+   - arm/corstone700: Updating the kernel arguments to support initramfs,
+     use fdts DDR memory and XIP rootfs, and set UART clocks to 32MHz
+
+   - arm/fvp: Modify multithreaded dts file of DynamIQ FVPs, slightly bump
+     the stack size for bl1 and bl2, remove re-definition of topology related
+     build options, stop reclaiming init code with Clang builds, and map only
+     the needed DRAM region statically in BL31/SP_MIN
+
+   - arm/juno: Maximize space allocated to SCP_BL2
+
+   - arm/sgi: Bump bl1 RW limit, mark remote chip shared ram as non-cacheable,
+     move GIC related constants to board files, include AFF3 affinity in core
+     position calculation, move bl31_platform_setup to board file, and move
+     topology information to board folder
+
+   - common: Refactor load_auth_image_internal().
+
+   - hisilicon: Remove uefi-tools in hikey and hikey960 documentation
+
+   - intel: Modify non secure access function, BL31 address mapping, mailbox's
+     get_config_status, and stratix10 BL31 parameter handling
+   - intel: Remove un-needed checks for qspi driver r/w and s10 unused source code
+   - intel: Change all global sip function to static
+   - intel: Refactor common platform code
+   - intel: Create SiP service header file
+
+
+   - marvell: armada: scp_bl2: Allow loading up to 8 images
+   - marvell: comphy-a3700: Support SGMII COMPHY power off and fix USB3
+     powering on when on lane 2
+   - marvell: Consolidate console register calls
+
+   - mediatek: mt8183: Protect 4GB~8GB dram memory, refine GIC driver for
+     low power scenarios, and switch PLL/CLKSQ/ck_off/axi_26m control to SPM
+
+   - qemu: Update flash address map to keep FIP in secure FLASH0
+
+   - renesas: rcar_gen3: Update IPL and Secure Monitor Rev.2.0.6, update DDR
+     setting for H3, M3, M3N, change fixed destination address of BL31 and BL32,
+     add missing #{address,size}-cells into generated DT, pass DT to OpTee OS,
+     and move DDR drivers out of staging
+
+   - rockchip: Make miniloader ddr_parameter handling optional, cleanup securing
+     of ddr regions, move secure init to separate file, use base+size for secure
+     ddr regions, bring TZRAM_SIZE values in lined, and prevent macro expansion
+     in paths
+
+   - rpi: Move plat_helpers.S to common
+   - rpi3: gpio: Simplify GPIO setup
+   - rpi4: Skip UART initialisation
+
+   - st: stm32m1: Use generic console_t data structure, remove second
+     QSPI flash instance, update for FMC2 pin muxing, and reduce MAX_XLAT_TABLES
+     to 4
+
+   - socionext: uniphier: Make on-chip SRAM and I/O register regions configurable
+   - socionext: uniphier: Make PSCI related, counter control, UART, pinmon, NAND
+     controller, and eMMC controller base addresses configurable
+   - socionext: uniphier: Change block_addressing flag and the return value type
+     of .is_usb_boot() to bool
+   - socionext: uniphier: Run BL33 at EL2, call uniphier_scp_is_running() only
+     when on-chip STM is supported, define PLAT_XLAT_TABLES_DYNAMIC only for BL2,
+     support read-only xlat tables, use enable_mmu() in common function, shrink
+     UNIPHIER_ROM_REGION_SIZE, prepare uniphier_soc_info() for next SoC, extend
+     boot device detection for future SoCs, make all BL images completely
+     position-independent, make uniphier_mmap_setup() work with PIE, pass SCP
+     base address as a function parameter, set buffer offset and length for
+     io_block dynamically, and use more mmap_add_dynamic_region() for loading
+     images
+
+   - spd/trusty: Disable error messages seen during boot, allow gic base to be
+     specified with GICD_BASE, and allow getting trusty memsize from BL32_MEM_SIZE
+     instead of TSP_SEC_MEM_SIZE
+
+   - ti: k3: common: Enable ARM cluster power down and rename device IDs to
+     be more consistent
+   - ti: k3: drivers: ti_sci: Put sequence number in coherent memory and
+     remove indirect structure of const data
+
+   - xilinx: Move ipi mailbox svc to xilinx common
+   - xilinx: zynqmp: Use GIC framework for warm restart
+   - xilinx: zynqmp: pm: Move custom clock flags to typeflags, remove
+     CLK_TOPSW_LSBUS from invalid clock list and rename FPD WDT clock ID
+   - xilinx: versal: Increase OCM memory size for DEBUG builds and adjust
+     cpu clock, Move versal_def.h and versal_private to include directory
+
+- Tools
+   - sptool: Updated sptool to accomodate building secure partition packages.
+
+Resolved Issues
+^^^^^^^^^^^^^^^
+
+- Arm Architecture
+   - Fix crash dump for lower EL
+
+- BL-Specific
+   - Bug fix: Protect TSP prints with lock
+
+   - Fix boot failures on some builds linked with ld.lld.
+
+- Build System
+   - Fix clang build if CC is not in the path.
+
+   - Fix 'BL stage' comment for build macros
+
+- Code Quality
+   - coverity: Fix various MISRA violations including null pointer violations,
+     C issues in BL1/BL2/BL31 and FDT helper functions, using boolean essential,
+     type, and removing unnecessary header file and comparisons to LONG_MAX in
+     debugfs devfip
+
+   - Based on coding guidelines, replace all `unsigned long` depending on if
+     fixed based on AArch32 or AArch64.
+
+   - Unify type of "cpu_idx" and Platform specific defines across PSCI module.
+
+- Drivers
+   - auth: Necessary fix in drivers to upgrade to mbedtls-2.18.0
+
+   - delay_timer: Fix non-standard frequency issue in udelay
+
+   - gicv3: Fix compiler dependent behavior
+   - gic600: Fix include ordering according to the coding style and power up sequence
+
+- Library Code
+   - el3_runtime: Fix stack pointer maintenance on EA handling path,
+     fixup 'cm_setup_context' prototype, and adds TPIDR_EL2 register
+     to the context save restore routines
+
+   - libc: Fix SIZE_MAX on AArch32
+
+   - locks: T589: Fix insufficient ordering guarantees in bakery lock
+
+   - pmf: Fix 'tautological-constant-compare' error, Make the runtime
+     instrumentation work on AArch32, and Simplify PMF helper macro
+     definitions across header files
+
+   - xlat_tables_v2: Fix assembler warning of PLAT_RO_XLAT_TABLES
+
+- Platforms
+   - allwinner: Fix H6 GPIO and CCU memory map addresses and incorrect ARISC
+     code patch offset check
+
+   - arm/a5ds: Correct system freq and Cache Writeback Granule, and cleanup
+     enable-method in devicetree
+
+   - arm/fvp: Fix incorrect GIC mapping, BL31 load address and image size
+     for RESET_TO_BL31=1, topology description of cpus for DynamIQ based
+     FVP, and multithreaded FVP power domain tree
+   - arm/fvp: spm-mm: Correcting instructions to build SPM for FVP
+
+   - arm/common: Fix ROTPK hash generation for ECDSA encryption, BL2 bug in
+     dynamic configuration initialisation, and current RECLAIM_INIT_CODE behavior
+
+   - arm/rde1edge: Fix incorrect topology tree description
+
+   - arm/sgi: Fix the incorrect check for SCMI channel ID
+
+   - common: Flush dcache when storing timestamp
+
+   - intel: Fix UEFI decompression issue, memory calibration, SMC SIP service,
+     mailbox config return status, mailbox driver logic, FPGA manager on
+     reconfiguration, and mailbox send_cmd issue
+
+   - imx: Fix shift-overflow errors, the rdc memory region slot's offset,
+     multiple definition of ipc_handle, missing inclusion of cdefs.h, and
+     correct the SGIs that used for secure interrupt
+
+   - mediatek: mt8183: Fix AARCH64 init fail on CPU0
+
+   - rockchip: Fix definition of struct param_ddr_usage
+
+   - rpi4: Fix documentation of armstub config entry
+
+   - st: Correct io possible NULL pointer dereference and device_size type,
+     nand xor_ecc.val assigned value, static analysis tool issues, and fix
+     incorrect return value and correctly check pwr-regulators node
+
+   - xilinx: zynqmp: Correct syscnt freq for QEMU and fix clock models
+     and IDs of GEM-related clocks
+
+Known Issues
+^^^^^^^^^^^^
+
+- Build System
+   - dtb: DTB creation not supported when building on a Windows host.
+
+     This step in the build process is skipped when running on a Windows host. A
+     known issue from the 1.6 release.
+
+   - Intermittent assertion firing `ASSERT: services/spd/tspd/tspd_main.c:105`
+
+- Coverity
+   - Intermittent Race condition in Coverity Jenkins Build Job
+
+- Platforms
+   - arm/juno: System suspend from Linux does not function as documented in the
+     user guide
+
+     Following the instructions provided in the user guide document does not
+     result in the platform entering system suspend state as expected. A message
+     relating to the hdlcd driver failing to suspend will be emitted on the
+     Linux terminal.
+
+   - mediatek/mt6795: This platform does not build in this release
+
 Version 2.2
 -----------
 
diff --git a/docs/components/arm-sip-service.rst b/docs/components/arm-sip-service.rst
index 01bc04d..b51a94d 100644
--- a/docs/components/arm-sip-service.rst
+++ b/docs/components/arm-sip-service.rst
@@ -430,6 +430,6 @@
 
 --------------
 
-*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.*
 
-.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
diff --git a/docs/components/debugfs-design.rst b/docs/components/debugfs-design.rst
index 8ce1ba6..2096bdb 100644
--- a/docs/components/debugfs-design.rst
+++ b/docs/components/debugfs-design.rst
@@ -78,7 +78,7 @@
 -------------
 
 The communication with the 9p layer in BL31 is made through an SMC conduit
-(`SMC Calling Convention PDD`_), using a specific SiP Function Id. An NS
+(`SMC Calling Convention`_), using a specific SiP Function Id. An NS
 shared buffer is used to pass path string parameters, or e.g. to exchange
 data on a read operation. Refer to `ARM SiP Services`_ for a description
 of the SMC interface.
@@ -119,7 +119,7 @@
 
 *Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
 
-.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
 .. _Notes on the Plan 9 Kernel Source: http://lsub.org/who/nemo/9.pdf
 .. _Linux 9p remote filesystem protocol: https://www.kernel.org/doc/Documentation/filesystems/9p.txt
 .. _ARM SiP Services: arm-sip-service.rst
diff --git a/docs/components/exception-handling.rst b/docs/components/exception-handling.rst
index e330a62..4cca5f4 100644
--- a/docs/components/exception-handling.rst
+++ b/docs/components/exception-handling.rst
@@ -467,7 +467,7 @@
 Non-secure world to request Secure services. They're broadly classified as
 *Fast* or *Yielding* (see `SMCCC`__).
 
-.. __: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
+.. __: https://developer.arm.com/docs/den0028/latest
 
 -  *Fast* SMCs are atomic from the caller's point of view. I.e., they return
    to the caller only when the Secure world has finished serving the request.
diff --git a/docs/components/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst
index 52b1c03..4f67185 100644
--- a/docs/components/secure-partition-manager-design.rst
+++ b/docs/components/secure-partition-manager-design.rst
@@ -807,13 +807,13 @@
 
 --------------
 
-*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.*
 
 .. _Armv8-A ARM: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
 .. _instructions in the EDK2 repository: https://github.com/tianocore/edk2-staging/blob/AArch64StandaloneMm/HowtoBuild.MD
 .. _Management Mode Interface Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0060a/DEN0060A_ARM_MM_Interface_Specification.pdf
 .. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
-.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
 
 .. |Image 1| image:: ../resources/diagrams/secure_sw_stack_tos.png
 .. |Image 2| image:: ../resources/diagrams/secure_sw_stack_sp.png
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 8e9dc38..b336b38 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -544,7 +544,7 @@
 exception vectors implement more elaborate support for handling SMCs since this
 is the only mechanism to access the runtime services implemented by BL31 (PSCI
 for example). BL31 checks each SMC for validity as specified by the
-`SMC Calling Convention PDD`_ before passing control to the required SMC
+`SMC Calling Convention`_ before passing control to the required SMC
 handler routine.
 
 BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system
@@ -2711,7 +2711,7 @@
 
 -  `Power State Coordination Interface PDD`_
 
--  `SMC Calling Convention PDD`_
+-  `SMC Calling Convention`_
 
 -  :ref:`Interrupt Management Framework`
 
@@ -2720,11 +2720,11 @@
 *Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
 
 .. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
-.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
+.. _SMCCC: https://developer.arm.com/docs/den0028/latest
 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
 .. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
 .. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
-.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
 .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
 
 .. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png
diff --git a/docs/design/interrupt-framework-design.rst b/docs/design/interrupt-framework-design.rst
index d155cb3..14f7227 100644
--- a/docs/design/interrupt-framework-design.rst
+++ b/docs/design/interrupt-framework-design.rst
@@ -1011,9 +1011,9 @@
 
 --------------
 
-*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
 
-.. _SMC calling convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
+.. _SMC calling convention: https://developer.arm.com/docs/den0028/latest
 
 .. |Image 1| image:: ../resources/diagrams/sec-int-handling.png
 .. |Image 2| image:: ../resources/diagrams/non-sec-int-handling.png
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 778b49c..90fe83f 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -643,6 +643,7 @@
 -  ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
    firmware configuration framework. This will move the io_policies into a
    configuration device tree, instead of static structure in the code base.
+   This is currently an experimental feature.
 
 
 -  ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
diff --git a/docs/getting_started/psci-lib-integration-guide.rst b/docs/getting_started/psci-lib-integration-guide.rst
index 1351fff..3735265 100644
--- a/docs/getting_started/psci-lib-integration-guide.rst
+++ b/docs/getting_started/psci-lib-integration-guide.rst
@@ -538,9 +538,9 @@
 
 --------------
 
-*Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.*
 
 .. _PSCI spec: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
-.. _SMCCC: https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR570-DA-80002-r0p0-00rel0/ARM_DEN0028A_SMC_Calling_Convention.pdf
+.. _SMCCC: https://developer.arm.com/docs/den0028/latest
 .. _PSCI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
 .. _PSCI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
diff --git a/docs/getting_started/rt-svc-writers-guide.rst b/docs/getting_started/rt-svc-writers-guide.rst
index 5375b65..b3758b8 100644
--- a/docs/getting_started/rt-svc-writers-guide.rst
+++ b/docs/getting_started/rt-svc-writers-guide.rst
@@ -314,7 +314,7 @@
 
 --------------
 
-*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
 
-.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
+.. _SMCCC: https://developer.arm.com/docs/den0028/latest
 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
diff --git a/docs/index.rst b/docs/index.rst
index 7413edd..cb53127 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -91,4 +91,4 @@
 .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
 .. _System Control and Management Interface (SCMI): http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
 .. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
-.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index 169b6f3..eb7eb00 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -12,7 +12,7 @@
 (64-bit host machine only).
 
 .. note::
-   The FVP models used are Version 11.6 Build 45, unless otherwise stated.
+   The FVP models used are Version 11.9 Build 41, unless otherwise stated.
 
 -  ``FVP_Base_AEMv8A-AEMv8A``
 -  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
@@ -26,8 +26,8 @@
 -  ``FVP_Base_Cortex-A57x2-A53x4``
 -  ``FVP_Base_Cortex-A57x4-A53x4``
 -  ``FVP_Base_Cortex-A57x4``
--  ``FVP_Base_Cortex-A65x4`` (Version 11.9 build 41)
--  ``FVP_Base_Cortex-A65AEx8`` (Version 11.9 build 41)
+-  ``FVP_Base_Cortex-A65x4``
+-  ``FVP_Base_Cortex-A65AEx8``
 -  ``FVP_Base_Cortex-A72x4-A53x4``
 -  ``FVP_Base_Cortex-A72x4``
 -  ``FVP_Base_Cortex-A73x4-A53x4``
@@ -36,13 +36,13 @@
 -  ``FVP_Base_Cortex-A76x4``
 -  ``FVP_Base_Cortex-A76AEx4``
 -  ``FVP_Base_Cortex-A76AEx8``
--  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
+-  ``FVP_Base_Cortex-A77x4``
 -  ``FVP_Base_Neoverse-N1x4``
 -  ``FVP_Base_Zeusx4``
--  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
--  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
--  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
--  ``FVP_RD_N1Edge``
+-  ``FVP_CSS_SGI-575`` (Version 11.10 build 25)
+-  ``FVP_CSS_SGM-775``
+-  ``FVP_RD_E1Edge``
+-  ``FVP_RD_N1Edge`` (Version 11.10 build 25)
 -  ``Foundation_Platform``
 
 The latest version of the AArch32 build of TF-A has been tested on the
diff --git a/docs/plat/brcm-stingray.rst b/docs/plat/brcm-stingray.rst
index c43c850..95029cc 100644
--- a/docs/plat/brcm-stingray.rst
+++ b/docs/plat/brcm-stingray.rst
@@ -1,27 +1,30 @@
+Broadcom Stingray
+=================
+
 Description
-===========
+-----------
 Broadcom's Stingray(BCM958742t) is a multi-core processor with 8 Cortex-A72 cores.
 Trusted Firmware-A (TF-A) is used to implement secure world firmware, supporting
-BL2 and BL31 for Broadcom Stingray SoCs
+BL2 and BL31 for Broadcom Stingray SoCs.
 
 On Poweron, Boot ROM will load bl2 image and Bl2 will initialize the hardware,
 then loads bl31 and bl33 into DDR and boots to bl33.
 
 Boot Sequence
-=============
+-------------
 
 Bootrom --> TF-A BL2 --> TF-A BL31 --> BL33(u-boot)
 
 Code Locations
---------------
+~~~~~~~~~~~~~~
 -  Trusted Firmware-A:
-   `link <https://github.com/ARM-software/arm-trusted-firmware>`__
+   `link <https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/>`__
 
 How to build
-============
+------------
 
 Build Procedure
----------------
+~~~~~~~~~~~~~~~
 
 -  Prepare AARCH64 toolchain.
 
@@ -31,10 +34,10 @@
 
    Build fip:
 
-   .. code::shell
+   .. code:: shell
 
        make CROSS_COMPILE=aarch64-linux-gnu- PLAT=stingray BOARD_CFG=bcm958742t all fip BL33=u-boot.bin
 
 Deploy TF-A Images
------------------
+~~~~~~~~~~~~~~~~~~
 The u-boot will be upstreamed soon, this doc will be updated once they are ready, and the link will be posted.
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index a6ef188..7969003 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -37,6 +37,7 @@
    ti-k3
    xilinx-versal
    xilinx-zynqmp
+   brcm-stingray
 
 This section provides a list of supported upstream *platform ports* and the
 documentation associated with them.
diff --git a/docs/security_advisories/security-advisory-tfv-8.rst b/docs/security_advisories/security-advisory-tfv-8.rst
index c401eb3..ebe324e 100644
--- a/docs/security_advisories/security-advisory-tfv-8.rst
+++ b/docs/security_advisories/security-advisory-tfv-8.rst
@@ -99,5 +99,5 @@
 
 .. _CVE-2018-19440: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-19440
 .. _commit c385955: https://github.com/ARM-software/arm-trusted-firmware/commit/c385955
-.. _SMC Calling Convention: http://arminfo.emea.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
 .. _Pull Request #1710: https://github.com/ARM-software/arm-trusted-firmware/pull/1710
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts
index 7334c45..c6f5be6 100644
--- a/fdts/a5ds.dts
+++ b/fdts/a5ds.dts
@@ -128,7 +128,7 @@
 		#size-cells = <1>;
 		ranges;
 		reg = <0x1a040000 0x1000>;
-		clock-frequency = <50000000>;
+		clock-frequency = <7500000>;
 
 		frame@1a050000 {
 			frame-number = <0>;
diff --git a/plat/arm/board/arm_fpga/fpga_bl31_setup.c b/plat/arm/board/arm_fpga/fpga_bl31_setup.c
index d499379..6329497 100644
--- a/plat/arm/board/arm_fpga/fpga_bl31_setup.c
+++ b/plat/arm/board/arm_fpga/fpga_bl31_setup.c
@@ -56,7 +56,6 @@
 
 	/* Write frequency to CNTCRL and initialize timer */
 	generic_delay_timer_init();
-	mmio_write_32(FPGA_TIMER_BASE, ((1 << 8) | 1UL));
 }
 
 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h
index 56ee166..dbdbe6f 100644
--- a/plat/arm/board/arm_fpga/fpga_def.h
+++ b/plat/arm/board/arm_fpga/fpga_def.h
@@ -36,6 +36,5 @@
 #define PLAT_FPGA_CRASH_UART_CLK_IN_HZ		PLAT_FPGA_BOOT_UART_CLK_IN_HZ
 
 #define FPGA_TIMER_FREQUENCY			10000000
-#define FPGA_TIMER_BASE				0x2a830000
 
 #endif
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index 79c4c07..ebfbe17 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -27,12 +27,12 @@
 		vm1 {
 			is_spci_partition;
 			debug_name = "cactus-primary";
-			load-addr = <0x7000000>;
+			load_address = <0x7000000>;
 		};
 		vm2 {
 			is_spci_partition;
 			debug_name = "cactus-secondary";
-			load-addr = <0x7100000>;
+			load_address = <0x7100000>;
 			vcpu_count = <2>;
 			mem_size = <1048576>;
 		};
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 43c267d..67802d4 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -253,7 +253,9 @@
  * anything else in this memory region and is handed over to the SCP before
  * BL31 is loaded over the top.
  */
-#define PLAT_CSS_MAX_SCP_BL2_SIZE	(SCP_BL2_LIMIT - ARM_TB_FW_CONFIG_LIMIT)
+#define PLAT_CSS_MAX_SCP_BL2_SIZE \
+	((SCP_BL2_LIMIT - ARM_TB_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK)
+
 #define PLAT_CSS_MAX_SCP_BL2U_SIZE	PLAT_CSS_MAX_SCP_BL2_SIZE
 
 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
diff --git a/plat/arm/board/rddanielxlr/fdts/rddanielxlr_fw_config.dts b/plat/arm/board/rddanielxlr/fdts/rddanielxlr_fw_config.dts
new file mode 100644
index 0000000..81e4cc1
--- /dev/null
+++ b/plat/arm/board/rddanielxlr/fdts/rddanielxlr_fw_config.dts
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <export/common/tbbr/tbbr_img_def_exp.h>
+
+/dts-v1/;
+
+/ {
+	dtb-registry {
+		compatible = "arm,dyn_cfg-dtb_registry";
+
+		/* tb_fw_config is temporarily contained on this dtb */
+		tb_fw-config {
+			load-address = <0x0 0x4001010>;
+			max-size = <0x200>;
+			id = <TB_FW_CONFIG_ID>;
+		};
+
+		nt_fw-config {
+			load-address = <0x0 0xFEF00000>;
+			max-size = <0x0100000>;
+			id = <NT_FW_CONFIG_ID>;
+		};
+	};
+
+	tb_fw-config {
+		compatible = "arm,tb_fw";
+
+		/* Disable authentication for development */
+		disable_auth = <0x0>;
+
+		/*
+		 * The following two entries are placeholders for Mbed TLS
+		 * heap information. The default values don't matter since
+		 * they will be overwritten by BL1.
+		 * In case of having shared Mbed TLS heap between BL1 and BL2,
+		 * BL1 will populate these two properties with the respective
+		 * info about the shared heap. This info will be available for
+		 * BL2 in order to locate and re-use the heap.
+		 */
+		mbedtls_heap_addr = <0x0 0x0>;
+		mbedtls_heap_size = <0x0>;
+	};
+};
diff --git a/plat/arm/board/rddanielxlr/fdts/rddanielxlr_nt_fw_config.dts b/plat/arm/board/rddanielxlr/fdts/rddanielxlr_nt_fw_config.dts
new file mode 100644
index 0000000..42d07a4
--- /dev/null
+++ b/plat/arm/board/rddanielxlr/fdts/rddanielxlr_nt_fw_config.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+/ {
+	/* compatible string */
+	compatible = "arm,rd-daniel-xlr";
+
+	/*
+	 * Place holder for system-id node with default values. The
+	 * value of platform-id and config-id will be set to the
+	 * correct values during the BL2 stage of boot.
+	 */
+	system-id {
+		platform-id = <0x0>;
+		config-id = <0x0>;
+		multi-chip-mode = <0x0>;
+	};
+};
diff --git a/plat/arm/board/rddanielxlr/include/platform_def.h b/plat/arm/board/rddanielxlr/include/platform_def.h
new file mode 100644
index 0000000..b1376b8
--- /dev/null
+++ b/plat/arm/board/rddanielxlr/include/platform_def.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+#include <sgi_base_platform_def.h>
+
+#define PLAT_ARM_CLUSTER_COUNT		U(4)
+#define CSS_SGI_MAX_CPUS_PER_CLUSTER	U(1)
+#define CSS_SGI_MAX_PE_PER_CPU		U(1)
+
+#define PLAT_CSS_MHU_BASE		UL(0x45400000)
+#define PLAT_MHUV2_BASE			PLAT_CSS_MHU_BASE
+
+#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
+
+/* Virtual address used by dynamic mem_protect for chunk_base */
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xC0000000)
+
+/* Physical and virtual address space limits for MMU in AARCH64 mode */
+#define PLAT_PHY_ADDR_SPACE_SIZE	CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+						CSS_SGI_CHIP_COUNT)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+						CSS_SGI_CHIP_COUNT)
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE		UL(0x30000000)
+#define PLAT_ARM_GICC_BASE		UL(0x2C000000)
+#define PLAT_ARM_GICR_BASE		UL(0x30140000)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rddanielxlr/platform.mk b/plat/arm/board/rddanielxlr/platform.mk
new file mode 100644
index 0000000..36a0099
--- /dev/null
+++ b/plat/arm/board/rddanielxlr/platform.mk
@@ -0,0 +1,57 @@
+# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Enable GICv4 extension with multichip driver
+GIC_ENABLE_V4_EXTN		:=	1
+GICV3_IMPL_GIC600_MULTICHIP	:=	1
+
+include plat/arm/css/sgi/sgi-common.mk
+
+RDDANIELXLR_BASE	=	plat/arm/board/rddanielxlr
+
+PLAT_INCLUDES		+=	-I${RDDANIELXLR_BASE}/include/
+
+SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_zeus.S
+
+BL1_SOURCES		+=	${SGI_CPU_SOURCES}			\
+				${RDDANIELXLR_BASE}/rddanielxlr_err.c
+
+BL2_SOURCES		+=	${RDDANIELXLR_BASE}/rddanielxlr_plat.c	\
+				${RDDANIELXLR_BASE}/rddanielxlr_security.c	\
+				${RDDANIELXLR_BASE}/rddanielxlr_err.c	\
+				lib/utils/mem_region.c			\
+				plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
+				${RDDANIELXLR_BASE}/rddanielxlr_plat.c	\
+				${RDDANIELXLR_BASE}/rddanielxlr_topology.c	\
+				drivers/cfi/v2m/v2m_flash.c		\
+				drivers/arm/gic/v3/gic600_multichip.c	\
+				lib/utils/mem_region.c			\
+				plat/arm/common/arm_nor_psci_mem_protect.c
+
+# Enable dynamic addition of MMAP regions in BL31
+BL31_CFLAGS		+=	-DPLAT_XLAT_TABLES_DYNAMIC
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES		+=	${RDDANIELXLR_BASE}/fdts/${PLAT}_fw_config.dts
+TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
+
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
+
+$(eval $(call CREATE_SEQ,SEQ,4))
+ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
+ $(error  "Chip count for RD-Daniel Config-XLR should be either $(SEQ) \
+ currently it is set to ${CSS_SGI_CHIP_COUNT}.")
+endif
+
+FDT_SOURCES		+=	${RDDANIELXLR_BASE}/fdts/${PLAT}_nt_fw_config.dts
+NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
+
+# Add the NT_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
+
+override CTX_INCLUDE_AARCH32_REGS	:= 0
diff --git a/plat/arm/board/rddanielxlr/rddanielxlr_err.c b/plat/arm/board/rddanielxlr/rddanielxlr_err.c
new file mode 100644
index 0000000..bff57cd
--- /dev/null
+++ b/plat/arm/board/rddanielxlr/rddanielxlr_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * rddanielxlr error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+	while (true) {
+		wfi();
+	}
+}
diff --git a/plat/arm/board/rddanielxlr/rddanielxlr_plat.c b/plat/arm/board/rddanielxlr/rddanielxlr_plat.c
new file mode 100644
index 0000000..4b5f16a
--- /dev/null
+++ b/plat/arm/board/rddanielxlr/rddanielxlr_plat.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/arm/gic600_multichip.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <sgi_base_platform_def.h>
+#include <sgi_plat.h>
+
+#if defined(IMAGE_BL31)
+static const mmap_region_t rddanielxlr_dynamic_mmap[] = {
+	ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
+	CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+	SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1),
+#if (CSS_SGI_CHIP_COUNT > 2)
+	ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
+	CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
+	SOC_CSS_MAP_DEVICE_REMOTE_CHIP(2),
+#endif
+#if (CSS_SGI_CHIP_COUNT > 3)
+	ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
+	CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
+	SOC_CSS_MAP_DEVICE_REMOTE_CHIP(3)
+#endif
+};
+
+static struct gic600_multichip_data rddanielxlr_multichip_data __init = {
+	.rt_owner_base = PLAT_ARM_GICD_BASE,
+	.rt_owner = 0,
+	.chip_count = CSS_SGI_CHIP_COUNT,
+	.chip_addrs = {
+		PLAT_ARM_GICD_BASE >> 16,
+		(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
+#if (CSS_SGI_CHIP_COUNT > 2)
+		(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
+#endif
+#if (CSS_SGI_CHIP_COUNT > 3)
+		(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
+#endif
+	},
+	.spi_ids = {
+		{32, 255},
+		{0, 0},
+#if (CSS_SGI_CHIP_COUNT > 2)
+		{0, 0},
+#endif
+#if (CSS_SGI_CHIP_COUNT > 3)
+		{0, 0},
+#endif
+	}
+};
+
+static uintptr_t rddanielxlr_multichip_gicr_frames[] = {
+	/* Chip 0's GICR Base */
+	PLAT_ARM_GICR_BASE,
+	/* Chip 1's GICR BASE */
+	PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
+#if (CSS_SGI_CHIP_COUNT > 2)
+	/* Chip 2's GICR BASE */
+	PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
+#endif
+#if (CSS_SGI_CHIP_COUNT > 3)
+	/* Chip 3's GICR BASE */
+	PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
+#endif
+	UL(0)	/* Zero Termination */
+};
+#endif /* IMAGE_BL31 */
+
+unsigned int plat_arm_sgi_get_platform_id(void)
+{
+	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
+				& SID_SYSTEM_ID_PART_NUM_MASK;
+}
+
+unsigned int plat_arm_sgi_get_config_id(void)
+{
+	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
+}
+
+unsigned int plat_arm_sgi_get_multi_chip_mode(void)
+{
+	return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
+			SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
+}
+
+/*
+ * bl31_platform_setup_function is guarded by IMAGE_BL31 macro because
+ * PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
+ * for other stages.
+ */
+#if defined(IMAGE_BL31)
+void bl31_platform_setup(void)
+{
+	int ret;
+	unsigned int i;
+
+	if ((plat_arm_sgi_get_multi_chip_mode() == 0) &&
+			(CSS_SGI_CHIP_COUNT > 1)) {
+		ERROR("Chip Count is set to %u but multi-chip mode is not "
+			"enabled\n", CSS_SGI_CHIP_COUNT);
+		panic();
+	} else if ((plat_arm_sgi_get_multi_chip_mode() == 1) &&
+			(CSS_SGI_CHIP_COUNT > 1)) {
+		INFO("Enabling support for multi-chip in RD-Daniel Cfg-XLR\n");
+
+		for (i = 0; i < ARRAY_SIZE(rddanielxlr_dynamic_mmap); i++) {
+			ret = mmap_add_dynamic_region(
+					rddanielxlr_dynamic_mmap[i].base_pa,
+					rddanielxlr_dynamic_mmap[i].base_va,
+					rddanielxlr_dynamic_mmap[i].size,
+					rddanielxlr_dynamic_mmap[i].attr);
+			if (ret != 0) {
+				ERROR("Failed to add dynamic mmap entry "
+						"(ret=%d)\n", ret);
+				panic();
+			}
+		}
+
+		plat_arm_override_gicr_frames(
+			rddanielxlr_multichip_gicr_frames);
+		gic600_multichip_init(&rddanielxlr_multichip_data);
+	}
+
+	sgi_bl31_common_platform_setup();
+}
+#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/rddanielxlr/rddanielxlr_security.c b/plat/arm/board/rddanielxlr/rddanielxlr_security.c
new file mode 100644
index 0000000..541f800
--- /dev/null
+++ b/plat/arm/board/rddanielxlr/rddanielxlr_security.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Initialize the secure environment */
+void plat_arm_security_setup(void)
+{
+}
diff --git a/plat/arm/board/rddanielxlr/rddanielxlr_topology.c b/plat/arm/board/rddanielxlr/rddanielxlr_topology.c
new file mode 100644
index 0000000..610e667
--- /dev/null
+++ b/plat/arm/board/rddanielxlr/rddanielxlr_topology.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/arm/css/common/css_pm.h>
+#include <sgi_variant.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+const unsigned char rd_daniel_xlr_pd_tree_desc_multi_chip[] = {
+	((PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT)),
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#if (CSS_SGI_CHIP_COUNT > 1)
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#endif
+#if (CSS_SGI_CHIP_COUNT > 2)
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#endif
+#if (CSS_SGI_CHIP_COUNT > 3)
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER
+#endif
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	if (plat_arm_sgi_get_multi_chip_mode() == 1)
+		return rd_daniel_xlr_pd_tree_desc_multi_chip;
+	panic();
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+#if (CSS_SGI_CHIP_COUNT > 1)
+	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
+	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
+	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
+	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (CSS_SGI_CHIP_COUNT > 2)
+	(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
+	(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
+	(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
+	(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (CSS_SGI_CHIP_COUNT > 3)
+	(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
+	(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
+	(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
+	(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3))
+#endif
+};
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index 3b8d565..14cdb7e 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -38,8 +38,8 @@
 #  define PLAT_SP_IMAGE_MMAP_REGIONS	7
 #  define PLAT_SP_IMAGE_MAX_XLAT_TABLES	10
 # else
-#  define PLAT_ARM_MMAP_ENTRIES		8
-#  define MAX_XLAT_TABLES		8
+#  define PLAT_ARM_MMAP_ENTRIES		(5 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
+#  define MAX_XLAT_TABLES		(5 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
 # endif
 #elif defined(IMAGE_BL32)
 # define PLAT_ARM_MMAP_ENTRIES		8
diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h
index 12fa07f..8be0b34 100644
--- a/plat/arm/css/sgm/include/sgm_base_platform_def.h
+++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h
@@ -137,7 +137,9 @@
  * anything else in this memory region and is handed over to the SCP before
  * BL31 is loaded over the top.
  */
-#define PLAT_CSS_MAX_SCP_BL2_SIZE	(SCP_BL2_LIMIT - ARM_TB_FW_CONFIG_LIMIT)
+#define PLAT_CSS_MAX_SCP_BL2_SIZE \
+	((SCP_BL2_LIMIT - ARM_TB_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK)
+
 #define PLAT_CSS_MAX_SCP_BL2U_SIZE	PLAT_CSS_MAX_SCP_BL2_SIZE
 
 /*
diff --git a/plat/brcm/board/stingray/src/bl2_setup.c b/plat/brcm/board/stingray/src/bl2_setup.c
index 9a79744..b2c8aec 100644
--- a/plat/brcm/board/stingray/src/bl2_setup.c
+++ b/plat/brcm/board/stingray/src/bl2_setup.c
@@ -682,7 +682,7 @@
 	bcm_board_detect();
 #ifdef DRIVER_EMMC_ENABLE
 	/* Initialize the card, if it is not */
-	if (bcm_emmc_init(true) < 0)
+	if (bcm_emmc_init(true) == 0)
 		WARN("eMMC Card Initialization Failed!!!\n");
 #endif
 
diff --git a/plat/brcm/board/stingray/src/paxb.c b/plat/brcm/board/stingray/src/paxb.c
index 28065f0..89f76d0 100644
--- a/plat/brcm/board/stingray/src/paxb.c
+++ b/plat/brcm/board/stingray/src/paxb.c
@@ -485,7 +485,7 @@
  */
 static int pcie_cores_init(void)
 {
-	int ret;
+	int ret = 0;
 	uint32_t core_idx;
 
 	if (paxb->pipemux_init) {