commit ed6dc9bc8c6b9f638676728e0bc8c1c115b141ae
author Biwen Li <biwen.li@nxp.com> Tue Jan 05 14:58:57 2021 +0800
committer Jiafei Pan <Jiafei.Pan@nxp.com> Sun Mar 27 23:24:24 2022 +0800
tree 5f4d951b98a8e41a9fe038831d0d3571830c9707
parent 150a71ef01c1d8ed2b918caf1e9ae6e401b15c67

feat(nxp-dcfg): add Chassis 3 support

Add support for Chassis 3.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I85cf68d4f1db81bf344e34dce13799ae173aa23a

drivers/nxp/dcfg/dcfg.c

diff --git a/drivers/nxp/dcfg/dcfg.c b/drivers/nxp/dcfg/dcfg.c
index a988c5d..e5c4db4 100644
--- a/drivers/nxp/dcfg/dcfg.c
+++ b/drivers/nxp/dcfg/dcfg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2022 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -74,14 +74,11 @@
 
 	reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET);
 
-#if defined(CONFIG_CHASSIS_3_2)
 	devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
+#if defined(CONFIG_CHASSIS_3_2)
 	devdisr5_info.ddrc2_present = (reg & DISR5_DDRC2_MASK) ? 0 : 1;
-	devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
-#elif defined(CONFIG_CHASSIS_2)
-	devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
-	devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
 #endif
+	devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
 	devdisr5_info.is_populated = true;
 
 	return (const devdisr5_info_t *) &devdisr5_info;

include/drivers/nxp/dcfg/dcfg.h

diff --git a/include/drivers/nxp/dcfg/dcfg.h b/include/drivers/nxp/dcfg/dcfg.h
index 524450a..cf29b12 100644
--- a/include/drivers/nxp/dcfg/dcfg.h
+++ b/include/drivers/nxp/dcfg/dcfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2021 NXP
+ * Copyright 2018-2022 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -12,7 +12,7 @@
 
 #if defined(CONFIG_CHASSIS_2)
 #include <dcfg_lsch2.h>
-#elif defined(CONFIG_CHASSIS_3_2)
+#elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3)
 #include <dcfg_lsch3.h>
 #endif