diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index 9ccf90c..29bf6dd 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -236,7 +236,22 @@
 	set_pll_bypass(pll_id);
 }
 
-void plls_suspend(void)
+void disable_dvfs_plls(void)
+{
+	_pll_suspend(CPLL_ID);
+	_pll_suspend(NPLL_ID);
+	_pll_suspend(VPLL_ID);
+	_pll_suspend(GPLL_ID);
+	_pll_suspend(ABPLL_ID);
+	_pll_suspend(ALPLL_ID);
+}
+
+void disable_nodvfs_plls(void)
+{
+	_pll_suspend(PPLL_ID);
+}
+
+void plls_suspend_prepare(void)
 {
 	uint32_t i, pll_id;
 
@@ -251,14 +266,6 @@
 		slp_data.pmucru_clksel_con[i] =
 			mmio_read_32(PMUCRU_BASE +
 				     PMUCRU_CLKSEL_OFFSET + i * REG_SIZE);
-
-	_pll_suspend(CPLL_ID);
-	_pll_suspend(NPLL_ID);
-	_pll_suspend(VPLL_ID);
-	_pll_suspend(PPLL_ID);
-	_pll_suspend(GPLL_ID);
-	_pll_suspend(ABPLL_ID);
-	_pll_suspend(ALPLL_ID);
 }
 
 void clk_gate_con_save(void)
@@ -308,7 +315,13 @@
 			      PLL_NO_BYPASS_MODE);
 }
 
+static void _pll_resume(uint32_t pll_id)
+{
+	set_plls_nobypass(pll_id);
+	set_pll_normal_mode(pll_id);
+}
+
-static void plls_resume_prepare(void)
+void plls_resume_finish(void)
 {
 	int i;
 
@@ -321,15 +334,19 @@
 			      REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]);
 }
 
-void plls_resume(void)
+void enable_dvfs_plls(void)
 {
-	int pll_id;
+	_pll_resume(ALPLL_ID);
+	_pll_resume(ABPLL_ID);
+	_pll_resume(GPLL_ID);
+	_pll_resume(VPLL_ID);
+	_pll_resume(NPLL_ID);
+	_pll_resume(CPLL_ID);
+}
 
-	plls_resume_prepare();
-	for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) {
-		set_plls_nobypass(pll_id);
-		set_pll_normal_mode(pll_id);
-	}
+void enable_nodvfs_plls(void)
+{
+	_pll_resume(PPLL_ID);
 }
 
 void soc_global_soft_reset_init(void)
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.h b/plat/rockchip/rk3399/drivers/soc/soc.h
index 26c0df6..1ea6e5e 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.h
+++ b/plat/rockchip/rk3399/drivers/soc/soc.h
@@ -240,6 +240,22 @@
 #define CPU_BOOT_ADDR_WMASK	0xffff0000
 #define CPU_BOOT_ADDR_ALIGN	16
 
+#define GRF_IOMUX_2BIT_MASK     0x3
+#define GRF_IOMUX_GPIO          0x0
+
+#define GRF_GPIO4C2_IOMUX_SHIFT         4
+#define GRF_GPIO4C2_IOMUX_PWM           0x1
+#define GRF_GPIO4C6_IOMUX_SHIFT         12
+#define GRF_GPIO4C6_IOMUX_PWM           0x1
+
+#define PWM_CNT(n)			(0x0000 + 0x10 * (n))
+#define PWM_PERIOD_HPR(n)		(0x0004 + 0x10 * (n))
+#define PWM_DUTY_LPR(n)			(0x0008 + 0x10 * (n))
+#define PWM_CTRL(n)			(0x000c + 0x10 * (n))
+
+#define PWM_DISABLE			(0 << 0)
+#define PWM_ENABLE			(1 << 0)
+
 /*
  * When system reset in running state, we want the cpus to be reboot
  * from maskrom (system reboot),
@@ -263,8 +279,12 @@
 
 /* funciton*/
 void __dead2 soc_global_soft_reset(void);
-void plls_resume(void);
-void plls_suspend(void);
+void plls_suspend_prepare(void);
+void disable_dvfs_plls(void);
+void disable_nodvfs_plls(void);
+void plls_resume_finish(void);
+void enable_dvfs_plls(void);
+void enable_nodvfs_plls(void);
 void clk_gate_con_save(void);
 void clk_gate_con_disable(void);
 void clk_gate_con_restore(void);