| commit | 8560672b90718b551912871f618a430f41495b86 | [log] [tgz] |
|---|---|---|
| author | Sieu Mun Tang <sieu.mun.tang@intel.com> | Tue Aug 27 00:01:51 2024 +0800 |
| committer | Tang Sieu Mun <sieu.mun.tang@intel.com> | Wed Oct 09 20:04:16 2024 +0200 |
| tree | 76b7f2c7e2b72aec0bc5cdf437e7b40a18b14e3d | |
| parent | 7bb345c386040fa960c668bb38703cc2feb67118 [diff] |
fix(intel): update Agilex5 BL2 init flow and other misc changes BL2: Update BL2 init flow, Timer base address, avoid cache flush of BL2 image descriptors BL31: Remove re-init of CCU and other misc updates Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>