Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c
index a139f6c..2adfe17 100644
--- a/drivers/arm/cci/cci.c
+++ b/drivers/arm/cci/cci.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -52,11 +52,11 @@
return false;
}
- if ((valid_cci_map & (1U << slave_if_id)) != 0U) {
+ if ((valid_cci_map & (1UL << slave_if_id)) != 0U) {
ERROR("Multiple masters are assigned same slave interface ID\n");
return false;
}
- valid_cci_map |= 1U << slave_if_id;
+ valid_cci_map |= 1UL << slave_if_id;
}
if (valid_cci_map == 0U) {
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index 50d6701..95a5e7f 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -91,9 +91,9 @@
open_status = get_gate_keeper_os(base);
if (val != 0)
- open_status |= (1U << filter);
+ open_status |= (1UL << filter);
else
- open_status &= ~(1U << filter);
+ open_status &= ~(1UL << filter);
_tzc400_write_gate_keeper(base, (open_status & GATE_KEEPER_OR_MASK) <<
GATE_KEEPER_OR_SHIFT);
diff --git a/drivers/arm/tzc/tzc_common_private.h b/drivers/arm/tzc/tzc_common_private.h
index c800536..1d99077 100644
--- a/drivers/arm/tzc/tzc_common_private.h
+++ b/drivers/arm/tzc/tzc_common_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,13 +30,13 @@
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
- region_no) + \
+ (u_register_t)region_no) + \
TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \
(uint32_t)region_base); \
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
- region_no) + \
+ (u_register_t)region_no) + \
TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \
(uint32_t)(region_base >> 32)); \
}
@@ -48,15 +48,15 @@
unsigned long long region_top) \
{ \
mmio_write_32(base + \
- TZC_REGION_OFFSET \
- (TZC_##macro_name##_REGION_SIZE, \
- region_no) + \
+ TZC_REGION_OFFSET( \
+ TZC_##macro_name##_REGION_SIZE, \
+ (u_register_t)region_no) + \
TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \
(uint32_t)region_top); \
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
- region_no) + \
+ (u_register_t)region_no) + \
TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \
(uint32_t)(region_top >> 32)); \
}
@@ -70,7 +70,7 @@
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
- region_no) + \
+ (u_register_t)region_no) + \
TZC_##macro_name##_REGION_ATTR_0_OFFSET, \
attr); \
}
@@ -84,7 +84,7 @@
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
- region_no) + \
+ (u_register_t)region_no) + \
TZC_##macro_name##_REGION_ID_ACCESS_0_OFFSET, \
val); \
}