tree f9c716ef9c67d9310eae029574b9c0bb8b5da3d5
parent 63d52341b6e2727a08761e1c8270f837845aec4d
author Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> 1536060805 +0530
committer Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> 1536060805 +0530

zynqmp: pm_service: Add support for resetting ULPI transceiver

To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's
are controlled by BOOT_PIN_CTRL register present in CRL_APB
address region. Since CRL_APB can be resticted to secure access,
this pin should be controlled by ATF.

This patch adds the support for the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>