commit ecb05e90f7a774aff9a3f1e4544bc23f3feeb8fb
author Jeenu Viswambharan <jeenu.viswambharan@arm.com> Fri Sep 29 11:14:02 2017 +0100
committer Jeenu Viswambharan <jeenu.viswambharan@arm.com> Mon Oct 16 16:50:02 2017 +0100
tree 220ad0205924399101ec8ebd6b917609274de1a5
parent 723dce09733e042582a9ad34b982b3b25f59a2ca

uniphier: Migrate to using interrupt properties

Change-Id: I795ec540942130b5ddc0fa1fd7167f7e1d1ae967
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

plat/socionext/uniphier/uniphier_gicv3.c

diff --git a/plat/socionext/uniphier/uniphier_gicv3.c b/plat/socionext/uniphier/uniphier_gicv3.c
index 05a4e35..93bc73a 100644
--- a/plat/socionext/uniphier/uniphier_gicv3.c
+++ b/plat/socionext/uniphier/uniphier_gicv3.c
@@ -6,6 +6,7 @@
 
 #include <assert.h>
 #include <gicv3.h>
+#include <interrupt_props.h>
 #include <platform.h>
 #include <platform_def.h>
 
@@ -13,19 +14,39 @@
 
 static uintptr_t uniphier_rdistif_base_addrs[PLATFORM_CORE_COUNT];
 
-static const unsigned int g0_interrupt_array[] = {
-	8,	/* SGI0 */
-	14,	/* SGI6 */
-};
+static const interrupt_prop_t uniphier_interrupt_props[] = {
+	/* G0 interrupts */
+
+	/* SGI0 */
+	INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
+			GIC_INTR_CFG_EDGE),
+	/* SGI6 */
+	INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
+			GIC_INTR_CFG_EDGE),
 
-static const unsigned int g1s_interrupt_array[] = {
-	29,	/* Timer */
-	9,	/* SGI1 */
-	10,	/* SGI2 */
-	11,	/* SGI3 */
-	12,	/* SGI4 */
-	13,	/* SGI5 */
-	15,	/* SGI7 */
+	/* G1S interrupts */
+
+	/* Timer */
+	INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
+			GIC_INTR_CFG_LEVEL),
+	/* SGI1 */
+	INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
+			GIC_INTR_CFG_EDGE),
+	/* SGI2 */
+	INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
+			GIC_INTR_CFG_EDGE),
+	/* SGI3 */
+	INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
+			GIC_INTR_CFG_EDGE),
+	/* SGI4 */
+	INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
+			GIC_INTR_CFG_EDGE),
+	/* SGI5 */
+	INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
+			GIC_INTR_CFG_EDGE),
+	/* SGI7 */
+	INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
+			GIC_INTR_CFG_EDGE)
 };
 
 static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
@@ -37,10 +58,8 @@
 	[UNIPHIER_SOC_LD11] = {
 		.gicd_base = 0x5fe00000,
 		.gicr_base = 0x5fe40000,
-		.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
-		.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
-		.g0_interrupt_array = g0_interrupt_array,
-		.g1s_interrupt_array = g1s_interrupt_array,
+		.interrupt_props = uniphier_interrupt_props,
+		.interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
 		.rdistif_num = PLATFORM_CORE_COUNT,
 		.rdistif_base_addrs = uniphier_rdistif_base_addrs,
 		.mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
@@ -48,10 +67,8 @@
 	[UNIPHIER_SOC_LD20] = {
 		.gicd_base = 0x5fe00000,
 		.gicr_base = 0x5fe80000,
-		.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
-		.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
-		.g0_interrupt_array = g0_interrupt_array,
-		.g1s_interrupt_array = g1s_interrupt_array,
+		.interrupt_props = uniphier_interrupt_props,
+		.interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
 		.rdistif_num = PLATFORM_CORE_COUNT,
 		.rdistif_base_addrs = uniphier_rdistif_base_addrs,
 		.mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
@@ -59,10 +76,8 @@
 	[UNIPHIER_SOC_PXS3] = {
 		.gicd_base = 0x5fe00000,
 		.gicr_base = 0x5fe80000,
-		.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
-		.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
-		.g0_interrupt_array = g0_interrupt_array,
-		.g1s_interrupt_array = g1s_interrupt_array,
+		.interrupt_props = uniphier_interrupt_props,
+		.interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
 		.rdistif_num = PLATFORM_CORE_COUNT,
 		.rdistif_base_addrs = uniphier_rdistif_base_addrs,
 		.mpidr_to_core_pos = uniphier_mpidr_to_core_pos,