Merge pull request #1017 from etienne-lms/minor-docs
Minor docs
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 45b0213..d8fbb9b 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -49,7 +49,8 @@
b.eq smc_handler64
/* Other kinds of synchronous exceptions are not handled */
- no_ret report_unhandled_exception
+ ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
+ b report_unhandled_exception
.endm
@@ -152,7 +153,7 @@
*/
vector_entry sync_exception_sp_el0
/* We don't expect any synchronous exceptions from EL3 */
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size sync_exception_sp_el0
vector_entry irq_sp_el0
@@ -160,17 +161,17 @@
* EL3 code is non-reentrant. Any asynchronous exception is a serious
* error. Loop infinitely.
*/
- no_ret report_unhandled_interrupt
+ b report_unhandled_interrupt
check_vector_size irq_sp_el0
vector_entry fiq_sp_el0
- no_ret report_unhandled_interrupt
+ b report_unhandled_interrupt
check_vector_size fiq_sp_el0
vector_entry serror_sp_el0
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size serror_sp_el0
/* ---------------------------------------------------------------------
@@ -184,19 +185,19 @@
* synchronous exception. There is a high probability that SP_EL3 is
* corrupted.
*/
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size sync_exception_sp_elx
vector_entry irq_sp_elx
- no_ret report_unhandled_interrupt
+ b report_unhandled_interrupt
check_vector_size irq_sp_elx
vector_entry fiq_sp_elx
- no_ret report_unhandled_interrupt
+ b report_unhandled_interrupt
check_vector_size fiq_sp_elx
vector_entry serror_sp_elx
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size serror_sp_elx
/* ---------------------------------------------------------------------
@@ -226,7 +227,7 @@
* SError exceptions from lower ELs are not currently supported.
* Report their occurrence.
*/
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size serror_aarch64
/* ---------------------------------------------------------------------
@@ -256,7 +257,7 @@
* SError exceptions from lower ELs are not currently supported.
* Report their occurrence.
*/
- no_ret report_unhandled_exception
+ b report_unhandled_exception
check_vector_size serror_aarch32
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index 2c32578..489183c 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -43,10 +43,7 @@
msr spsr_el1, \reg2
.endm
- .section .text, "ax"
- .align 3
-
-func tsp_entrypoint
+func tsp_entrypoint _align=3
/* ---------------------------------------------
* Set the exception vector to something sane.
diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S
index 96d958e..4b2ad75 100644
--- a/bl32/tsp/aarch64/tsp_exceptions.S
+++ b/bl32/tsp/aarch64/tsp_exceptions.S
@@ -81,19 +81,19 @@
* -----------------------------------------------------
*/
vector_entry sync_exception_sp_el0
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size sync_exception_sp_el0
vector_entry irq_sp_el0
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size irq_sp_el0
vector_entry fiq_sp_el0
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size fiq_sp_el0
vector_entry serror_sp_el0
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size serror_sp_el0
@@ -103,7 +103,7 @@
* -----------------------------------------------------
*/
vector_entry sync_exception_sp_elx
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size sync_exception_sp_elx
vector_entry irq_sp_elx
@@ -115,7 +115,7 @@
check_vector_size fiq_sp_elx
vector_entry serror_sp_elx
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size serror_sp_elx
@@ -125,19 +125,19 @@
* -----------------------------------------------------
*/
vector_entry sync_exception_aarch64
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size sync_exception_aarch64
vector_entry irq_aarch64
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size irq_aarch64
vector_entry fiq_aarch64
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size fiq_aarch64
vector_entry serror_aarch64
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size serror_aarch64
@@ -147,17 +147,17 @@
* -----------------------------------------------------
*/
vector_entry sync_exception_aarch32
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size sync_exception_aarch32
vector_entry irq_aarch32
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size irq_aarch32
vector_entry fiq_aarch32
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size fiq_aarch32
vector_entry serror_aarch32
- no_ret plat_panic_handler
+ b plat_panic_handler
check_vector_size serror_aarch32
diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S
index 2e60bd5..583ee4a 100644
--- a/common/aarch32/debug.S
+++ b/common/aarch32/debug.S
@@ -51,7 +51,7 @@
1:
mov lr, r6
- no_ret plat_panic_handler
+ b plat_panic_handler
endfunc do_panic
/***********************************************************
diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S
index fe6a9a2..d794d12 100644
--- a/common/aarch64/debug.S
+++ b/common/aarch64/debug.S
@@ -175,6 +175,6 @@
_panic_handler:
/* Pass to plat_panic_handler the address from where el3_panic was
* called, not the address of the call from el3_panic. */
- mov x30,x6
- no_ret plat_panic_handler
+ mov x30, x6
+ b plat_panic_handler
endfunc do_panic
diff --git a/include/common/asm_macros_common.S b/include/common/asm_macros_common.S
index b529246..dbc9e2d 100644
--- a/include/common/asm_macros_common.S
+++ b/include/common/asm_macros_common.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,9 +11,12 @@
* code into a separate text section based on the function name
* to enable elimination of unused code during linking. It also adds
* basic debug information to enable call stack printing most of the
- * time.
+ * time. The optional _align parameter can be used to force a
+ * non-standard alignment (indicated in powers of 2). Do *not* try to
+ * use a raw .align directive. Since func switches to a new section,
+ * this would not have the desired effect.
*/
- .macro func _name
+ .macro func _name, _align=-1
/*
* Add Call Frame Information entry in the .debug_frame section for
* debugger consumption. This enables callstack printing in debuggers.
@@ -33,6 +36,9 @@
* .debug_frame
*/
.cfi_startproc
+ .if (\_align) != -1
+ .align \_align
+ .endif
\_name:
.endm
diff --git a/plat/hisilicon/hikey/hisi_pwrc_sram.S b/plat/hisilicon/hikey/hisi_pwrc_sram.S
index 1fb63ea..f9e1de4 100644
--- a/plat/hisilicon/hikey/hisi_pwrc_sram.S
+++ b/plat/hisilicon/hikey/hisi_pwrc_sram.S
@@ -15,8 +15,7 @@
.global v7_asm
.global v7_asm_end
- .align 3
-func pm_asm_code
+func pm_asm_code _align=3
mov x0, 0
msr oslar_el1, x0
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index e5e5126..691b90a 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -307,8 +307,7 @@
* Secure entrypoint function for CPU boot
* ----------------------------------------
*/
- .align 6
-func tegra_secure_entrypoint
+func tegra_secure_entrypoint _align=6
#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT
diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index 4841aa2..6a17c33 100644
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -12,11 +12,10 @@
#define TEGRA186_SMMU_CTX_SIZE 0x420
- .align 4
.globl tegra186_cpu_reset_handler
/* CPU reset handler routine */
-func tegra186_cpu_reset_handler
+func tegra186_cpu_reset_handler _align=4
/*
* The TZRAM loses state during System Suspend. We use this
* information to decide if the reset handler is running after a
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index 1c8aefc..abfb5a7 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -112,8 +112,7 @@
* cpus online or resume enterpoint
* --------------------------------------------------------------------
*/
- .align 16
-func platform_cpu_warmboot
+func platform_cpu_warmboot _align=16
mrs x0, MPIDR_EL1
and x19, x0, #MPIDR_CPU_MASK
and x20, x0, #MPIDR_CLUSTER_MASK