feat(tc): configure MCN rdalloc and wralloc mode
SLC WRALLOCMODE and RDALLOCMODE are configured by default to 0b01
(always alloc), configure both to mode 0b10 (use bus signal attribute
from interface).
Change-Id: Ic8cd3ee988dd0772cfb9b639dea0cc335ab70539
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 0eec795..38413ef 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -431,6 +431,19 @@
#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \
(n * MCN_ADDRESS_SPACE_SIZE) + \
MCN_PMU_OFFSET)
+#define MCN_MPAM_NS_OFFSET 0x000D0000
+#define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET)
+#define MCN_MPAM_S_OFFSET 0x000D4000
+#define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET)
+#define MPAM_SLCCFG_CTL_OFFSET 0x00003018
+#define SLC_RDALLOCMODE_SHIFT 8
+#define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT)
+#define SLC_WRALLOCMODE_SHIFT 12
+#define SLC_WRALLOCMODE_MASK (3 << SLC_WRALLOCMODE_SHIFT)
+
+#define SLC_DONT_ALLOC 0
+#define SLC_ALWAYS_ALLOC 1
+#define SLC_ALLOC_BUS_SIGNAL_ATTR 2
#endif /* TARGET_PLATFORM == 3 */
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index a5c931c..7d1bc9c 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -78,6 +78,30 @@
mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT);
}
}
+
+static void set_mcn_slc_alloc_mode(void)
+{
+ /*
+ * SLC WRALLOCMODE and RDALLOCMODE are configured by default to
+ * 0b01 (always alloc), configure both to 0b10 (use bus signal
+ * attribute from interface).
+ */
+ for (int i = 0; i < MCN_INSTANCES; i++) {
+ uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR +
+ (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
+ uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR +
+ (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
+
+ mmio_clrsetbits_32(slccfg_ctl_ns,
+ (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
+ (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
+ (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
+ mmio_clrsetbits_32(slccfg_ctl_s,
+ (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
+ (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
+ (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
+ }
+}
#endif
void bl31_platform_setup(void)
@@ -85,6 +109,7 @@
tc_bl31_common_platform_setup();
#if TARGET_PLATFORM == 3
enable_ns_mcn_pmu();
+ set_mcn_slc_alloc_mode();
#endif
}