Merge changes from topic "renaming_daniel" into integration
* changes:
plat/arm: rename rddanielxlr to rdv1mc
plat/arm: rename rddaniel to rdv1
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index d1995e3..4c1a80e 100644
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -105,15 +105,15 @@
cmp w0, #0xA
b.ne 2f
1:
- /* Check if the transmit FIFO is full */
+ /* Check if the transmit FIFO is empty */
ldr w2, [x1, #R_UART_SR]
- tbnz w2, #UART_SR_INTR_TFUL_BIT, 1b
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, 1b
mov w2, #0xD
str w2, [x1, #R_UART_TX]
2:
- /* Check if the transmit FIFO is full */
+ /* Check if the transmit FIFO is empty */
ldr w2, [x1, #R_UART_SR]
- tbnz w2, #UART_SR_INTR_TFUL_BIT, 2b
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, 2b
str w0, [x1, #R_UART_TX]
ret
endfunc console_cdns_core_putc
diff --git a/drivers/renesas/rcar/auth/auth_mod.c b/drivers/renesas/rcar/auth/auth_mod.c
index ece3462..4aa86e2 100644
--- a/drivers/renesas/rcar/auth/auth_mod.c
+++ b/drivers/renesas/rcar/auth/auth_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -7,29 +7,28 @@
#include <stddef.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
#include "rom_api.h"
typedef int32_t(*secure_boot_api_f) (uint32_t a, uint32_t b, void *c);
extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert_addr);
-#define RCAR_IMAGE_ID_MAX (10)
-#define RCAR_CERT_MAGIC_NUM (0xE291F358U)
+#define RCAR_IMAGE_ID_MAX (10)
+#define RCAR_CERT_MAGIC_NUM (0xE291F358U)
#define RCAR_BOOT_KEY_CERT (0xE6300C00U)
#define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U)
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-#define MFISOFTMDR (0xE6260600U)
-#define MODEMR_MD5_MASK (0x00000020U)
-#define MODEMR_MD5_SHIFT (5U)
-#define SOFTMD_BOOTMODE_MASK (0x00000001U)
-#define SOFTMD_NORMALBOOT (0x1U)
+#define RST_BASE (0xE6160000U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
+#define MFISOFTMDR (0xE6260600U)
+#define MODEMR_MD5_MASK (0x00000020U)
+#define MODEMR_MD5_SHIFT (5U)
+#define SOFTMD_BOOTMODE_MASK (0x00000001U)
+#define SOFTMD_NORMALBOOT (0x1U)
static secure_boot_api_f secure_boot_api;
@@ -125,9 +124,9 @@
#if RCAR_BL2_DCACHE == 1
/* enable */
write_sctlr_el3(read_sctlr_el3() | SCTLR_C_BIT);
-#endif
+#endif /* RCAR_BL2_DCACHE */
-#endif
+#endif /* IMAGE_BL2 */
return ret;
}
diff --git a/drivers/renesas/rcar/avs/avs_driver.c b/drivers/renesas/rcar/avs/avs_driver.c
index 647869e..2c939cd 100644
--- a/drivers/renesas/rcar/avs/avs_driver.c
+++ b/drivers/renesas/rcar/avs/avs_driver.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,8 +8,8 @@
#include <lib/mmio.h>
#include <lib/utils_def.h>
-#include "cpg_registers.h"
#include "avs_driver.h"
+#include "cpg_registers.h"
#include "rcar_def.h"
#include "rcar_private.h"
@@ -22,12 +22,12 @@
#endif /* PMIC_ROHM_BD9571 */
/* Base address of Adaptive Voltage Scaling module registers*/
-#define AVS_BASE (0xE60A0000U)
+#define AVS_BASE (0xE60A0000U)
/* Adaptive Dynamic Voltage ADJust Parameter2 registers */
-#define ADVADJP2 (AVS_BASE + 0x013CU)
+#define ADVADJP2 (AVS_BASE + 0x013CU)
/* Mask VOLCOND bit in ADVADJP2 registers */
-#define ADVADJP2_VOLCOND_MASK (0x000001FFU) /* VOLCOND[8:0] */
+#define ADVADJP2_VOLCOND_MASK (0x000001FFU) /* VOLCOND[8:0] */
#if PMIC_ROHM_BD9571
/* I2C for DVFS bit in CPG registers for module standby and software reset*/
@@ -38,19 +38,19 @@
#if PMIC_ROHM_BD9571
/* Base address of IICDVFS registers*/
-#define IIC_DVFS_BASE (0xE60B0000U)
+#define IIC_DVFS_BASE (0xE60B0000U)
/* IIC bus data register */
-#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U)
+#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U)
/* IIC bus control register */
-#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U)
+#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U)
/* IIC bus status register */
-#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U)
+#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U)
/* IIC interrupt control register */
-#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU)
+#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU)
/* IIC clock control register low */
-#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U)
+#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U)
/* IIC clock control register high */
-#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U)
+#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U)
/* Bit in ICSR register */
#define ICSR_BUSY (0x10U)
@@ -76,20 +76,23 @@
#define ICCR_STOP_RECV (0xC0U)
/* Low-level period of SCL */
-#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */
-#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */
-#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */
-#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */
+#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */
+#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */
+#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */
+#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */
/* High-level period of SCL */
-#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */
-#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */
-#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */
-#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */
+#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */
+#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */
+#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */
+#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */
/* PMIC */
-#define PMIC_W_SLAVE_ADDRESS (0x60U) /* ROHM BD9571 slave address + (W) */
-#define PMIC_R_SLAVE_ADDRESS (0x61U) /* ROHM BD9571 slave address + (R) */
-#define PMIC_DVFS_SETVID (0x54U) /* ROHM BD9571 DVFS SetVID register */
+/* ROHM BD9571 slave address + (W) */
+#define PMIC_W_SLAVE_ADDRESS (0x60U)
+/* ROHM BD9571 slave address + (R) */
+#define PMIC_R_SLAVE_ADDRESS (0x61U)
+/* ROHM BD9571 DVFS SetVID register */
+#define PMIC_DVFS_SETVID (0x54U)
#endif /* PMIC_ROHM_BD9571 */
/* Individual information */
@@ -102,7 +105,7 @@
} initial_voltage_t;
static const initial_voltage_t init_vol_tbl[] = {
- /* AVS code, RHOM BD9571 DVFS SetVID register */
+ /* AVS code, ROHM BD9571 DVFS SetVID register */
{0x00U, 0x53U}, /* AVS0, 0.83V */
{0x01U, 0x52U}, /* AVS1, 0.82V */
{0x02U, 0x51U}, /* AVS2, 0.81V */
@@ -188,7 +191,7 @@
/* Disable I2C module and All internal registers initialized. */
mmio_write_8(IIC_ICCR, 0x00U);
while ((mmio_read_8(IIC_ICCR) & ICCR_ENABLE) != 0U) {
- /* Disable I2C module and All internal registers initialized. */
+ /* Disable I2C module and all internal registers initialized. */
mmio_write_8(IIC_ICCR, 0x00U);
}
@@ -283,8 +286,8 @@
/* Dose efuse_avs exceed the number of */
/* the tables? */
if (efuse_avs >= EFUSE_AVS_NUM) {
- ERROR("AVS number of eFuse is out "
- "of a range. number=%u\n",
+ ERROR("%s%s=%u\n", "AVS number of ",
+ "eFuse is out of range. number",
efuse_avs);
/* Infinite loop */
panic();
@@ -417,7 +420,8 @@
{
uint8_t addr = PMIC_DVFS_SETVID;
uint8_t value = avs_read_pmic_reg(addr);
- NOTICE("Read PMIC register. address=0x%x value=0x%x \n",
+
+ NOTICE("Read PMIC register. address=0x%x value=0x%x\n",
addr, value);
}
#endif
@@ -446,8 +450,8 @@
avs_error_t ret;
if ((mmio_read_8(IIC_ICSR) & ICSR_AL) == ICSR_AL) {
- NOTICE("Loss of arbitration is detected. "
- "AVS status=%d Retry=%u\n", avs_status, avs_retry);
+ NOTICE("%s AVS status=%d Retry=%u\n",
+ "Loss of arbitration is detected.", avs_status, avs_retry);
/* Check of retry number of times */
if (avs_retry >= AVS_RETRY_NUM) {
ERROR("AVS setting failed in retry. max=%u\n",
@@ -458,8 +462,8 @@
/* Set the error detected to error status. */
ret = avs_error_al;
} else if ((mmio_read_8(IIC_ICSR) & ICSR_TACK) == ICSR_TACK) {
- NOTICE("Non-acknowledge is detected. "
- "AVS status=%d Retry=%u\n", avs_status, avs_retry);
+ NOTICE("%s AVS status=%d Retry=%u\n",
+ "Non-acknowledge is detected.", avs_status, avs_retry);
/* Check of retry number of times */
if (avs_retry >= AVS_RETRY_NUM) {
ERROR("AVS setting failed in retry. max=%u\n",
@@ -526,8 +530,10 @@
/* Set frequency of 400kHz */
avs_set_iic_clock();
- /* Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission */
- /* interrupt and wait interrupt. */
+ /*
+ * Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission
+ * interrupt and wait interrupt.
+ */
mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_WAITE | ICIC_DTEE);
/* Write H'94 in ICCR to issue start condition */
diff --git a/drivers/renesas/rcar/common.c b/drivers/renesas/rcar/common.c
index 42bdce5..9b7c1eb 100644
--- a/drivers/renesas/rcar/common.c
+++ b/drivers/renesas/rcar/common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,24 +8,27 @@
#include "rcar_private.h"
-void
#if IMAGE_BL31
- __attribute__ ((section(".system_ram")))
+void __attribute__ ((section(".system_ram"))) cpg_write(uintptr_t regadr, uint32_t regval)
+#else
+void cpg_write(uintptr_t regadr, uint32_t regval)
#endif
- cpg_write(uintptr_t regadr, uint32_t regval)
{
- uint32_t value = (regval);
+ uint32_t value = regval;
+
mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
mmio_write_32(regadr, value);
}
-void
#if IMAGE_BL31
- __attribute__ ((section(".system_ram")))
+void __attribute__ ((section(".system_ram"))) mstpcr_write(uint32_t mstpcr, uint32_t mstpsr,
+ uint32_t target_bit)
+#else
+void mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
#endif
- mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
{
uint32_t reg;
+
reg = mmio_read_32(mstpcr);
reg &= ~target_bit;
cpg_write(mstpcr, reg);
diff --git a/drivers/renesas/rcar/delay/micro_delay.c b/drivers/renesas/rcar/delay/micro_delay.c
index aced589..a5e2a69 100644
--- a/drivers/renesas/rcar/delay/micro_delay.c
+++ b/drivers/renesas/rcar/delay/micro_delay.c
@@ -1,18 +1,19 @@
/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
+
#include "micro_delay.h"
#define RCAR_CONV_MICROSEC 1000000U
void
#if IMAGE_BL31
- __attribute__ ((section (".system_ram")))
+ __attribute__ ((section(".system_ram")))
#endif
rcar_micro_delay(uint64_t micro_sec)
{
diff --git a/drivers/renesas/rcar/dma/dma_driver.c b/drivers/renesas/rcar/dma/dma_driver.c
index e0be46e..44ee985 100644
--- a/drivers/renesas/rcar/dma/dma_driver.c
+++ b/drivers/renesas/rcar/dma/dma_driver.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,15 +11,15 @@
#include <common/debug.h>
#include <lib/mmio.h>
-#include "rcar_def.h"
#include "cpg_registers.h"
+#include "rcar_def.h"
#include "rcar_private.h"
/* DMA CHANNEL setting (0/16/32) */
#if RCAR_LSI == RCAR_V3M
-#define DMA_CH 16
+#define DMA_CH 16
#else
-#define DMA_CH 0
+#define DMA_CH 0
#endif
#if (DMA_CH == 0)
@@ -39,7 +39,7 @@
/* DMA operation */
#define DMA_DMAOR (DMA_BASE + 0x0060U)
/* DMA secure control */
-#define DMA_DMASEC (DMA_BASE + 0x0030U)
+#define DMA_DMASEC (DMA_BASE + 0x0030U)
/* DMA channel clear */
#define DMA_DMACHCLR (DMA_BASE + 0x0080U)
/* DMA source address */
@@ -53,21 +53,21 @@
/* DMA fixed destination address */
#define DMA_DMAFIXDAR (DMA_BASE + 0x8014U)
-#define DMA_USE_CHANNEL (0x00000001U)
-#define DMAOR_INITIAL (0x0301U)
-#define DMACHCLR_CH_ALL (0x0000FFFFU)
-#define DMAFIXDAR_32BIT_SHIFT (32U)
-#define DMAFIXDAR_DAR_MASK (0x000000FFU)
-#define DMADAR_BOUNDARY_ADDR (0x100000000ULL)
-#define DMATCR_CNT_SHIFT (6U)
-#define DMATCR_MAX (0x00FFFFFFU)
-#define DMACHCR_TRN_MODE (0x00105409U)
-#define DMACHCR_DE_BIT (0x00000001U)
-#define DMACHCR_TE_BIT (0x00000002U)
-#define DMACHCR_CHE_BIT (0x80000000U)
+#define DMA_USE_CHANNEL (0x00000001U)
+#define DMAOR_INITIAL (0x0301U)
+#define DMACHCLR_CH_ALL (0x0000FFFFU)
+#define DMAFIXDAR_32BIT_SHIFT (32U)
+#define DMAFIXDAR_DAR_MASK (0x000000FFU)
+#define DMADAR_BOUNDARY_ADDR (0x100000000ULL)
+#define DMATCR_CNT_SHIFT (6U)
+#define DMATCR_MAX (0x00FFFFFFU)
+#define DMACHCR_TRN_MODE (0x00105409U)
+#define DMACHCR_DE_BIT (0x00000001U)
+#define DMACHCR_TE_BIT (0x00000002U)
+#define DMACHCR_CHE_BIT (0x80000000U)
-#define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT
-#define DMA_FRACTION_MASK (0xFFU)
+#define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT
+#define DMA_FRACTION_MASK (0xFFU)
#define DMA_DST_LIMIT (0x10000000000ULL)
/* transfer length limit */
@@ -129,16 +129,16 @@
}
if (src & DMA_FRACTION_MASK) {
- ERROR("BL2: DMA - source address invalid (0x%x), "
- "length (0x%x)\n", src, dma_len);
+ ERROR("BL2: DMA - src address invalid (0x%x), len=(0x%x)\n",
+ src, dma_len);
panic();
}
if ((dst & UINT32_MAX) + dma_len > DMADAR_BOUNDARY_ADDR ||
- (dst + dma_len > DMA_DST_LIMIT) ||
+ (dst + dma_len > DMA_DST_LIMIT) ||
(dst & DMA_FRACTION_MASK)) {
- ERROR("BL2: DMA - destination address invalid (0x%lx), "
- "length (0x%x)\n", dst, dma_len);
+ ERROR("BL2: DMA - dest address invalid (0x%lx), len=(0x%x)\n",
+ dst, dma_len);
panic();
}
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
index 28b56c1..e1c9a5b 100644
--- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
+++ b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,59 +7,59 @@
#include <common/debug.h>
#include <lib/mmio.h>
-#include "rcar_def.h"
#include "cpg_registers.h"
#include "iic_dvfs.h"
+#include "rcar_def.h"
#include "rcar_private.h"
#define DVFS_RETRY_MAX (2U)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0B)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0E)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07U)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09U)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0BU)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0EU)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15U)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07U)
-#define CPG_BIT_SMSTPCR9_DVFS (0x04000000)
+#define CPG_BIT_SMSTPCR9_DVFS (0x04000000U)
-#define IIC_DVFS_REG_BASE (0xE60B0000)
-#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000)
-#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004)
-#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008)
-#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000C)
-#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010)
-#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014)
+#define IIC_DVFS_REG_BASE (0xE60B0000U)
+#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000U)
+#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004U)
+#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008U)
+#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000CU)
+#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010U)
+#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014U)
-#define IIC_DVFS_BIT_ICSR_BUSY (0x10)
-#define IIC_DVFS_BIT_ICSR_AL (0x08)
-#define IIC_DVFS_BIT_ICSR_TACK (0x04)
-#define IIC_DVFS_BIT_ICSR_WAIT (0x02)
-#define IIC_DVFS_BIT_ICSR_DTE (0x01)
+#define IIC_DVFS_BIT_ICSR_BUSY (0x10U)
+#define IIC_DVFS_BIT_ICSR_AL (0x08U)
+#define IIC_DVFS_BIT_ICSR_TACK (0x04U)
+#define IIC_DVFS_BIT_ICSR_WAIT (0x02U)
+#define IIC_DVFS_BIT_ICSR_DTE (0x01U)
-#define IIC_DVFS_BIT_ICCR_ENABLE (0x80)
-#define IIC_DVFS_SET_ICCR_START (0x94)
-#define IIC_DVFS_SET_ICCR_STOP (0x90)
-#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94)
-#define IIC_DVFS_SET_ICCR_CHANGE (0x81)
-#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0)
+#define IIC_DVFS_BIT_ICCR_ENABLE (0x80U)
+#define IIC_DVFS_SET_ICCR_START (0x94U)
+#define IIC_DVFS_SET_ICCR_STOP (0x90U)
+#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94U)
+#define IIC_DVFS_SET_ICCR_CHANGE (0x81U)
+#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0U)
-#define IIC_DVFS_BIT_ICIC_TACKE (0x04)
-#define IIC_DVFS_BIT_ICIC_WAITE (0x02)
-#define IIC_DVFS_BIT_ICIC_DTEE (0x01)
+#define IIC_DVFS_BIT_ICIC_TACKE (0x04U)
+#define IIC_DVFS_BIT_ICIC_WAITE (0x02U)
+#define IIC_DVFS_BIT_ICIC_DTEE (0x01U)
-#define DVFS_READ_MODE (0x01)
-#define DVFS_WRITE_MODE (0x00)
+#define DVFS_READ_MODE (0x01U)
+#define DVFS_WRITE_MODE (0x00U)
-#define IIC_DVFS_SET_DUMMY (0x52)
+#define IIC_DVFS_SET_DUMMY (0x52U)
#define IIC_DVFS_SET_BUSY_LOOP (500000000U)
-typedef enum {
+enum dvfs_state_t {
DVFS_START = 0,
DVFS_STOP,
DVFS_RETRANSMIT,
@@ -69,9 +69,9 @@
DVFS_SET_SLAVE,
DVFS_WRITE_ADDR,
DVFS_WRITE_DATA,
- DVFS_CHANGE_SEND_TO_RECIEVE,
+ DVFS_CHANGE_SEND_TO_RECEIVE,
DVFS_DONE,
-} DVFS_STATE_T;
+};
#define DVFS_PROCESS (1)
#define DVFS_COMPLETE (0)
@@ -79,26 +79,26 @@
#if IMAGE_BL31
#define IIC_DVFS_FUNC(__name, ...) \
-static int32_t __attribute__ ((section (".system_ram"))) \
+static int32_t __attribute__ ((section(".system_ram"))) \
dvfs_ ##__name(__VA_ARGS__)
#define RCAR_DVFS_API(__name, ...) \
-int32_t __attribute__ ((section (".system_ram"))) \
+int32_t __attribute__ ((section(".system_ram"))) \
rcar_iic_dvfs_ ##__name(__VA_ARGS__)
#else
-#define IIC_DVFS_FUNC(__name, ...) \
+#define IIC_DVFS_FUNC(__name, ...) \
static int32_t dvfs_ ##__name(__VA_ARGS__)
#define RCAR_DVFS_API(__name, ...) \
int32_t rcar_iic_dvfs_ ##__name(__VA_ARGS__)
#endif
-IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
+IIC_DVFS_FUNC(check_error, enum dvfs_state_t *state, uint32_t *err, uint8_t mode)
{
- uint8_t icsr_al = 0, icsr_tack = 0;
+ uint8_t icsr_al = 0U, icsr_tack = 0U;
uint8_t reg, stop;
- uint32_t i = 0;
+ uint32_t i = 0U;
stop = mode == DVFS_READ_MODE ? IIC_DVFS_SET_ICCR_STOP_READ :
IIC_DVFS_SET_ICCR_STOP;
@@ -107,43 +107,48 @@
icsr_al = (reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL;
icsr_tack = (reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK;
- if (icsr_al == 0 && icsr_tack == 0)
+ if (icsr_al == 0U && icsr_tack == 0U) {
return DVFS_PROCESS;
+ }
if (icsr_al) {
reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_AL;
mmio_write_8(IIC_DVFS_REG_ICSR, reg);
- if (*state == DVFS_SET_SLAVE)
+ if (*state == DVFS_SET_SLAVE) {
mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY);
+ }
do {
reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
IIC_DVFS_BIT_ICSR_WAIT;
- } while (reg == 0);
+ } while (reg == 0U);
mmio_write_8(IIC_DVFS_REG_ICCR, stop);
reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
mmio_write_8(IIC_DVFS_REG_ICSR, reg);
- i = 0;
+ i = 0U;
do {
reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
IIC_DVFS_BIT_ICSR_BUSY;
- if (reg == 0)
+ if (reg == 0U) {
break;
+ }
- if (i++ > IIC_DVFS_SET_BUSY_LOOP)
+ if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
panic();
+ }
- } while (1);
+ } while (true);
mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U);
(*err)++;
- if (*err > DVFS_RETRY_MAX)
+ if (*err > DVFS_RETRY_MAX) {
return DVFS_ERROR;
+ }
*state = DVFS_START;
@@ -161,24 +166,26 @@
reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_TACK;
mmio_write_8(IIC_DVFS_REG_ICSR, reg);
- i = 0;
- while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0) {
- if (i++ > IIC_DVFS_SET_BUSY_LOOP)
+ i = 0U;
+ while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
+ if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
panic();
+ }
}
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
(*err)++;
- if (*err > DVFS_RETRY_MAX)
+ if (*err > DVFS_RETRY_MAX) {
return DVFS_ERROR;
+ }
*state = DVFS_START;
return DVFS_PROCESS;
}
-IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
+IIC_DVFS_FUNC(start, enum dvfs_state_t *state)
{
uint8_t iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_E;
uint8_t icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_E;
@@ -190,8 +197,9 @@
mmio_write_8(IIC_DVFS_REG_ICCR, mode);
lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
- if (lsi_product == PRR_PRODUCT_E3)
+ if (lsi_product == PRR_PRODUCT_E3) {
goto start;
+ }
reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
switch (reg) {
@@ -228,19 +236,21 @@
return result;
}
-IIC_DVFS_FUNC(set_slave, DVFS_STATE_T * state, uint32_t *err, uint8_t slave)
+IIC_DVFS_FUNC(set_slave, enum dvfs_state_t *state, uint32_t *err, uint8_t slave)
{
uint8_t mode;
int32_t result;
uint8_t address;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
- if (mode != IIC_DVFS_BIT_ICSR_DTE)
+ if (mode != IIC_DVFS_BIT_ICSR_DTE) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
@@ -253,18 +263,20 @@
return result;
}
-IIC_DVFS_FUNC(write_addr, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_addr)
+IIC_DVFS_FUNC(write_addr, enum dvfs_state_t *state, uint32_t *err, uint8_t reg_addr)
{
uint8_t mode;
int32_t result;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
@@ -276,18 +288,21 @@
return result;
}
-IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data)
+IIC_DVFS_FUNC(write_data, enum dvfs_state_t *state, uint32_t *err,
+ uint8_t reg_data)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICDR, reg_data);
@@ -299,18 +314,20 @@
return result;
}
-IIC_DVFS_FUNC(stop, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(stop, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP);
@@ -326,32 +343,35 @@
{
uint32_t i;
- for (i = 0; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
- if (mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY)
+ for (i = 0U; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
+ if ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
continue;
+ }
goto done;
}
panic();
done:
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
return DVFS_COMPLETE;
}
-IIC_DVFS_FUNC(write_reg_addr_read, DVFS_STATE_T *state, uint32_t *err,
- uint8_t reg_addr)
+IIC_DVFS_FUNC(write_reg_addr_read, enum dvfs_state_t *state, uint32_t *err,
+ uint8_t reg_addr)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
@@ -363,18 +383,20 @@
return result;
}
-IIC_DVFS_FUNC(retransmit, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(retransmit, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_RETRANSMISSION);
@@ -389,20 +411,22 @@
return result;
}
-IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
- uint8_t slave)
+IIC_DVFS_FUNC(set_slave_read, enum dvfs_state_t *state, uint32_t *err,
+ uint8_t slave)
{
uint8_t address;
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
- if (mode != IIC_DVFS_BIT_ICSR_DTE)
+ if (mode != IIC_DVFS_BIT_ICSR_DTE) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
@@ -410,23 +434,25 @@
address = ((uint8_t) (slave << 1) + DVFS_READ_MODE);
mmio_write_8(IIC_DVFS_REG_ICDR, address);
- *state = DVFS_CHANGE_SEND_TO_RECIEVE;
+ *state = DVFS_CHANGE_SEND_TO_RECEIVE;
return result;
}
-IIC_DVFS_FUNC(change_send_to_recieve, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(change_send_to_receive, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_CHANGE);
@@ -438,18 +464,20 @@
return result;
}
-IIC_DVFS_FUNC(stop_read, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(stop_read, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_READ_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP_READ);
@@ -464,13 +492,14 @@
return result;
}
-IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data)
+IIC_DVFS_FUNC(read, enum dvfs_state_t *state, uint8_t *reg_data)
{
uint8_t mode;
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
- if (mode != IIC_DVFS_BIT_ICSR_DTE)
+ if (mode != IIC_DVFS_BIT_ICSR_DTE) {
return DVFS_PROCESS;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
@@ -483,12 +512,12 @@
RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data)
{
- DVFS_STATE_T state = DVFS_START;
+ enum dvfs_state_t state = DVFS_START;
int32_t result = DVFS_PROCESS;
- uint32_t err = 0;
+ uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
again:
switch (state) {
case DVFS_START:
@@ -514,20 +543,21 @@
break;
}
- if (result == DVFS_PROCESS)
+ if (result == DVFS_PROCESS) {
goto again;
+ }
return result;
}
RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data)
{
- DVFS_STATE_T state = DVFS_START;
+ enum dvfs_state_t state = DVFS_START;
int32_t result = DVFS_PROCESS;
- uint32_t err = 0;
+ uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
again:
switch (state) {
case DVFS_START:
@@ -545,8 +575,8 @@
case DVFS_SET_SLAVE_READ:
result = dvfs_set_slave_read(&state, &err, slave);
break;
- case DVFS_CHANGE_SEND_TO_RECIEVE:
- result = dvfs_change_send_to_recieve(&state, &err);
+ case DVFS_CHANGE_SEND_TO_RECEIVE:
+ result = dvfs_change_send_to_receive(&state, &err);
break;
case DVFS_STOP_READ:
result = dvfs_stop_read(&state, &err);
@@ -562,8 +592,9 @@
break;
}
- if (result == DVFS_PROCESS)
+ if (result == DVFS_PROCESS) {
goto again;
+ }
return result;
}
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h
index 2dec58f..244c06c 100644
--- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h
+++ b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,14 +8,14 @@
#define IIC_DVFS_H
/* PMIC slave */
-#define PMIC (0x30)
-#define BKUP_MODE_CNT (0x20)
-#define DVFS_SET_VID (0x54)
-#define REG_KEEP10 (0x79)
+#define PMIC (0x30U)
+#define BKUP_MODE_CNT (0x20U)
+#define DVFS_SET_VID (0x54U)
+#define REG_KEEP10 (0x79U)
/* EEPROM slave */
-#define EEPROM (0x50)
-#define BOARD_ID (0x70)
+#define EEPROM (0x50U)
+#define BOARD_ID (0x70U)
int32_t rcar_iic_dvfs_receive(uint8_t slave, uint8_t reg, uint8_t *data);
int32_t rcar_iic_dvfs_send(uint8_t slave, uint8_t regr, uint8_t data);
diff --git a/drivers/renesas/rcar/io/io_emmcdrv.c b/drivers/renesas/rcar/io/io_emmcdrv.c
index 84240d2..c2b5f7c 100644
--- a/drivers/renesas/rcar/io/io_emmcdrv.c
+++ b/drivers/renesas/rcar/io/io_emmcdrv.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,13 +10,13 @@
#include <drivers/io/io_driver.h>
#include <drivers/io/io_storage.h>
-#include "io_common.h"
-#include "io_emmcdrv.h"
-#include "io_private.h"
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
#include "emmc_std.h"
-#include "emmc_def.h"
+#include "io_common.h"
+#include "io_emmcdrv.h"
+#include "io_private.h"
static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)),
io_dev_info_t **dev_info);
@@ -41,8 +41,9 @@
static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode,
signed long long offset)
{
- if (mode != IO_SEEK_SET)
+ if (mode != IO_SEEK_SET) {
return IO_FAIL;
+ }
((file_state_t *) entity->info)->file_pos = offset;
@@ -64,12 +65,14 @@
current_file.partition, current_file.file_pos,
sector_add, length, sector_num);
- if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX)
+ if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX) {
emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE;
+ }
if (emmc_read_sector((uint32_t *) buffer, sector_add, sector_num,
- emmc_dma) != EMMC_SUCCESS)
+ emmc_dma) != EMMC_SUCCESS) {
result = IO_FAIL;
+ }
*length_read = length;
fp->file_pos += (signed long long)length;
@@ -92,8 +95,8 @@
if (emmcdrv_bootpartition == PARTITION_ID_USER) {
emmcdrv_bootpartition = mmc_drv_obj.boot_partition_en;
- if ((PARTITION_ID_BOOT_1 == emmcdrv_bootpartition) ||
- (PARTITION_ID_BOOT_2 == emmcdrv_bootpartition)) {
+ if ((emmcdrv_bootpartition == PARTITION_ID_BOOT_1) ||
+ (emmcdrv_bootpartition == PARTITION_ID_BOOT_2)) {
current_file.partition = emmcdrv_bootpartition;
NOTICE("BL2: eMMC boot from partition %d\n",
@@ -103,16 +106,18 @@
return IO_FAIL;
}
- if ((PARTITION_ID_USER == block_spec->partition) ||
- (PARTITION_ID_BOOT_1 == block_spec->partition) ||
- (PARTITION_ID_BOOT_2 == block_spec->partition))
+ if ((block_spec->partition == PARTITION_ID_USER) ||
+ (block_spec->partition == PARTITION_ID_BOOT_1) ||
+ (block_spec->partition == PARTITION_ID_BOOT_2)) {
current_file.partition = block_spec->partition;
- else
+ } else {
current_file.partition = emmcdrv_bootpartition;
+ }
done:
- if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS)
+ if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS) {
return IO_FAIL;
+ }
entity->info = (uintptr_t) ¤t_file;
@@ -166,8 +171,9 @@
int32_t rc;
rc = io_register_device(&emmcdrv_dev_info);
- if (rc == IO_SUCCESS)
+ if (rc == IO_SUCCESS) {
*dev_con = &emmcdrv_dev_connector;
+ }
return rc;
}
diff --git a/drivers/renesas/rcar/io/io_memdrv.c b/drivers/renesas/rcar/io/io_memdrv.c
index 7e8c1d3..1f31c0f 100644
--- a/drivers/renesas/rcar/io/io_memdrv.c
+++ b/drivers/renesas/rcar/io/io_memdrv.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,8 +11,8 @@
#include <drivers/io/io_storage.h>
#include "io_common.h"
-#include "io_private.h"
#include "io_memdrv.h"
+#include "io_private.h"
#include "rcar_def.h"
extern void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len);
@@ -21,7 +21,8 @@
io_dev_info_t **dev_info);
static int32_t memdrv_dev_close(io_dev_info_t *dev_info);
-/* As we need to be able to keep state for seek, only one file can be open
+/*
+ * As we need to be able to keep state for seek, only one file can be open
* at a time. Make this a structure and point to the entity->info. When we
* can malloc memory we can change this to support more open files.
*/
@@ -43,12 +44,14 @@
{
const io_drv_spec_t *block_spec = (io_drv_spec_t *) spec;
- /* Since we need to track open state for seek() we only allow one open
+ /*
+ * Since we need to track open state for seek() we only allow one open
* spec at a time. When we have dynamic memory we can malloc and set
* entity->info.
*/
- if (current_file.in_use != 0U)
+ if (current_file.in_use != 0U) {
return IO_RESOURCES_EXHAUSTED;
+ }
/* File cursor offset for seek and incremental reads etc. */
current_file.base = block_spec->offset;
@@ -63,8 +66,9 @@
static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode,
signed long long offset)
{
- if (mode != IO_SEEK_SET)
+ if (mode != IO_SEEK_SET) {
return IO_FAIL;
+ }
((file_state_t *) entity->info)->file_pos = offset;
@@ -142,8 +146,9 @@
int32_t result;
result = io_register_device(&memdrv_dev_info);
- if (result == IO_SUCCESS)
+ if (result == IO_SUCCESS) {
*dev_con = &memdrv_dev_connector;
+ }
return result;
}
diff --git a/drivers/renesas/rcar/io/io_rcar.c b/drivers/renesas/rcar/io/io_rcar.c
index b82c510..c3e8319 100644
--- a/drivers/renesas/rcar/io/io_rcar.c
+++ b/drivers/renesas/rcar/io/io_rcar.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,8 +8,6 @@
#include <stdint.h>
#include <string.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -24,6 +22,7 @@
#include "io_rcar.h"
#include "io_common.h"
#include "io_private.h"
+#include <platform_def.h>
extern int32_t plat_get_drv_source(uint32_t id, uintptr_t *dev,
uintptr_t *image_spec);
@@ -39,7 +38,8 @@
} plat_rcar_name_offset_t;
typedef struct {
- /* Put position above the struct to allow {0} on static init.
+ /*
+ * Put position above the struct to allow {0} on static init.
* It is a workaround for a known bug in GCC
* http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
*/
@@ -59,7 +59,7 @@
#define RCAR_ATTR_SET_ISNOLOAD(a) (((a) & 0x1) << 16U)
#define RCAR_ATTR_SET_CERTOFF(a) (((a) & 0xF) << 8U)
#define RCAR_ATTR_SET_ALL(a, b, c) ((uint32_t)(RCAR_ATTR_SET_CALCADDR(a) |\
- RCAR_ATTR_SET_ISNOLOAD(b) | \
+ RCAR_ATTR_SET_ISNOLOAD(b) |\
RCAR_ATTR_SET_CERTOFF(c)))
#define RCAR_ATTR_GET_CALCADDR(a) ((a) & 0xFU)
@@ -136,9 +136,11 @@
{
#if TRUSTED_BOARD_BOOT
int32_t i;
+
for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
- if (name != cert_offset[i].name)
+ if (name != cert_offset[i].name) {
continue;
+ }
*cert = RCAR_CERT_SIZE;
*cert *= RCAR_ATTR_GET_CERTOFF(cert_offset[i].attr);
@@ -157,12 +159,14 @@
int32_t i;
for (i = 0; i < ARRAY_SIZE(name_offset); i++) {
- if (name != name_offset[i].name)
+ if (name != name_offset[i].name) {
continue;
+ }
addr = RCAR_ATTR_GET_CALCADDR(name_offset[i].attr);
- if (rcar_image_number + 2 < addr)
+ if (rcar_image_number + 2U < addr) {
continue;
+ }
*offset = rcar_image_header[addr];
*cert = RCAR_CERT_SIZE;
@@ -175,8 +179,9 @@
#if TRUSTED_BOARD_BOOT
for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
- if (name != cert_offset[i].name)
+ if (name != cert_offset[i].name) {
continue;
+ }
*no_load = RCAR_ATTR_GET_ISNOLOAD(cert_offset[i].attr);
*partition = 0U;
@@ -282,8 +287,9 @@
result = IO_FAIL;
}
done:
- if (result == IO_FAIL)
+ if (result == IO_FAIL) {
ERROR("BL2: Out of range : dst=0x%lx len=0x%lx\n", dst, len);
+ }
return result;
}
@@ -307,14 +313,15 @@
BL338_IMAGE_ID
};
- if (loaded != IO_NOT_SUPPORTED)
+ if (loaded != IO_NOT_SUPPORTED) {
return loaded;
+ }
for (i = 1; i < rcar_image_number; i++) {
rc = file_to_offset(img[i], &offset, &cert, &noload,
&partition);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: failed to get offset\n");
+ WARN("%s: failed to get offset\n", __func__);
loaded = IO_FAIL;
return loaded;
}
@@ -324,34 +331,34 @@
rc = io_open(rcar_handle, rcar_spec, &handle);
if (rc != IO_SUCCESS) {
- WARN("Failed to open FIP (%i)\n", rc);
+ WARN("%s: Failed to open FIP (%i)\n", __func__, rc);
loaded = IO_FAIL;
return loaded;
}
rc = io_seek(handle, IO_SEEK_SET, offset);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: failed to seek\n");
+ WARN("%s: failed to seek\n", __func__);
loaded = IO_FAIL;
return loaded;
}
rc = check_load_area(dst, len);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: check load area\n");
+ WARN("%s: check load area\n", __func__);
loaded = IO_FAIL;
return loaded;
}
rc = io_read(handle, dst, len, &cnt);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: failed to read\n");
+ WARN("%s: failed to read\n", __func__);
loaded = IO_FAIL;
return loaded;
}
#if TRUSTED_BOARD_BOOT
rc = auth_mod_verify_img(img[i], (void *)dst, len);
- if (rc) {
+ if (rc != 0) {
memset((void *)dst, 0x00, len);
loaded = IO_FAIL;
return loaded;
@@ -367,8 +374,7 @@
static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
{
- uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {
- 0};
+ uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {0UL};
uintptr_t handle;
ssize_t offset;
uint32_t i;
@@ -382,8 +388,9 @@
return IO_FAIL;
}
- if (RCAR_CERT_LOAD == rcar_cert_load)
+ if (rcar_cert_load == RCAR_CERT_LOAD) {
return IO_SUCCESS;
+ }
rc = io_open(rcar_handle, rcar_spec, &handle);
if (rc != IO_SUCCESS) {
@@ -391,16 +398,18 @@
return IO_FAIL;
}
- /* get start address list */
- /* [0] address num */
- /* [1] BL33-1 image address */
- /* [2] BL33-2 image address */
- /* [3] BL33-3 image address */
- /* [4] BL33-4 image address */
- /* [5] BL33-5 image address */
- /* [6] BL33-6 image address */
- /* [7] BL33-7 image address */
- /* [8] BL33-8 image address */
+ /*
+ * get start address list
+ * [0] address num
+ * [1] BL33-1 image address
+ * [2] BL33-2 image address
+ * [3] BL33-3 image address
+ * [4] BL33-4 image address
+ * [5] BL33-5 image address
+ * [6] BL33-6 image address
+ * [7] BL33-7 image address
+ * [8] BL33-8 image address
+ */
offset = name == EMMC_DEV_ID ? RCAR_EMMC_CERT_HEADER :
RCAR_FLASH_CERT_HEADER;
rc = io_seek(handle, IO_SEEK_SET, offset);
@@ -447,8 +456,9 @@
rcar_cert_load = RCAR_CERT_LOAD;
error:
- if (rc != IO_SUCCESS)
+ if (rc != IO_SUCCESS) {
rc = IO_FAIL;
+ }
io_close(handle);
@@ -464,13 +474,15 @@
uint32_t noload, cert, len;
int32_t rc;
- /* Only one file open at a time. We need to track state (ie, file
- * cursor position). Since the header lives at * offset zero, this entry
+ /*
+ * Only one file open at a time. We need to track state (ie, file
+ * cursor position). Since the header lives at offset zero, this entry
* should never be zero in an active file.
* Once the system supports dynamic memory allocation we will allow more
- * than one open file at a time. */
+ * than one open file at a time.
+ */
if (current_file.offset != 0U) {
- WARN("rcar_file_open : Only one open file at a time.\n");
+ WARN("%s: Only one open file at a time.\n", __func__);
return IO_RESOURCES_EXHAUSTED;
}
@@ -480,7 +492,7 @@
return IO_FAIL;
}
- if (noload) {
+ if (noload != 0U) {
current_file.offset = 1;
current_file.dst = 0;
current_file.size = 1;
@@ -494,12 +506,10 @@
rcar_read_certificate((uint64_t) cert, &len, &dst);
- /*----------------*
- * Baylibre: HACK *
- *----------------*/
- if (BL31_IMAGE_ID == spec->offset && len < RCAR_TRUSTED_SRAM_SIZE) {
- WARN("r-car ignoring the BL31 size from certificate,"
- "using RCAR_TRUSTED_SRAM_SIZE instead\n");
+ /* Baylibre: HACK */
+ if (spec->offset == BL31_IMAGE_ID && len < RCAR_TRUSTED_SRAM_SIZE) {
+ WARN("%s,%s\n", "r-car ignoring the BL31 size from certificate",
+ "using RCAR_TRUSTED_SRAM_SIZE instead");
len = RCAR_TRUSTED_SRAM_SIZE;
}
@@ -536,7 +546,7 @@
#else
static uint32_t load_bl33x_counter;
#endif
- if (current_file.no_load) {
+ if (current_file.no_load != 0U) {
*cnt = length;
return IO_SUCCESS;
}
@@ -551,14 +561,14 @@
rc = io_seek(handle, IO_SEEK_SET, offset);
if (rc != IO_SUCCESS) {
- WARN("rcar_file_read: failed to seek\n");
+ WARN("%s: failed to seek\n", __func__);
goto error;
}
if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33) {
rc = check_load_area(buffer, length);
if (rc != IO_SUCCESS) {
- WARN("rcar_file_read: load area err\n");
+ WARN("%s: load area err\n", __func__);
goto error;
}
}
@@ -573,8 +583,9 @@
io_close(handle);
load_bl33x_counter += 1;
- if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33X)
+ if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33X) {
return load_bl33x();
+ }
return IO_SUCCESS;
error:
@@ -584,8 +595,9 @@
static int32_t rcar_file_close(io_entity_t *entity)
{
- if (current_file.offset)
+ if (current_file.offset != 0U) {
memset(¤t_file, 0, sizeof(current_file));
+ }
entity->info = 0U;
@@ -634,8 +646,9 @@
int32_t result;
result = io_register_device(&rcar_dev_info);
- if (result == IO_SUCCESS)
+ if (result == IO_SUCCESS) {
*dev_con = &rcar_dev_connector;
+ }
return result;
}
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
index 2ce6b61..c0f015f 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,10 +16,10 @@
#include <plat/common/platform.h>
#include "iic_dvfs.h"
-#include "rcar_def.h"
-#include "rcar_private.h"
#include "micro_delay.h"
#include "pwrc.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
/*
* Someday there will be a generic power controller api. At the moment each
@@ -27,105 +27,105 @@
*/
RCAR_INSTANTIATE_LOCK
-#define WUP_IRQ_SHIFT (0U)
-#define WUP_FIQ_SHIFT (8U)
-#define WUP_CSD_SHIFT (16U)
-#define BIT_SOFTRESET (1U<<15)
-#define BIT_CA53_SCU (1U<<21)
-#define BIT_CA57_SCU (1U<<12)
-#define REQ_RESUME (1U<<1)
-#define REQ_OFF (1U<<0)
-#define STATUS_PWRUP (1U<<4)
-#define STATUS_PWRDOWN (1U<<0)
-#define STATE_CA57_CPU (27U)
-#define STATE_CA53_CPU (22U)
-#define MODE_L2_DOWN (0x00000002U)
-#define CPU_PWR_OFF (0x00000003U)
-#define RCAR_PSTR_MASK (0x00000003U)
-#define ST_ALL_STANDBY (0x00003333U)
+#define WUP_IRQ_SHIFT (0U)
+#define WUP_FIQ_SHIFT (8U)
+#define WUP_CSD_SHIFT (16U)
+#define BIT_SOFTRESET (1U << 15)
+#define BIT_CA53_SCU (1U << 21)
+#define BIT_CA57_SCU (1U << 12)
+#define REQ_RESUME (1U << 1)
+#define REQ_OFF (1U << 0)
+#define STATUS_PWRUP (1U << 4)
+#define STATUS_PWRDOWN (1U << 0)
+#define STATE_CA57_CPU (27U)
+#define STATE_CA53_CPU (22U)
+#define MODE_L2_DOWN (0x00000002U)
+#define CPU_PWR_OFF (0x00000003U)
+#define RCAR_PSTR_MASK (0x00000003U)
+#define ST_ALL_STANDBY (0x00003333U)
/* Suspend to ram */
-#define DBSC4_REG_BASE (0xE6790000U)
-#define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
-#define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
-#define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
-#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
-#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
-#define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
-#define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
-#define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
-#define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
-#define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
-#define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
-#define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
-#define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
-#define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
-#define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
-#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
-#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
-#define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
-#define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
-#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
-#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
-#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
-#define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
-#define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
-#define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
-#define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
-#define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
-#define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
-#define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
-#define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
-#define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
-#define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
-#define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
-#define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
-#define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
-#define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
-#define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
-#define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
-#define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
-#define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
-#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
-#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
-#define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-#define RST_MODEMR_BIT0 (0x00000001U)
+#define DBSC4_REG_BASE (0xE6790000U)
+#define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
+#define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
+#define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
+#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
+#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
+#define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
+#define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
+#define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
+#define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
+#define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
+#define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
+#define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
+#define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
+#define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
+#define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
+#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
+#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
+#define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
+#define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
+#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
+#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
+#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
+#define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
+#define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
+#define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
+#define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
+#define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
+#define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
+#define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
+#define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
+#define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
+#define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
+#define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
+#define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
+#define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
+#define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
+#define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
+#define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
+#define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
+#define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
+#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
+#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
+#define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
+#define RST_BASE (0xE6160000U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
+#define RST_MODEMR_BIT0 (0x00000001U)
#define RCAR_CNTCR_OFF (0x00U)
#define RCAR_CNTCVL_OFF (0x08U)
@@ -136,17 +136,17 @@
#define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U)
#if PMIC_ROHM_BD9571
-#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
-#define PMIC_BKUP_MODE_CNT (0x20U)
-#define PMIC_QLLM_CNT (0x27U)
-#define PMIC_RETRY_MAX (100U)
-#endif
-#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
-#define RCAR_CA53CPU_NUM_MAX (4U)
-#define RCAR_CA57CPU_NUM_MAX (4U)
-#define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
-#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
-#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
+#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
+#define PMIC_BKUP_MODE_CNT (0x20U)
+#define PMIC_QLLM_CNT (0x27U)
+#define PMIC_RETRY_MAX (100U)
+#endif /* PMIC_ROHM_BD9571 */
+#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
+#define RCAR_CA53CPU_NUM_MAX (4U)
+#define RCAR_CA57CPU_NUM_MAX (4U)
+#define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
+#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
+#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
#ifndef __ASSEMBLER__
IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
@@ -320,11 +320,13 @@
c = rcar_pwrc_get_mpidr_cluster(mpidr);
dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
- if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
+ if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
goto done;
+ }
- if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
+ if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) {
goto done;
+ }
/* all of the CPUs in the cluster is in the CoreStandby mode */
mmio_write_32(dst, MODE_L2_DOWN);
@@ -343,7 +345,7 @@
rcar_pwrc_saved_cntfid =
mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
}
-#endif
+#endif /* RCAR_SYSTEM_SUSPEND */
void rcar_pwrc_restore_timer_state(void)
{
@@ -372,10 +374,10 @@
}
#endif /* PMIC_ROHM_BD9571 */
-#define RST_CA53_CPU0_BARH (0xE6160080U)
-#define RST_CA53_CPU0_BARL (0xE6160084U)
-#define RST_CA57_CPU0_BARH (0xE61600C0U)
-#define RST_CA57_CPU0_BARL (0xE61600C4U)
+#define RST_CA53_CPU0_BARH (0xE6160080U)
+#define RST_CA53_CPU0_BARL (0xE6160084U)
+#define RST_CA57_CPU0_BARH (0xE61600C0U)
+#define RST_CA57_CPU0_BARL (0xE61600C4U)
void rcar_pwrc_setup(void)
{
@@ -427,11 +429,13 @@
product = reg & PRR_PRODUCT_MASK;
cut = reg & PRR_CUT_MASK;
- if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
+ if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
goto self_refresh;
+ }
- if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
+ if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) {
goto self_refresh;
+ }
mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
@@ -509,7 +513,7 @@
}
static void __attribute__ ((section(".system_ram")))
- rcar_pwrc_set_self_refresh_e3(void)
+rcar_pwrc_set_self_refresh_e3(void)
{
uint32_t ddr_md;
uint32_t reg;
@@ -533,8 +537,10 @@
while (mmio_read_32(DBSC4_REG_DBWAIT))
;
- /* Set the auto-refresh enable register */
- /* Set the ARFEN bit to 0 in the DBRFEN */
+ /*
+ * Set the auto-refresh enable register
+ * Set the ARFEN bit to 0 in the DBRFEN
+ */
mmio_write_32(DBSC4_REG_DBRFEN, 0);
mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
@@ -638,7 +644,7 @@
}
void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
- rcar_pwrc_go_suspend_to_ram(void)
+rcar_pwrc_go_suspend_to_ram(void)
{
#if PMIC_ROHM_BD9571
int32_t rc = -1, qllm = -1;
@@ -713,7 +719,7 @@
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
if (error) {
- ERROR("Failed send KEEP10 init ret=%d \n", error);
+ ERROR("Failed send KEEP10 init ret=%d\n", error);
return;
}
#endif
@@ -835,7 +841,6 @@
uint64_t my_cpu;
int32_t rtn;
uint32_t my_cluster_type;
-
const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
RCAR_CLUSTER_CA53,
RCAR_CLUSTER_CA57
@@ -861,6 +866,6 @@
}
}
}
- return (rtn);
+ return rtn;
}
diff --git a/drivers/renesas/rcar/pwrc/pwrc.h b/drivers/renesas/rcar/pwrc/pwrc.h
index 2b81783..f73099b 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.h
+++ b/drivers/renesas/rcar/pwrc/pwrc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,12 +31,12 @@
#define WKUP_PPONR 0x2
#define WKUP_GICREQ 0x3
-#define RCAR_INVALID (0xffffffffU)
+#define RCAR_INVALID (0xffffffffU)
#define PSYSR_INVALID 0xffffffff
-#define RCAR_CLUSTER_A53A57 (0U)
-#define RCAR_CLUSTER_CA53 (1U)
-#define RCAR_CLUSTER_CA57 (2U)
+#define RCAR_CLUSTER_A53A57 (0U)
+#define RCAR_CLUSTER_CA53 (1U)
+#define RCAR_CLUSTER_CA57 (2U)
#ifndef __ASSEMBLER__
void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr);
diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/rcar/scif/scif.S
index ae26cc4..beb8dd8 100644
--- a/drivers/renesas/rcar/scif/scif.S
+++ b/drivers/renesas/rcar/scif/scif.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,43 +9,43 @@
#include <console_macros.S>
#include <drivers/renesas/rcar/console/console.h>
-#define SCIF_INTERNAL_CLK 0
-#define SCIF_EXTARNAL_CLK 1
-#define SCIF_CLK SCIF_INTERNAL_CLK
+#define SCIF_INTERNAL_CLK 0
+#define SCIF_EXTARNAL_CLK 1
+#define SCIF_CLK SCIF_INTERNAL_CLK
/* product register */
-#define PRR (0xFFF00044)
-#define PRR_PRODUCT_MASK (0x00007F00)
-#define PRR_CUT_MASK (0x000000FF)
-#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
-#define PRR_PRODUCT_E3 (0x00005700)
-#define PRR_PRODUCT_D3 (0x00005800)
+#define PRR (0xFFF00044)
+#define PRR_PRODUCT_MASK (0x00007F00)
+#define PRR_CUT_MASK (0x000000FF)
+#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
+#define PRR_PRODUCT_E3 (0x00005700)
+#define PRR_PRODUCT_D3 (0x00005800)
/* module stop */
-#define CPG_BASE (0xE6150000)
-#define CPG_SMSTPCR2 (0x0138)
-#define CPG_SMSTPCR3 (0x013C)
+#define CPG_BASE (0xE6150000)
+#define CPG_SMSTPCR2 (0x0138)
+#define CPG_SMSTPCR3 (0x013C)
#define CPG_MSTPSR2 (0x0040)
-#define CPG_MSTPSR3 (0x0048)
-#define MSTP207 (1 << 7)
-#define MSTP310 (1 << 10)
-#define CPG_CPGWPR (0x0900)
+#define CPG_MSTPSR3 (0x0048)
+#define MSTP207 (1 << 7)
+#define MSTP310 (1 << 10)
+#define CPG_CPGWPR (0x0900)
/* scif */
-#define SCIF0_BASE (0xE6E60000)
-#define SCIF2_BASE (0xE6E88000)
-#define SCIF_SCSMR (0x00)
-#define SCIF_SCBRR (0x04)
-#define SCIF_SCSCR (0x08)
-#define SCIF_SCFTDR (0x0C)
-#define SCIF_SCFSR (0x10)
-#define SCIF_SCFRDR (0x14)
-#define SCIF_SCFCR (0x18)
-#define SCIF_SCFDR (0x1C)
-#define SCIF_SCSPTR (0x20)
-#define SCIF_SCLSR (0x24)
-#define SCIF_DL (0x30)
-#define SCIF_CKS (0x34)
+#define SCIF0_BASE (0xE6E60000)
+#define SCIF2_BASE (0xE6E88000)
+#define SCIF_SCSMR (0x00)
+#define SCIF_SCBRR (0x04)
+#define SCIF_SCSCR (0x08)
+#define SCIF_SCFTDR (0x0C)
+#define SCIF_SCFSR (0x10)
+#define SCIF_SCFRDR (0x14)
+#define SCIF_SCFCR (0x18)
+#define SCIF_SCFDR (0x1C)
+#define SCIF_SCSPTR (0x20)
+#define SCIF_SCLSR (0x24)
+#define SCIF_DL (0x30)
+#define SCIF_CKS (0x34)
#if RCAR_LSI == RCAR_V3M
#define SCIF_BASE SCIF0_BASE
@@ -60,70 +60,71 @@
#endif
/* mode pin */
-#define RST_MODEMR (0xE6160060)
-#define MODEMR_MD12 (0x00001000)
+#define RST_MODEMR (0xE6160060)
+#define MODEMR_MD12 (0x00001000)
-#define SCSMR_CA_MASK (1 << 7)
-#define SCSMR_CA_ASYNC (0x0000)
-#define SCSMR_CHR_MASK (1 << 6)
-#define SCSMR_CHR_8 (0x0000)
-#define SCSMR_PE_MASK (1 << 5)
-#define SCSMR_PE_DIS (0x0000)
-#define SCSMR_STOP_MASK (1 << 3)
-#define SCSMR_STOP_1 (0x0000)
-#define SCSMR_CKS_MASK (3 << 0)
-#define SCSMR_CKS_DIV1 (0x0000)
-#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
+#define SCSMR_CA_MASK (1 << 7)
+#define SCSMR_CA_ASYNC (0x0000)
+#define SCSMR_CHR_MASK (1 << 6)
+#define SCSMR_CHR_8 (0x0000)
+#define SCSMR_PE_MASK (1 << 5)
+#define SCSMR_PE_DIS (0x0000)
+#define SCSMR_STOP_MASK (1 << 3)
+#define SCSMR_STOP_1 (0x0000)
+#define SCSMR_CKS_MASK (3 << 0)
+#define SCSMR_CKS_DIV1 (0x0000)
+#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
SCSMR_CHR_8 + \
SCSMR_PE_DIS + \
SCSMR_STOP_1 + \
SCSMR_CKS_DIV1)
-#define SCBRR_115200BPS (17)
-#define SCBRR_115200BPSON (16)
-#define SCBRR_115200BPS_E3_SSCG (15)
-#define SCBRR_230400BPS (8)
+#define SCBRR_115200BPS (17)
+#define SCBRR_115200BPSON (16)
+#define SCBRR_115200BPS_E3_SSCG (15)
+#define SCBRR_230400BPS (8)
-#define SCSCR_TE_MASK (1 << 5)
-#define SCSCR_TE_DIS (0x0000)
-#define SCSCR_TE_EN (0x0020)
-#define SCSCR_RE_MASK (1 << 4)
-#define SCSCR_RE_DIS (0x0000)
-#define SCSCR_RE_EN (0x0010)
-#define SCSCR_CKE_MASK (3 << 0)
-#define SCSCR_CKE_INT (0x0000)
-#define SCSCR_CKE_BRG (0x0002)
+#define SCSCR_TE_MASK (1 << 5)
+#define SCSCR_TE_DIS (0x0000)
+#define SCSCR_TE_EN (0x0020)
+#define SCSCR_RE_MASK (1 << 4)
+#define SCSCR_RE_DIS (0x0000)
+#define SCSCR_RE_EN (0x0010)
+#define SCSCR_CKE_MASK (3 << 0)
+#define SCSCR_CKE_INT (0x0000)
+#define SCSCR_CKE_BRG (0x0002)
#if SCIF_CLK == SCIF_EXTARNAL_CLK
-#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
+#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
#else
-#define SCFSR_TEND_MASK (1 << 6)
-#define SCFSR_TEND_TRANS_END (0x0040)
-#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
+#define SCFSR_TEND_MASK (1 << 6)
+#define SCFSR_TEND_TRANS_END (0x0040)
+#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
#endif
-#define SCFSR_INIT_DATA (0x0000)
-#define SCFCR_TTRG_MASK (3 << 4)
-#define SCFCR_TTRG_8 (0x0000)
-#define SCFCR_TTRG_0 (0x0030)
-#define SCFCR_TFRST_MASK (1 << 2)
-#define SCFCR_TFRST_DIS (0x0000)
-#define SCFCR_TFRST_EN (0x0004)
-#define SCFCR_RFRS_MASK (1 << 1)
-#define SCFCR_RFRS_DIS (0x0000)
-#define SCFCR_RFRS_EN (0x0002)
-#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
-#define SCFDR_T_MASK (0x1f << 8)
-#define DL_INIT_DATA (8)
-#define CKS_CKS_DIV_MASK (1 << 15)
-#define CKS_CKS_DIV_CLK (0x0000)
-#define CKS_XIN_MASK (1 << 14)
-#define CKS_XIN_SCIF_CLK (0x0000)
-#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
+#define SCFSR_INIT_DATA (0x0000)
+#define SCFCR_TTRG_MASK (3 << 4)
+#define SCFCR_TTRG_8 (0x0000)
+#define SCFCR_TTRG_0 (0x0030)
+#define SCFCR_TFRST_MASK (1 << 2)
+#define SCFCR_TFRST_DIS (0x0000)
+#define SCFCR_TFRST_EN (0x0004)
+#define SCFCR_RFRS_MASK (1 << 1)
+#define SCFCR_RFRS_DIS (0x0000)
+#define SCFCR_RFRS_EN (0x0002)
+#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
+#define SCFDR_T_MASK (0x1f << 8)
+#define DL_INIT_DATA (8)
+#define CKS_CKS_DIV_MASK (1 << 15)
+#define CKS_CKS_DIV_CLK (0x0000)
+#define CKS_XIN_MASK (1 << 14)
+#define CKS_XIN_SCIF_CLK (0x0000)
+#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
.globl console_rcar_register
.globl console_rcar_init
.globl console_rcar_putc
.globl console_rcar_flush
- /* -----------------------------------------------
+ /*
+ * -----------------------------------------------
* int console_rcar_register(
* uintptr_t base, uint32_t clk, uint32_t baud,
* console_t *console)
@@ -154,7 +155,7 @@
ret x7
endfunc console_rcar_register
- /* -----------------------------------------------
+ /*
* int console_rcar_init(unsigned long base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
@@ -166,7 +167,6 @@
* w2 - Baud rate
* Out: return 1 on success
* Clobber list : x1, x2
- * -----------------------------------------------
*/
func console_rcar_init
ldr x0, =CPG_BASE
@@ -188,8 +188,10 @@
ldrh w1, [x0, #SCIF_SCFCR]
orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN)
strh w1, [x0, #SCIF_SCFCR]
- /* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
- in SCLSR, then clear them to 0 */
+ /*
+ * Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
+ * in SCLSR, then clear them to 0
+ */
mov w1, #SCFSR_INIT_DATA
strh w1, [x0, #SCIF_SCFSR]
mov w1, #0
@@ -265,7 +267,7 @@
ret
endfunc console_rcar_init
- /* --------------------------------------------------------
+ /*
* int console_rcar_putc(int c, unsigned int base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
@@ -273,7 +275,6 @@
* x1 - pointer to console_t structure
* Out : return -1 on error else return character.
* Clobber list : x2
- * --------------------------------------------------------
*/
func console_rcar_putc
ldr x1, =SCIF_BASE
@@ -304,12 +305,11 @@
ret
endfunc console_rcar_putc
- /* ---------------------------------------------
+ /*
* void console_rcar_flush(void)
* Function to force a write of all buffered
* data that hasn't been output. It returns void
* Clobber list : x0, x1
- * ---------------------------------------------
*/
func console_rcar_flush
ldr x0, =SCIF_BASE
diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/rcar/watchdog/swdt.c
index 111e651..05987ab 100644
--- a/drivers/renesas/rcar/watchdog/swdt.c
+++ b/drivers/renesas/rcar/watchdog/swdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -162,6 +162,6 @@
gicv2_end_of_interrupt(ARM_IRQ_SEC_WDT);
rcar_swdt_release();
ERROR("\n");
- ERROR("System WDT overflow, occured address is %p\n", (void *)p);
+ ERROR("System WDT overflow, occurred address is %p\n", (void *)p);
panic();
}
diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h
index 46ba466..30ca910 100644
--- a/include/drivers/cadence/cdns_uart.h
+++ b/include/drivers/cadence/cdns_uart.h
@@ -21,6 +21,7 @@
#define R_UART_SR 0x2C
#define UART_SR_INTR_REMPTY_BIT 1
#define UART_SR_INTR_TFUL_BIT 4
+#define UART_SR_INTR_TEMPTY_BIT 3
#define R_UART_TX 0x30
#define R_UART_RX 0x30
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 27991d3..5e870ff 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -34,8 +34,9 @@
{
assert(sec_state_is_valid(type));
- if (type == NON_SECURE)
+ if (type == NON_SECURE) {
return &bl33_image_ep_info;
+ }
return &bl32_image_ep_info;
}
@@ -68,8 +69,9 @@
VERSAL_UART_CLOCK,
VERSAL_UART_BAUDRATE,
&versal_runtime_console);
- if (rc == 0)
+ if (rc == 0) {
panic();
+ }
console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME);
diff --git a/plat/xilinx/versal/plat_versal.c b/plat/xilinx/versal/plat_versal.c
index a080a76..107eae6 100644
--- a/plat/xilinx/versal/plat_versal.c
+++ b/plat/xilinx/versal/plat_versal.c
@@ -9,11 +9,13 @@
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
- if (mpidr & MPIDR_CLUSTER_MASK)
+ if (mpidr & MPIDR_CLUSTER_MASK) {
return -1;
+ }
- if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT)
+ if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT) {
return -1;
+ }
return versal_calc_core_pos(mpidr);
}
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 8272d62..d4cd7f6 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -32,8 +32,9 @@
{
assert(sec_state_is_valid(type));
- if (type == NON_SECURE)
+ if (type == NON_SECURE) {
return &bl33_image_ep_info;
+ }
return &bl32_image_ep_info;
}
@@ -99,10 +100,11 @@
enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
&bl33_image_ep_info,
atf_handoff_addr);
- if (ret == FSBL_HANDOFF_NO_STRUCT)
+ if (ret == FSBL_HANDOFF_NO_STRUCT) {
bl31_set_default_config();
- else if (ret != FSBL_HANDOFF_SUCCESS)
+ } else if (ret != FSBL_HANDOFF_SUCCESS) {
panic();
+ }
}
if (bl32_image_ep_info.pc) {
VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
@@ -137,12 +139,14 @@
int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
{
/* Validate 'handler' and 'id' parameters */
- if (!handler || id >= MAX_INTR_EL3)
+ if (!handler || id >= MAX_INTR_EL3) {
return -EINVAL;
+ }
/* Check if a handler has already been registered */
- if (type_el3_interrupt_table[id])
+ if (type_el3_interrupt_table[id]) {
return -EALREADY;
+ }
type_el3_interrupt_table[id] = handler;
@@ -157,8 +161,9 @@
intr_id = plat_ic_get_pending_interrupt_id();
handler = type_el3_interrupt_table[intr_id];
- if (handler != NULL)
+ if (handler != NULL) {
handler(intr_id, flags, handle, cookie);
+ }
return 0;
}
@@ -181,8 +186,9 @@
set_interrupt_rm_flag(flags, NON_SECURE);
rc = register_interrupt_type_handler(INTR_TYPE_EL3,
rdo_el3_interrupt_handler, flags);
- if (rc)
+ if (rc) {
panic();
+ }
#endif
}
diff --git a/plat/xilinx/zynqmp/plat_zynqmp.c b/plat/xilinx/zynqmp/plat_zynqmp.c
index 906ce1b..58a52a3 100644
--- a/plat/xilinx/zynqmp/plat_zynqmp.c
+++ b/plat/xilinx/zynqmp/plat_zynqmp.c
@@ -9,11 +9,13 @@
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
- if (mpidr & MPIDR_CLUSTER_MASK)
+ if (mpidr & MPIDR_CLUSTER_MASK) {
return -1;
+ }
- if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT)
+ if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT) {
return -1;
+ }
return zynqmp_calc_core_pos(mpidr);
}