diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index fc3effd..f135ca2 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -73,9 +73,9 @@
 +----------------+----------------+--------------------+--------------------+
 |    mt6795      |      MTK       |        2.5         |       2.7          |
 +----------------+----------------+--------------------+--------------------+
-|    sgi575      |      Arm       |        2.8         |       2.10         |
+|    sgi575      |      Arm       |        2.8         |       TBD          |
 +----------------+----------------+--------------------+--------------------+
-|    rdn1edge    |      Arm       |        2.8         |       2.10         |
+|    rdn1edge    |      Arm       |        2.8         |       TBD          |
 +----------------+----------------+--------------------+--------------------+
 |    tc0         |      Arm       |        2.8         |       2.10         |
 +----------------+----------------+--------------------+--------------------+
diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
index 0235f8b..ed3801c 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,36 +33,16 @@
 static void set_fip_image_source(void)
 {
 	const struct plat_io_policy *policy;
-	/*
-	 * metadata for firmware update is written at 0x0000 offset of the flash.
-	 * PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted.
-	 * As per firmware update spec, at a given point of time, only one bank
-	 * is active. This means, TF-A should boot from the same bank as TF-M.
-	 */
-	volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG);
-
-	if (*boot_bank_flag > 1) {
-		VERBOSE("Boot_bank is set higher than possible values");
-	}
-
-	VERBOSE("Boot bank flag = %u.\n\r", *boot_bank_flag);
-
 	policy = FCONF_GET_PROPERTY(arm, io_policies, FIP_IMAGE_ID);
 
 	assert(policy != NULL);
 	assert(policy->image_spec != 0UL);
 
+	/* FIP Partition contains Signature area at the beginning which TF-A doesn't expect */
 	io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec;
+	spec->offset += FIP_SIGNATURE_AREA_SIZE;
+	spec->length -= FIP_SIGNATURE_AREA_SIZE;
 
-	if ((*boot_bank_flag) == 0) {
-		VERBOSE("Booting from bank 0: fip offset = 0x%lx\n\r",
-						PLAT_ARM_FIP_BASE_BANK0);
-		spec->offset = PLAT_ARM_FIP_BASE_BANK0;
-	} else {
-		VERBOSE("Booting from bank 1: fip offset = 0x%lx\n\r",
-						PLAT_ARM_FIP_BASE_BANK1);
-		spec->offset = PLAT_ARM_FIP_BASE_BANK1;
-	}
 }
 
 void bl2_platform_setup(void)
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
index 584d485..442d187 100644
--- a/plat/arm/board/corstone1000/common/include/platform_def.h
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -173,16 +173,15 @@
 
 /* NOR Flash */
 
-#define PLAT_ARM_BOOT_BANK_FLAG		UL(0x08002000)
-#define PLAT_ARM_FIP_BASE_BANK0		UL(0x081EF000)
-#define PLAT_ARM_FIP_BASE_BANK1		UL(0x0916F000)
-#define PLAT_ARM_FIP_MAX_SIZE		UL(0x1ff000)  /* 1.996 MB */
-
 #define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
 #define PLAT_ARM_NVM_SIZE		(SZ_32M)  /* 32 MB */
-
-#define PLAT_ARM_FLASH_IMAGE_BASE	PLAT_ARM_FIP_BASE_BANK0
+#define PLAT_ARM_FIP_MAX_SIZE		UL(0x1ff000)  /* 1.996 MB */
+#define PLAT_ARM_FLASH_IMAGE_BASE	UL(0x08000000)
 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	PLAT_ARM_FIP_MAX_SIZE
+#define PLAT_ARM_FIP_OFFSET_IN_GPT	(0x86000)
+
+/* FIP Information */
+#define FIP_SIGNATURE_AREA_SIZE         (0x1000)      /* 4 KB */
 
 /*
  * Some data must be aligned on the biggest cache line size in the platform.
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c
index b598c59..01e0db0 100644
--- a/plat/arm/common/arm_bl2_el3_setup.c
+++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -7,6 +7,7 @@
 #include <assert.h>
 
 #include <drivers/generic_delay_timer.h>
+#include <drivers/partition/partition.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
@@ -94,7 +95,15 @@
 
 void bl2_el3_plat_arch_setup(void)
 {
+	int __maybe_unused ret;
 	arm_bl2_el3_plat_arch_setup();
+#if ARM_GPT_SUPPORT
+	ret = gpt_partition_init();
+	if (ret != 0) {
+		ERROR("GPT partition initialisation failed!\n");
+		panic();
+	}
+#endif /* ARM_GPT_SUPPORT */
 }
 
 void bl2_el3_plat_prepare_exit(void)
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index d6d090a..b21faa3 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -302,14 +302,14 @@
 	 */
 	if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) ||
 	    (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) {
-		ret = PSCI_E_NOT_PRESENT;
+		ret = -1;
 	} else {
 		/* calculate the core position */
 		pos = cpu_id + (cluster_id << 2U);
 
 		/* check for non-existent CPUs */
 		if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) {
-			ret = PSCI_E_NOT_PRESENT;
+			ret = -1;
 		} else {
 			ret = (int32_t)pos;
 		}
diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h
index edfa73f..ade6d7a 100644
--- a/plat/ti/k3/board/generic/include/board_def.h
+++ b/plat/ti/k3/board/generic/include/board_def.h
@@ -12,8 +12,8 @@
 /* The ports must be in order and contiguous */
 #define K3_CLUSTER0_CORE_COUNT		U(2)
 #define K3_CLUSTER1_CORE_COUNT		U(2)
-#define K3_CLUSTER2_CORE_COUNT		U(2)
-#define K3_CLUSTER3_CORE_COUNT		U(2)
+#define K3_CLUSTER2_CORE_COUNT		U(0)
+#define K3_CLUSTER3_CORE_COUNT		U(0)
 
 #define PLAT_PROC_START_ID		U(32)
 #define PLAT_PROC_DEVICE_START_ID	U(202)
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
index 495f0c7..3f22bfd 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
@@ -211,6 +211,42 @@
 }
 
 /**
+ * ti_sci_query_fw_caps() - Get the FW/SoC capabilities
+ * @handle:		Pointer to TI SCI handle
+ * @fw_caps:		Each bit in fw_caps indicating one FW/SOC capability
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+int ti_sci_query_fw_caps(uint64_t *fw_caps)
+{
+	struct ti_sci_msg_hdr req;
+	struct ti_sci_msg_resp_query_fw_caps resp;
+
+	struct ti_sci_xfer xfer;
+	int ret;
+
+	ret = ti_sci_setup_one_xfer(TI_SCI_MSG_QUERY_FW_CAPS, 0,
+				    &req, sizeof(req),
+				    &resp, sizeof(resp),
+				    &xfer);
+	if (ret != 0U) {
+		ERROR("Message alloc failed (%d)\n", ret);
+		return ret;
+	}
+
+	ret = ti_sci_do_xfer(&xfer);
+	if (ret != 0U) {
+		ERROR("Transfer send failed (%d)\n", ret);
+		return ret;
+	}
+
+	if (fw_caps)
+		*fw_caps = resp.fw_caps;
+
+	return 0;
+}
+
+/**
  * ti_sci_device_set_state() - Set device state
  *
  * @id:		Device identifier
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci.h
index 06944a7..c702a71 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.h
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.h
@@ -141,10 +141,13 @@
  * Core control operations
  *
  * - ti_sci_core_reboot() - Command to request system reset
+ * - ti_sci_query_fw_caps() - Get the FW/SoC capabilities
+ *              @fw_caps: Each bit in fw_caps indicating one FW/SOC capability
  *
  * Return: 0 if all went well, else returns appropriate error value.
  */
 int ti_sci_core_reboot(void);
+int ti_sci_query_fw_caps(uint64_t *fw_caps);
 
 /**
  * Processor control operations
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
index 36909f5..7f1c368 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
@@ -22,6 +22,7 @@
 #define TI_SCI_MSG_WAKE_REASON		0x0003
 #define TI_SCI_MSG_GOODBYE		0x0004
 #define TI_SCI_MSG_SYS_RESET		0x0005
+#define TI_SCI_MSG_QUERY_FW_CAPS	0x0022
 
 /* Device requests */
 #define TI_SCI_MSG_SET_DEVICE_STATE	0x0200
@@ -124,6 +125,30 @@
 } __packed;
 
 /**
+ * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps
+ * @hdr:	Generic header
+ * @fw_caps:	Each bit in fw_caps indicating one FW/SOC capability
+ *		MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported)
+ *		MSG_FLAG_CAPS_LPM_DEEP_SLEEP: Deep Sleep LPM
+ *		MSG_FLAG_CAPS_LPM_MCU_ONLY: MCU only LPM
+ *		MSG_FLAG_CAPS_LPM_STANDBY: Standby LPM
+ *		MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM
+ *
+ * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
+ * providing currently available SOC/firmware capabilities. SoC that don't
+ * support low power modes return only MSG_FLAG_CAPS_GENERIC capability.
+ */
+struct ti_sci_msg_resp_query_fw_caps {
+	struct ti_sci_msg_hdr hdr;
+#define MSG_FLAG_CAPS_GENERIC		TI_SCI_MSG_FLAG(0)
+#define MSG_FLAG_CAPS_LPM_DEEP_SLEEP	TI_SCI_MSG_FLAG(1)
+#define MSG_FLAG_CAPS_LPM_MCU_ONLY	TI_SCI_MSG_FLAG(2)
+#define MSG_FLAG_CAPS_LPM_STANDBY	TI_SCI_MSG_FLAG(3)
+#define MSG_FLAG_CAPS_LPM_PARTIAL_IO	TI_SCI_MSG_FLAG(4)
+	uint64_t fw_caps;
+} __packed;
+
+/**
  * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
  * @hdr:		Generic header
  * @id:	Indicates which device to modify
diff --git a/plat/ti/k3/common/k3_gicv3.c b/plat/ti/k3/common/k3_gicv3.c
index 0199822..eda9430 100644
--- a/plat/ti/k3/common/k3_gicv3.c
+++ b/plat/ti/k3/common/k3_gicv3.c
@@ -19,10 +19,8 @@
 /* The GICv3 driver only needs to be initialized in EL3 */
 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
 
-#if K3_PM_SYSTEM_SUSPEND
 static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT];
 static gicv3_dist_ctx_t dist_ctx;
-#endif
 
 static const interrupt_prop_t k3_interrupt_props[] = {
 	PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
@@ -94,7 +92,6 @@
 	gicv3_rdistif_init(plat_my_core_pos());
 }
 
-#if K3_PM_SYSTEM_SUSPEND
 void k3_gic_save_context(void)
 {
 	for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) {
@@ -110,4 +107,3 @@
 		gicv3_rdistif_init_restore(i, &rdist_ctx[i]);
 	}
 }
-#endif
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index d846495..e8d73db 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -234,7 +234,6 @@
 	return PSCI_E_SUCCESS;
 }
 
-#if K3_PM_SYSTEM_SUSPEND
 static void k3_pwr_domain_suspend(const psci_power_state_t *target_state)
 {
 	unsigned int core, proc_id;
@@ -266,18 +265,15 @@
 		req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
 	}
 }
-#endif
 
-static const plat_psci_ops_t k3_plat_psci_ops = {
+static plat_psci_ops_t k3_plat_psci_ops = {
 	.cpu_standby = k3_cpu_standby,
 	.pwr_domain_on = k3_pwr_domain_on,
 	.pwr_domain_off = k3_pwr_domain_off,
 	.pwr_domain_on_finish = k3_pwr_domain_on_finish,
-#if K3_PM_SYSTEM_SUSPEND
 	.pwr_domain_suspend = k3_pwr_domain_suspend,
 	.pwr_domain_suspend_finish = k3_pwr_domain_suspend_finish,
 	.get_sys_suspend_power_state = k3_get_sys_suspend_power_state,
-#endif
 	.system_off = k3_system_off,
 	.system_reset = k3_system_reset,
 	.validate_power_state = k3_validate_power_state,
@@ -286,8 +282,27 @@
 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
 			const plat_psci_ops_t **psci_ops)
 {
+	uint64_t fw_caps = 0;
+	int ret;
+
 	k3_sec_entrypoint = sec_entrypoint;
 
+	ret = ti_sci_query_fw_caps(&fw_caps);
+	if (ret) {
+		ERROR("Unable to query firmware capabilities (%d)\n", ret);
+	}
+
+	/* If firmware does not support any known suspend mode */
+	if (!(fw_caps & (MSG_FLAG_CAPS_LPM_DEEP_SLEEP |
+			 MSG_FLAG_CAPS_LPM_MCU_ONLY |
+			 MSG_FLAG_CAPS_LPM_STANDBY |
+			 MSG_FLAG_CAPS_LPM_PARTIAL_IO))) {
+		/* Disable PSCI suspend support */
+		k3_plat_psci_ops.pwr_domain_suspend = NULL;
+		k3_plat_psci_ops.pwr_domain_suspend_finish = NULL;
+		k3_plat_psci_ops.get_sys_suspend_power_state = NULL;
+	}
+
 	*psci_ops = &k3_plat_psci_ops;
 
 	return 0;
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index fb633a8..23efa31 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -44,10 +44,6 @@
 K3_USART_BAUD		:=	115200
 $(eval $(call add_define,K3_USART_BAUD))
 
-# Enable system suspend modes
-K3_PM_SYSTEM_SUSPEND	:=	0
-$(eval $(call add_define,K3_PM_SYSTEM_SUSPEND))
-
 # Libraries
 include lib/xlat_tables_v2/xlat_tables.mk