tree 9ac3a9976037606760f09e42795688759f0f57d1
parent 38945f0a3db6d54d3cbc20632197781eb1324d7c
author Marek Vasut <marex@denx.de> 1701378871 +0100
committer Marek Vasut <marex@denx.de> 1701496058 +0100

fix(imx8m): align 3200 MTps rate with U-Boot

The 3200 MTps DRAM and its 800 MHz PLL setting in U-Boot is set to
M=300 P=9 S=0 , so 24 MHz * 300 / 9 / 2^0 = 800 MHz ~ 3200 MTps (x4) .
Make sure the PLL settings are aligned across software components.

Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: I163f81696be213acf6ecebe89ff2c76d41484cc5