fix(imx8m): align 3200 MTps rate with U-Boot
The 3200 MTps DRAM and its 800 MHz PLL setting in U-Boot is set to
M=300 P=9 S=0 , so 24 MHz * 300 / 9 / 2^0 = 800 MHz ~ 3200 MTps (x4) .
Make sure the PLL settings are aligned across software components.
Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: I163f81696be213acf6ecebe89ff2c76d41484cc5
diff --git a/plat/imx/imx8m/ddr/clock.c b/plat/imx/imx8m/ddr/clock.c
index 4d0b261..f23e410 100644
--- a/plat/imx/imx8m/ddr/clock.c
+++ b/plat/imx/imx8m/ddr/clock.c
@@ -97,7 +97,7 @@
mmio_write_32(DRAM_PLL_CTRL + 0x4, (311 << 12) | (4 << 4) | 1);
break;
case 3200:
- mmio_write_32(DRAM_PLL_CTRL + 0x4, (200 << 12) | (3 << 4) | 1);
+ mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (9 << 4) | 0);
break;
case 2400:
mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (3 << 4) | 2);