Tegra132: set TZDRAM_BASE to 0xF5C00000
The TZDRAM base on the reference platform has been bumped up due to
some BL2 memory cleanup. Platforms can also use a different TZDRAM
base by setting TZDRAM_BASE=<value> in the build command line.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md
index 6c76dd1..d8e8ec6 100644
--- a/docs/plat/nvidia-tegra.md
+++ b/docs/plat/nvidia-tegra.md
@@ -59,6 +59,9 @@
'CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> all'
+Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>'
+to the build command line.
+
Power Management
================
The PSCI implementation expects each platform to expose the 'power state'
diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index 1be13e9..69d6296 100644
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -31,7 +31,7 @@
TEGRA_BOOT_UART_BASE := 0x70006300
$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
-TZDRAM_BASE := 0xF1C00000
+TZDRAM_BASE := 0xF5C00000
$(eval $(call add_define,TZDRAM_BASE))
PLATFORM_CLUSTER_COUNT := 1