Merge "dts: stm32mp157c: fix etzpc node location in DTSI file" into integration
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 258f73d..591f2f8 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -227,11 +227,10 @@
- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
-For Hercules, the following errata build flags are defined :
+For Cortex-A78, the following errata build flags are defined :
-- ``ERRATA_HERCULES_1688305``: This applies errata 1688305 workaround to
- Hercules CPU. This needs to be enabled only for revision r0p0 - r1p0 of
- the CPU.
+- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
+ CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
For Neoverse N1, the following errata build flags are defined :
@@ -338,7 +337,7 @@
--------------
-*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_a78.h
similarity index 64%
rename from include/lib/cpus/aarch64/cortex_hercules.h
rename to include/lib/cpus/aarch64/cortex_a78.h
index d5ca85e..0d4712b 100644
--- a/include/lib/cpus/aarch64/cortex_hercules.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,34 +1,34 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef CORTEX_HERCULES_H
-#define CORTEX_HERCULES_H
+#ifndef CORTEX_A78_H
+#define CORTEX_A78_H
#include <lib/utils_def.h>
-#define CORTEX_HERCULES_MIDR U(0x410FD410)
+#define CORTEX_A78_MIDR U(0x410FD410)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_HERCULES_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
-#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
+#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
+#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
-#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1
-#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
+#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
+#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
@@ -38,7 +38,7 @@
#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
-#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF)
-#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7)
+#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
+#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
-#endif /* CORTEX_HERCULES_H */
+#endif /* CORTEX_A78_H */
diff --git a/include/lib/cpus/aarch64/cortex_hercules_ae.h b/include/lib/cpus/aarch64/cortex_hercules_ae.h
index 795563b..73c22f7 100644
--- a/include/lib/cpus/aarch64/cortex_hercules_ae.h
+++ b/include/lib/cpus/aarch64/cortex_hercules_ae.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#ifndef CORTEX_HERCULES_AE_H
#define CORTEX_HERCULES_AE_H
-#include <cortex_hercules.h>
+#include <cortex_a78.h>
#define CORTEX_HERCULES_AE_MIDR U(0x410FD420)
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
new file mode 100644
index 0000000..9914f12
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a78.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+
+/* --------------------------------------------------
+ * Errata Workaround for A78 Erratum 1688305.
+ * This applies to revision r0p0 and r1p0 of A78.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78_1688305_wa
+ /* Compare x0 against revision r1p0 */
+ mov x17, x30
+ bl check_errata_1688305
+ cbz x0, 1f
+ mrs x1, CORTEX_A78_ACTLR2_EL1
+ orr x1, x1, CORTEX_A78_ACTLR2_EL1_BIT_1
+ msr CORTEX_A78_ACTLR2_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_a78_1688305_wa
+
+func check_errata_1688305
+ /* Applies to r0p0 and r1p0 */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_1688305
+
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A78
+ * -------------------------------------------------
+ */
+func cortex_a78_reset_func
+ mov x19, x30
+ bl cpu_get_rev_var
+ mov x18, x0
+
+#if ERRATA_A78_1688305
+ mov x0, x18
+ bl errata_a78_1688305_wa
+#endif
+
+#if ENABLE_AMU
+ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
+ mrs x0, actlr_el3
+ bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
+ msr actlr_el3, x0
+
+ /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
+ mrs x0, actlr_el2
+ bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
+ msr actlr_el2, x0
+
+ /* Enable group0 counters */
+ mov x0, #CORTEX_A78_AMU_GROUP0_MASK
+ msr CPUAMCNTENSET0_EL0, x0
+
+ /* Enable group1 counters */
+ mov x0, #CORTEX_A78_AMU_GROUP1_MASK
+ msr CPUAMCNTENSET1_EL0, x0
+#endif
+
+ isb
+ ret x19
+endfunc cortex_a78_reset_func
+
+ /* ---------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ---------------------------------------------
+ */
+func cortex_a78_core_pwr_dwn
+ /* ---------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------
+ */
+ mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+ msr CORTEX_A78_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_a78_core_pwr_dwn
+
+ /*
+ * Errata printing function for cortex_a78. Must follow AAPCS.
+ */
+#if REPORT_ERRATA
+func cortex_a78_errata_report
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata ERRATA_A78_1688305, cortex_a78, 1688305
+
+ ldp x8, x30, [sp], #16
+ ret
+endfunc cortex_a78_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides cortex_a78 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a78_regs, "aS"
+cortex_a78_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a78_cpu_reg_dump
+ adr x6, cortex_a78_regs
+ mrs x8, CORTEX_A78_CPUECTLR_EL1
+ ret
+endfunc cortex_a78_cpu_reg_dump
+
+declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \
+ cortex_a78_reset_func, \
+ cortex_a78_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_hercules.S b/lib/cpus/aarch64/cortex_hercules.S
deleted file mode 100644
index a239196..0000000
--- a/lib/cpus/aarch64/cortex_hercules.S
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_hercules.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-
-/* --------------------------------------------------
- * Errata Workaround for Hercules Erratum 1688305.
- * This applies to revision r0p0 and r1p0 of Hercules.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_hercules_1688305_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1688305
- cbz x0, 1f
- mrs x1, CORTEX_HERCULES_ACTLR2_EL1
- orr x1, x1, CORTEX_HERCULES_ACTLR2_EL1_BIT_1
- msr CORTEX_HERCULES_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_hercules_1688305_wa
-
-func check_errata_1688305
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1688305
-
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-Hercules
- * -------------------------------------------------
- */
-func cortex_hercules_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_HERCULES_1688305
- mov x0, x18
- bl errata_hercules_1688305_wa
-#endif
-
-#if ENABLE_AMU
- /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
- msr actlr_el3, x0
-
- /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
- msr actlr_el2, x0
-
- /* Enable group0 counters */
- mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
- msr CPUAMCNTENSET0_EL0, x0
-
- /* Enable group1 counters */
- mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
- msr CPUAMCNTENSET1_EL0, x0
-#endif
-
- isb
- ret x19
-endfunc cortex_hercules_reset_func
-
- /* ---------------------------------------------
- * HW will do the cache maintenance while powering down
- * ---------------------------------------------
- */
-func cortex_hercules_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_hercules_core_pwr_dwn
-
- /*
- * Errata printing function for cortex_hercules. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_hercules_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_HERCULES_1688305, cortex_hercules, 1688305
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_hercules_errata_report
-#endif
-
- /* ---------------------------------------------
- * This function provides cortex_hercules specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_hercules_regs, "aS"
-cortex_hercules_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_hercules_cpu_reg_dump
- adr x6, cortex_hercules_regs
- mrs x8, CORTEX_HERCULES_CPUECTLR_EL1
- ret
-endfunc cortex_hercules_cpu_reg_dump
-
-declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
- cortex_hercules_reset_func, \
- cortex_hercules_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_hercules_ae.S b/lib/cpus/aarch64/cortex_hercules_ae.S
index c4a2163..4452c41 100644
--- a/lib/cpus/aarch64/cortex_hercules_ae.S
+++ b/lib/cpus/aarch64/cortex_hercules_ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,20 +24,20 @@
func cortex_hercules_ae_reset_func
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
- bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el3, x0
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
mrs x0, actlr_el2
- bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
msr actlr_el2, x0
/* Enable group0 counters */
- mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
+ mov x0, #CORTEX_A78_AMU_GROUP0_MASK
msr CPUAMCNTENSET0_EL0, x0
/* Enable group1 counters */
- mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
+ mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
isb
@@ -54,9 +54,9 @@
* Enable CPU power down bit in power control register
* -------------------------------------------------------
*/
- mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0
+ mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+ msr CORTEX_A78_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_hercules_ae_core_pwr_dwn
@@ -85,7 +85,7 @@
func cortex_hercules_ae_cpu_reg_dump
adr x6, cortex_hercules_ae_regs
- mrs x8, CORTEX_HERCULES_CPUECTLR_EL1
+ mrs x8, CORTEX_A78_CPUECTLR_EL1
ret
endfunc cortex_hercules_ae_cpu_reg_dump
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 3c0c9cd..1bc082d 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -251,8 +251,8 @@
ERRATA_A76_1286807 ?=0
# Flag to apply erratum 1688305 workaround during reset. This erratum applies
-# to revisions r0p0 - r1p0 of the Hercules cpu.
-ERRATA_HERCULES_1688305 ?=0
+# to revisions r0p0 - r1p0 of the A78 cpu.
+ERRATA_A78_1688305 ?=0
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
@@ -487,9 +487,9 @@
$(eval $(call assert_boolean,ERRATA_A76_1286807))
$(eval $(call add_define,ERRATA_A76_1286807))
-# Process ERRATA_HERCULES_1688305 flag
-$(eval $(call assert_boolean,ERRATA_HERCULES_1688305))
-$(eval $(call add_define,ERRATA_HERCULES_1688305))
+# Process ERRATA_A78_1688305 flag
+$(eval $(call assert_boolean,ERRATA_A78_1688305))
+$(eval $(call add_define,ERRATA_A78_1688305))
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 0d0d010..7039a6d 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -58,10 +58,10 @@
FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/cortex_a77.S \
+ lib/cpus/aarch64/cortex_a78.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_zeus.S \
- lib/cpus/aarch64/cortex_hercules.S \
lib/cpus/aarch64/cortex_hercules_ae.S \
lib/cpus/aarch64/cortex_a65.S \
lib/cpus/aarch64/cortex_a65ae.S
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 33531f3..024e682 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -129,10 +129,10 @@
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/cortex_a77.S \
+ lib/cpus/aarch64/cortex_a78.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_zeus.S \
- lib/cpus/aarch64/cortex_hercules.S \
lib/cpus/aarch64/cortex_hercules_ae.S \
lib/cpus/aarch64/cortex_klein.S \
lib/cpus/aarch64/cortex_matterhorn.S \
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index d6ed766..0500740 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -203,6 +203,13 @@
k3_gic_cpuif_enable();
}
+static void __dead2 k3_system_off(void)
+{
+ ERROR("System Off: operation not handled.\n");
+ while (true)
+ wfi();
+}
+
static void __dead2 k3_system_reset(void)
{
/* Send the system reset request to system firmware */
@@ -232,6 +239,7 @@
.pwr_domain_on = k3_pwr_domain_on,
.pwr_domain_off = k3_pwr_domain_off,
.pwr_domain_on_finish = k3_pwr_domain_on_finish,
+ .system_off = k3_system_off,
.system_reset = k3_system_reset,
.validate_power_state = k3_validate_power_state,
.validate_ns_entrypoint = k3_validate_ns_entrypoint