rcar_gen3: drivers: qos: H3: Drop extra level of nesting
The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7b55a6fa53145ff0427e05656234917f486031df
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
index 0557b79..906d158 100644
--- a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
@@ -188,30 +188,28 @@
io_write_32(QOSCTRL_REF_ARS,
((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
- {
- uint32_t i;
+ uint32_t i;
- for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
- io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
- io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
- io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
- io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
- }
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+ }
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
- for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
- io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
- qoswt_fix[i]);
- io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
- qoswt_fix[i]);
- }
- for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
- io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
- io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
- }
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+ qoswt_fix[i]);
+ io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+ qoswt_fix[i]);
}
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+ io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
/* AXI setting */
io_write_32(AXI_MMCR, 0x00010008U);