refactor(xilinx): create generic function for clock retrieval
Refactors the code in the AMD-Xilinx platform for Versal and Versal NET
to create a more generic function for obtaining clock signals
from the platform. The new function get_uart_clk is specific to each
platform and providing greater flexibility for clock signal retrieval
in various parts of the codebase.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Iff67315339b2651c9bea73af0d89fcbad2bb332a
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c
index b2de411..df18814 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_common.c
+++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c
@@ -88,6 +88,30 @@
platform_version / 10U, platform_version % 10U);
}
+uint32_t get_uart_clk(void)
+{
+ uint32_t uart_clock;
+
+ switch (platform_id) {
+ case VERSAL_NET_SPP:
+ uart_clock = 1000000;
+ break;
+ case VERSAL_NET_EMU:
+ uart_clock = 25000000;
+ break;
+ case VERSAL_NET_QEMU:
+ uart_clock = 25000000;
+ break;
+ case VERSAL_NET_SILICON:
+ uart_clock = 100000000;
+ break;
+ default:
+ panic();
+ }
+
+ return uart_clock;
+}
+
void versal_net_config_setup(void)
{
uint32_t val;
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index a70095d..7e877a4 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -69,33 +69,29 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- uint32_t uart_clock;
int32_t rc;
#if !(TFA_NO_PM)
uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0};
uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE;
enum pm_ret_status ret_status;
#endif /* !(TFA_NO_PM) */
+ uint32_t uart_clk = get_uart_clk();
board_detection();
switch (platform_id) {
case VERSAL_NET_SPP:
cpu_clock = 1000000;
- uart_clock = 1000000;
break;
case VERSAL_NET_EMU:
cpu_clock = 3660000;
- uart_clock = 25000000;
break;
case VERSAL_NET_QEMU:
/* Random values now */
cpu_clock = 100000000;
- uart_clock = 25000000;
break;
case VERSAL_NET_SILICON:
cpu_clock = 100000000;
- uart_clock = 100000000;
break;
default:
panic();
@@ -105,7 +101,7 @@
static console_t versal_net_runtime_console;
/* Initialize the console to provide early debug support */
- rc = console_pl011_register(UART_BASE, uart_clock,
+ rc = console_pl011_register(UART_BASE, uart_clk,
UART_BAUDRATE,
&versal_net_runtime_console);
if (rc == 0) {
diff --git a/plat/xilinx/versal_net/include/plat_private.h b/plat/xilinx/versal_net/include/plat_private.h
index be75bfd..3eb8052 100644
--- a/plat/xilinx/versal_net/include/plat_private.h
+++ b/plat/xilinx/versal_net/include/plat_private.h
@@ -18,6 +18,7 @@
} versal_intr_info_type_el3_t;
void versal_net_config_setup(void);
+uint32_t get_uart_clk(void);
const mmap_region_t *plat_versal_net_get_mmap(void);