Disable PL011 UART before configuring it
The PL011 TRM (ARM DDI 0183G) specifies that the UART must be
disabled before any of the control registers are programmed. The
PL011 driver included in TF does not disable the UART, so the
initialization in BL2 and BL31 is violating this requirement
(and potentially in BL1 if the UART is enabled after reset).
This patch modifies the initialization function in the PL011
console driver to disable the UART before programming the
control registers.
Register clobber list and documentation updated.
Fixes ARM-software/tf-issues#300
Change-Id: I839b2d681d48b03f821ac53663a6a78e8b30a1a1
diff --git a/drivers/arm/pl011/pl011_console.S b/drivers/arm/pl011/pl011_console.S
index 47608da..f29f895 100644
--- a/drivers/arm/pl011/pl011_console.S
+++ b/drivers/arm/pl011/pl011_console.S
@@ -54,7 +54,7 @@
* w1 - Uart clock in Hz
* w2 - Baud rate
* Out: return 1 on success else 0 on error
- * Clobber list : x1, x2
+ * Clobber list : x1, x2, x3, x4
* -----------------------------------------------
*/
func console_core_init
@@ -64,6 +64,20 @@
/* Check baud rate and uart clock for sanity */
cbz w1, core_init_fail
cbz w2, core_init_fail
+ /* Disable uart before programming */
+ ldr w3, [x0, #UARTCR]
+ mov w4, #PL011_UARTCR_UARTEN
+ bic w3, w3, w4
+ str w3, [x0, #UARTCR]
+ /* Flush the transmit FIFO */
+ ldr w3, [x0, #UARTLCR_H]
+ mov w4, #PL011_UARTLCR_H_FEN
+ bic w3, w3, w4
+ str w3, [x0, #UARTLCR_H]
+ /* Wait for the end of Tx of current character */
+busy_loop:
+ ldr w3, [x0, #UARTFR]
+ tbnz w3, #PL011_UARTFR_BUSY_BIT, busy_loop
/* Program the baudrate */
/* Divisor = (Uart clock * 4) / baudrate */
lsl w1, w1, #2
diff --git a/drivers/console/console.S b/drivers/console/console.S
index b772363..797b564 100644
--- a/drivers/console/console.S
+++ b/drivers/console/console.S
@@ -54,7 +54,7 @@
* w1 - Uart clock in Hz
* w2 - Baud rate
* out: return 1 on success else 0 on error
- * Clobber list : x1 - x3
+ * Clobber list : x1 - x4
* -----------------------------------------------
*/
func console_init