diff --git a/plat/intel/soc/stratix10/include/s10_memory_controller.h b/plat/intel/soc/stratix10/include/s10_memory_controller.h
index ad7cb9d..155b279 100644
--- a/plat/intel/soc/stratix10/include/s10_memory_controller.h
+++ b/plat/intel/soc/stratix10/include/s10_memory_controller.h
@@ -22,8 +22,6 @@
 #define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value)	\
 						(((value) & 0x00000060) >> 5)
 
-#define S10_RSTMGR_BRGMODRST				0xffd1102c
-#define S10_RSTMGR_BRGMODRST_DDRSCH			0x00000040
 
 #define S10_MPFE_HMC_ADP_ECCCTRL1			0xf8011100
 #define S10_MPFE_HMC_ADP_ECCCTRL2			0xf8011104
diff --git a/plat/intel/soc/stratix10/include/s10_reset_manager.h b/plat/intel/soc/stratix10/include/s10_reset_manager.h
index 731a8dd..40e7bac 100644
--- a/plat/intel/soc/stratix10/include/s10_reset_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_reset_manager.h
@@ -9,7 +9,9 @@
 
 #define S10_RSTMGR_PER0MODRST				0xffd11024
 #define S10_RSTMGR_PER1MODRST				0xffd11028
-#define S10_RSTMGR_HDSKEN					0xffd11010
+#define S10_RSTMGR_HDSKEN				0xffd11010
+#define S10_RSTMGR_BRGMODRST                            0xffd1102c
+
 
 #define S10_RSTMGR_PER0MODRST_EMAC0			0x00000001
 #define S10_RSTMGR_PER0MODRST_EMAC1			0x00000002
@@ -80,8 +82,18 @@
 #define S10_RSTMGR_PER0MODRST_DMAIF6		0x40000000
 #define S10_RSTMGR_PER0MODRST_DMAIF7		0x80000000
 
+#define BRGMODRST_DDRSCH_MASK			0x40
+#define BRGMODRST_F2SSDRAM2_MASK		0x20
+#define BRGMODRST_F2SSDRAM1_MASK		0x10
+#define BRGMODRST_F2SSDRAM_MASK			0x08
+#define BRGMODRST_FPGA2SOC_MASK			0x04
+#define BRGMODRST_LWHPS2FPGA_MASK		0x02
+#define BRGMODRST_SOC2FPGA_MASK			0x01
+
 void deassert_peripheral_reset(void);
 void config_hps_hs_before_warm_reset(void);
+int socfpga_bridges_enable(void);
+int socfpga_bridges_disable(void);
 
 #endif
 
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
index 8c51181..c34fcf7 100644
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@@ -69,6 +69,17 @@
 #define SYSMGR_MMC				0x28
 #define SYSMGR_MMC_DRVSEL(x)			(((x) & 0x7) << 0)
 
+#define SYSMGR_NOC_TIMEOUT			0xc0
+#define SYSMGR_NOC_IDLEREQ_SET			0xc4
+#define SYSMGR_NOC_IDLEREQ_CLR			0xc8
+#define SYSMGR_NOC_IDLEREQ_VAL			0xcc
+#define SYSMGR_NOC_IDLEACK			0xd0
+#define SYSMGR_NOC_IDLESTATUS			0xd4
+
+#define IDLE_DATA_LWSOC2FPGA			BIT(0)
+#define IDLE_DATA_SOC2FPGA			BIT(4)
+#define IDLE_DATA_MASK	(IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
+
 #define SYSMGR_BOOT_SCRATCH_COLD_0		0x200
 #define SYSMGR_BOOT_SCRATCH_COLD_1		0x204
 #define SYSMGR_BOOT_SCRATCH_COLD_2		0x208