commit e73c51188d3f0eaabb6860dab34d1c9c7e7a03cb
author Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Mon Oct 21 16:35:08 2019 +0800
committer Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Thu Jan 16 10:53:21 2020 +0800
tree 343107e0fba2fc261de6a67c4037931c06390f1f
parent 3afb87afabbf269fa918d2fc94218af796e9ccae

intel: Enable bridge access in Intel platform

Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f

plat/intel/soc/agilex/bl2_plat_setup.c

diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index 0366f50..d160279 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -74,6 +74,8 @@
 	socfpga_delay_timer_init();
 	init_ncore_ccu();
 	init_hard_memory_controller();
+	mailbox_init();
+	socfpga_bridges_enable();
 }
 
 
@@ -106,8 +108,6 @@
 	info.mmc_dev_type = MMC_IS_SD;
 	info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
 
-	mailbox_init();
-
 	switch (boot_source) {
 	case BOOT_SOURCE_SDMMC:
 		dw_mmc_init(&params, &info);