rcar_gen3: drivers: qos: Fix checkpatch issues
Fix checkpatch issues, clean up macro indentation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id0f1e322b44562f9863e885583d89fbf47cab91b
diff --git a/drivers/staging/renesas/rcar/qos/qos_common.h b/drivers/staging/renesas/rcar/qos/qos_common.h
index c3a83ac..64a89f8 100644
--- a/drivers/staging/renesas/rcar/qos/qos_common.h
+++ b/drivers/staging/renesas/rcar/qos/qos_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,98 +7,106 @@
#ifndef QOS_COMMON_H
#define QOS_COMMON_H
-#define RCAR_REF_DEFAULT (0U)
+#define RCAR_REF_DEFAULT 0U
/* define used for get_refperiod. */
/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
-#define REFPERIOD_CYCLE ((126 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
+#define REFPERIOD_CYCLE /* unit:ns */ \
+ ((126 * BASE_SUB_SLOT_NUM * 1000U) / 400)
#else /* REF option */
-#define REFPERIOD_CYCLE ((252 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
+#define REFPERIOD_CYCLE /* unit:ns */ \
+ ((252 * BASE_SUB_SLOT_NUM * 1000U) / 400)
#endif
#if (RCAR_LSI == RCAR_E3)
/* define used for E3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_E3 (0xAFU) /* 175 */
+#define SUB_SLOT_CYCLE_E3 0xAFU /* 175 */
#else /* REF 7.8usec */
-#define SUB_SLOT_CYCLE_E3 (0x15EU) /* 350 */
+#define SUB_SLOT_CYCLE_E3 0x15EU /* 350 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-#define OPERATING_FREQ_E3 (266U) /* MHz */
-#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
-/* #define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */ /* unit:ns */
+#define OPERATING_FREQ_E3 266U /* MHz */
+#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 - 1U)
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
/* define used for M3N */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
-#define SUB_SLOT_CYCLE_M3N (0x7EU) /* 126 */
+#define SUB_SLOT_CYCLE_M3N 0x7EU /* 126 */
#else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_M3N (0xFCU) /* 252 */
+#define SUB_SLOT_CYCLE_M3N 0xFCU /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U)
-#define QOSWT_WTSET0_CYCLE_M3N ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
+#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N - 1U)
+#define QOSWT_WTSET0_CYCLE_M3N /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
/* define used for H3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
-#define SUB_SLOT_CYCLE_H3_20 (0x7EU) /* 126 */
+#define SUB_SLOT_CYCLE_H3_20 0x7EU /* 126 */
#else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_H3_20 (0xFCU) /* 252 */
+#define SUB_SLOT_CYCLE_H3_20 0xFCU /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U)
-#define QOSWT_WTSET0_CYCLE_H3_20 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
+#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 - 1U)
+#define QOSWT_WTSET0_CYCLE_H3_20 /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
/* define used for H3 Cut 30 */
#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */
-#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 -1U)
-#define QOSWT_WTSET0_CYCLE_H3_30 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
+#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 - 1U)
+#define QOSWT_WTSET0_CYCLE_H3_30 /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#endif
#if (RCAR_LSI == RCAR_H3N)
/* define used for H3N */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
-#define SUB_SLOT_CYCLE_H3N (0x7EU) /* 126 */
+#define SUB_SLOT_CYCLE_H3N 0x7EU /* 126 */
#else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_H3N (0xFCU) /* 252 */
+#define SUB_SLOT_CYCLE_H3N 0xFCU /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U)
-#define QOSWT_WTSET0_CYCLE_H3N ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
+#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N - 1U)
+#define QOSWT_WTSET0_CYCLE_H3N /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
/* define used for M3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
-#define SUB_SLOT_CYCLE_M3_11 (0x7EU) /* 126 */
-#define SUB_SLOT_CYCLE_M3_30 (0x7EU) /* 126 */
+#define SUB_SLOT_CYCLE_M3_11 0x7EU /* 126 */
+#define SUB_SLOT_CYCLE_M3_30 0x7EU /* 126 */
#else /* REF 3.9usec */
-#define SUB_SLOT_CYCLE_M3_11 (0xFCU) /* 252 */
-#define SUB_SLOT_CYCLE_M3_30 (0xFCU) /* 252 */
+#define SUB_SLOT_CYCLE_M3_11 0xFCU /* 252 */
+#define SUB_SLOT_CYCLE_M3_30 0xFCU /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
-#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
-#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 -1U)
-#define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
-#define QOSWT_WTSET0_CYCLE_M3_30 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
+#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 - 1U)
+#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 - 1U)
+#define QOSWT_WTSET0_CYCLE_M3_11 /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#define QOSWT_WTSET0_CYCLE_M3_30 /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#endif
-#define OPERATING_FREQ (400U) /* MHz */
-#define BASE_SUB_SLOT_NUM (0x6U)
-#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
+#define OPERATING_FREQ 400U /* MHz */
+#define BASE_SUB_SLOT_NUM 0x6U
+#define SUB_SLOT_CYCLE 0x7EU /* 126 */
-#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
+#define QOSWT_WTSET0_CYCLE /* unit:ns */ \
+ ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#define SL_INIT_REFFSSLOT (0x3U << 24U)
#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
-#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE -1U)
+#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U)
static inline void io_write_32(uintptr_t addr, uint32_t value)
{