diff --git a/Makefile b/Makefile
index f91699c..da3e493 100644
--- a/Makefile
+++ b/Makefile
@@ -449,10 +449,6 @@
 DTC_CPPFLAGS		+=	-P -nostdinc -Iinclude -Ifdts -undef \
 				-x assembler-with-cpp $(DEFINES)
 
-ifeq ($(MEASURED_BOOT),1)
-DTC_CPPFLAGS		+=	-DMEASURED_BOOT -DBL2_HASH_SIZE=${TCG_DIGEST_SIZE}
-endif
-
 ################################################################################
 # Common sources and include directories
 ################################################################################
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 797093e..2a3d838 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -259,7 +259,16 @@
 		(image_type == SECURE) ? "secure" : "normal");
 	print_entry_point_info(next_image_info);
 	cm_init_my_context(next_image_info);
-	cm_prepare_el3_exit(image_type);
+
+	/*
+	* If we are entering the Non-secure world, use
+	* 'cm_prepare_el3_exit_ns' to exit.
+	*/
+	if (image_type == NON_SECURE) {
+		cm_prepare_el3_exit_ns();
+	} else {
+		cm_prepare_el3_exit(image_type);
+	}
 }
 
 /*******************************************************************************
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index 3c27aff..5e3575f 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -656,7 +656,6 @@
 	sense_data_t *sense;
 	unsigned char data[CACHE_WRITEBACK_GRANULE << 1];
 	uintptr_t buf;
-	int result;
 	int retry;
 
 	assert((ufs_params.reg_base != 0) &&
@@ -693,14 +692,12 @@
 		/* logical block length in bytes */
 		*size = be32toh(*(unsigned int *)(buf + 4));
 	} while (retry);
-	(void)result;
 }
 
 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size)
 {
 	utp_utrd_t utrd;
 	resp_upiu_t *resp;
-	int result;
 
 	assert((ufs_params.reg_base != 0) &&
 	       (ufs_params.desc_base != 0) &&
@@ -711,7 +708,6 @@
 	dump_upiu(&utrd);
 #endif
 	resp = (resp_upiu_t *)utrd.resp_upiu;
-	(void)result;
 	return size - resp->res_trans_cnt;
 }
 
@@ -719,7 +715,6 @@
 {
 	utp_utrd_t utrd;
 	resp_upiu_t *resp;
-	int result;
 
 	assert((ufs_params.reg_base != 0) &&
 	       (ufs_params.desc_base != 0) &&
@@ -730,7 +725,6 @@
 	dump_upiu(&utrd);
 #endif
 	resp = (resp_upiu_t *)utrd.resp_upiu;
-	(void)result;
 	return size - resp->res_trans_cnt;
 }
 
diff --git a/fdts/stm32mp131.dtsi b/fdts/stm32mp131.dtsi
index dff1b33..adf7a91 100644
--- a/fdts/stm32mp131.dtsi
+++ b/fdts/stm32mp131.dtsi
@@ -26,26 +26,6 @@
 		};
 	};
 
-	nvmem_layout: nvmem_layout@0 {
-		compatible = "st,stm32-nvmem-layout";
-
-		nvmem-cells = <&cfg0_otp>,
-			      <&part_number_otp>,
-			      <&monotonic_otp>,
-			      <&nand_otp>,
-			      <&nand2_otp>,
-			      <&uid_otp>,
-			      <&hw2_otp>;
-
-		nvmem-cell-names = "cfg0_otp",
-				   "part_number_otp",
-				   "monotonic_otp",
-				   "nand_otp",
-				   "nand2_otp",
-				   "uid_otp",
-				   "hw2_otp";
-	};
-
 	clocks {
 		clk_csi: clk-csi {
 			#clock-cells = <0>;
diff --git a/fdts/stm32mp135f-dk.dts b/fdts/stm32mp135f-dk.dts
index 0fa064b..6240381 100644
--- a/fdts/stm32mp135f-dk.dts
+++ b/fdts/stm32mp135f-dk.dts
@@ -175,28 +175,6 @@
 	status = "okay";
 };
 
-&nvmem_layout {
-	nvmem-cells = <&cfg0_otp>,
-		      <&part_number_otp>,
-		      <&monotonic_otp>,
-		      <&nand_otp>,
-		      <&nand2_otp>,
-		      <&uid_otp>,
-		      <&hw2_otp>,
-		      <&pkh_otp>,
-		      <&board_id>;
-
-	nvmem-cell-names = "cfg0_otp",
-			   "part_number_otp",
-			   "monotonic_otp",
-			   "nand_otp",
-			   "nand2_otp",
-			   "uid_otp",
-			   "hw2_otp",
-			   "pkh_otp",
-			   "board_id";
-};
-
 &pka {
 	secure-status = "okay";
 };
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
index 454e124..63cc917 100644
--- a/fdts/stm32mp151.dtsi
+++ b/fdts/stm32mp151.dtsi
@@ -24,26 +24,6 @@
 		};
 	};
 
-	nvmem_layout: nvmem_layout@0 {
-		compatible = "st,stm32-nvmem-layout";
-
-		nvmem-cells = <&cfg0_otp>,
-			      <&part_number_otp>,
-			      <&monotonic_otp>,
-			      <&nand_otp>,
-			      <&uid_otp>,
-			      <&package_otp>,
-			      <&hw2_otp>;
-
-		nvmem-cell-names = "cfg0_otp",
-				   "part_number_otp",
-				   "monotonic_otp",
-				   "nand_otp",
-				   "uid_otp",
-				   "package_otp",
-				   "hw2_otp";
-	};
-
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index 44c7016..659e8bf 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -195,26 +195,6 @@
 	status = "okay";
 };
 
-&nvmem_layout {
-	nvmem-cells = <&cfg0_otp>,
-		      <&part_number_otp>,
-		      <&monotonic_otp>,
-		      <&nand_otp>,
-		      <&uid_otp>,
-		      <&package_otp>,
-		      <&hw2_otp>,
-		      <&board_id>;
-
-	nvmem-cell-names = "cfg0_otp",
-			   "part_number_otp",
-			   "monotonic_otp",
-			   "nand_otp",
-			   "uid_otp",
-			   "package_otp",
-			   "hw2_otp",
-			   "board_id";
-};
-
 &pwr_regulators {
 	vdd-supply = <&vdd>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;
diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
index 2eb3a57..05eb46a 100644
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -183,26 +183,6 @@
 	secure-status = "okay";
 };
 
-&nvmem_layout {
-	nvmem-cells = <&cfg0_otp>,
-		      <&part_number_otp>,
-		      <&monotonic_otp>,
-		      <&nand_otp>,
-		      <&uid_otp>,
-		      <&package_otp>,
-		      <&hw2_otp>,
-		      <&board_id>;
-
-	nvmem-cell-names = "cfg0_otp",
-			   "part_number_otp",
-			   "monotonic_otp",
-			   "nand_otp",
-			   "uid_otp",
-			   "package_otp",
-			   "hw2_otp",
-			   "board_id";
-};
-
 &pwr_regulators {
 	vdd-supply = <&vdd>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index d2d12e5..3a09383 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -220,20 +220,17 @@
 #define CTX_TTBR1_EL2		U(0x1a0)
 #define CTX_VDISR_EL2		U(0x1a8)
 #define CTX_VSESR_EL2		U(0x1b0)
-#define CTX_VSTCR_EL2		U(0x1b8)
-#define CTX_VSTTBR_EL2		U(0x1c0)
-#define CTX_SDER32_EL2		U(0x1c8)
-#define CTX_VNCR_EL2		U(0x1d0)
-#define CTX_TRFCR_EL2		U(0x1d8)
+#define CTX_VNCR_EL2		U(0x1b8)
+#define CTX_TRFCR_EL2		U(0x1c0)
 
 // Starting with Armv8.5
-#define CTX_SCXTNUM_EL2		U(0x1e0)
+#define CTX_SCXTNUM_EL2		U(0x1c8)
 
 // Register for FEAT_HCX
-#define CTX_HCRX_EL2            U(0x1e8)
+#define CTX_HCRX_EL2            U(0x1d0)
 
 /* Align to the next 16 byte boundary */
-#define CTX_EL2_SYSREGS_END	U(0x1f0)
+#define CTX_EL2_SYSREGS_END	U(0x1e0)
 
 #endif /* CTX_INCLUDE_EL2_REGS */
 
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index 2090687..1a76d8e 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,6 +34,7 @@
 			      const struct entry_point_info *ep);
 void cm_setup_context(cpu_context_t *ctx, const struct entry_point_info *ep);
 void cm_prepare_el3_exit(uint32_t security_state);
+void cm_prepare_el3_exit_ns(void);
 
 #ifdef __aarch64__
 #if CTX_INCLUDE_EL2_REGS
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 3ef378c..af8edf5 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -332,3 +332,12 @@
 		enable_extensions_nonsecure(el2_unused);
 	}
 }
+
+/*******************************************************************************
+ * This function is used to exit to Non-secure world. It simply calls the
+ * cm_prepare_el3_exit function for AArch32.
+ ******************************************************************************/
+void cm_prepare_el3_exit_ns(void)
+{
+	cm_prepare_el3_exit(NON_SECURE);
+}
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 0432d96..69acc2f 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -188,25 +188,6 @@
 	stp	x11, x12, [x0, #CTX_VDISR_EL2]
 #endif /* RAS_EXTENSION */
 
-#if ENABLE_FEAT_SEL2
-	/*
-	 * VSTCR_EL2 and VSTTBR_EL2 registers are saved only
-	 * when FEAT_SEL2 is supported.
-	 */
-	mrs	x13, vstcr_el2
-	mrs	x14, vsttbr_el2
-	stp	x13, x14, [x0, #CTX_VSTCR_EL2]
-#endif /* ENABLE_FEAT_SEL2 */
-
-#if CTX_INCLUDE_AARCH32_REGS && ENABLE_FEAT_SEL2
-	/*
-	 * SDER32_EL2 register is saved only when EL2 and EL1
-	 * capable of using Aarch32 and FEAT_SEL2 is supported.
-	 */
-	mrs	x15, sder32_el2
-	str	x15, [x0, #CTX_SDER32_EL2]
-#endif /* CTX_INCLUDE_AARCH32_REGS && ENABLE_FEAT_SEL2 */
-
 #if CTX_INCLUDE_NEVE_REGS
 	/*
 	 * VNCR_EL2 register is saved only when FEAT_NV2 is supported.
@@ -401,25 +382,6 @@
 	msr	vsesr_el2, x12
 #endif /* RAS_EXTENSION */
 
-#if ENABLE_FEAT_SEL2
-	/*
-	 * VSTCR_EL2 and VSTTBR_EL2 registers are restored only when FEAT_SEL2
-	 * is supported.
-	 */
-	ldp	x13, x14, [x0, #CTX_VSTCR_EL2]
-	msr	vstcr_el2, x13
-	msr	vsttbr_el2, x14
-#endif /* ENABLE_FEAT_SEL2 */
-
-#if CTX_INCLUDE_AARCH32_REGS && ENABLE_FEAT_SEL2
-	/*
-	 * SDER32_EL2 register is restored only when EL2 and EL1 capable of using
-	 * Aarch32 and FEAT_SEL2 is supported.
-	 */
-	ldr	x15, [x0, #CTX_SDER32_EL2]
-	msr	sder32_el2, x15
-#endif /* CTX_INCLUDE_AARCH32_REGS && ENABLE_FEAT_SEL2 */
-
 #if CTX_INCLUDE_NEVE_REGS
 	/*
 	 * VNCR_EL2 register is restored only when FEAT_NV2 is supported.
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index c69dc95..459ca2c 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,6 +16,7 @@
 #include <bl31/interrupt_mgmt.h>
 #include <common/bl_common.h>
 #include <context.h>
+#include <drivers/arm/gicv3.h>
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/el3_runtime/pubsub_events.h>
 #include <lib/extensions/amu.h>
@@ -31,54 +32,158 @@
 
 static void manage_extensions_secure(cpu_context_t *ctx);
 
-/*******************************************************************************
- * Context management library initialisation routine. This library is used by
- * runtime services to share pointers to 'cpu_context' structures for the secure
- * and non-secure states. Management of the structures and their associated
- * memory is not done by the context management library e.g. the PSCI service
- * manages the cpu context used for entry from and exit to the non-secure state.
- * The Secure payload dispatcher service manages the context(s) corresponding to
- * the secure state. It also uses this library to get access to the non-secure
- * state cpu context pointers.
- * Lastly, this library provides the api to make SP_EL3 point to the cpu context
- * which will used for programming an entry into a lower EL. The same context
- * will used to save state upon exception entry from that EL.
- ******************************************************************************/
-void __init cm_init(void)
+/******************************************************************************
+ * This function performs initializations that are specific to SECURE state
+ * and updates the cpu context specified by 'ctx'.
+ *****************************************************************************/
+static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
 {
+	u_register_t scr_el3;
+	el3_state_t *state;
+
+	state = get_el3state_ctx(ctx);
+	scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
+
+#if defined(IMAGE_BL31) && !defined(SPD_spmd)
 	/*
-	 * The context management library has only global data to intialize, but
-	 * that will be done when the BSS is zeroed out
+	 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
+	 * indicated by the interrupt routing model for BL31.
 	 */
+	scr_el3 |= get_scr_el3_from_routing_model(SECURE);
+#endif
+
+#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
+	/* Get Memory Tagging Extension support level */
+	unsigned int mte = get_armv8_5_mte_support();
+#endif
+	/*
+	 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS
+	 * is set, or when MTE is only implemented at EL0.
+	 */
+#if CTX_INCLUDE_MTE_REGS
+	assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
+	scr_el3 |= SCR_ATA_BIT;
+#else
+	if (mte == MTE_IMPLEMENTED_EL0) {
+		scr_el3 |= SCR_ATA_BIT;
+	}
+#endif /* CTX_INCLUDE_MTE_REGS */
+
+	/* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */
+	if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) {
+		if (GET_RW(ep->spsr) != MODE_RW_64) {
+			ERROR("S-EL2 can not be used in AArch32\n.");
+			panic();
+		}
+
+		scr_el3 |= SCR_EEL2_BIT;
+	}
+
+	write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
+
+	manage_extensions_secure(ctx);
 }
 
+#if ENABLE_RME
+/******************************************************************************
+ * This function performs initializations that are specific to REALM state
+ * and updates the cpu context specified by 'ctx'.
+ *****************************************************************************/
+static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
+{
+	u_register_t scr_el3;
+	el3_state_t *state;
+
+	state = get_el3state_ctx(ctx);
+	scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
+
+	scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT;
+
+	write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
+}
+#endif /* ENABLE_RME */
+
+/******************************************************************************
+ * This function performs initializations that are specific to NON-SECURE state
+ * and updates the cpu context specified by 'ctx'.
+ *****************************************************************************/
+static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
+{
+	u_register_t scr_el3;
+	el3_state_t *state;
+
+	state = get_el3state_ctx(ctx);
+	scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
+
+	/* SCR_NS: Set the NS bit */
+	scr_el3 |= SCR_NS_BIT;
+
+#if !CTX_INCLUDE_PAUTH_REGS
+	/*
+	 * If the pointer authentication registers aren't saved during world
+	 * switches the value of the registers can be leaked from the Secure to
+	 * the Non-secure world. To prevent this, rather than enabling pointer
+	 * authentication everywhere, we only enable it in the Non-secure world.
+	 *
+	 * If the Secure world wants to use pointer authentication,
+	 * CTX_INCLUDE_PAUTH_REGS must be set to 1.
+	 */
+	scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
+#endif /* !CTX_INCLUDE_PAUTH_REGS */
+
+	/* Allow access to Allocation Tags when MTE is implemented. */
+	scr_el3 |= SCR_ATA_BIT;
+
+#ifdef IMAGE_BL31
+	/*
+	 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
+	 *  indicated by the interrupt routing model for BL31.
+	 */
+	scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
+#endif
+	write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
+
+	/* Initialize EL2 context registers */
+#if CTX_INCLUDE_EL2_REGS
+
+	/*
+	 * Initialize SCTLR_EL2 context register using Endianness value
+	 * taken from the entrypoint attribute.
+	 */
+	u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
+	sctlr_el2 |= SCTLR_EL2_RES1;
+	write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2,
+			sctlr_el2);
+
+	/*
+	 * The GICv3 driver initializes the ICC_SRE_EL2 register during
+	 * platform setup. Use the same setting for the corresponding
+	 * context register to make sure the correct bits are set when
+	 * restoring NS context.
+	 */
+	u_register_t icc_sre_el2 = read_icc_sre_el2();
+	icc_sre_el2 |= (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT);
+	icc_sre_el2 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
+	write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2,
+			icc_sre_el2);
+#endif /* CTX_INCLUDE_EL2_REGS */
+}
+
 /*******************************************************************************
- * The following function initializes the cpu_context 'ctx' for
- * first use, and sets the initial entrypoint state as specified by the
- * entry_point_info structure.
- *
- * The security state to initialize is determined by the SECURE attribute
- * of the entry_point_info.
+ * The following function performs initialization of the cpu_context 'ctx'
+ * for first use that is common to all security states, and sets the
+ * initial entrypoint state as specified by the entry_point_info structure.
  *
  * The EE and ST attributes are used to configure the endianness and secure
  * timer availability for the new execution context.
- *
- * To prepare the register state for entry call cm_prepare_el3_exit() and
- * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
- * cm_el1_sysregs_context_restore().
  ******************************************************************************/
-void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
+static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
 {
-	unsigned int security_state;
 	u_register_t scr_el3;
 	el3_state_t *state;
 	gp_regs_t *gp_regs;
 	u_register_t sctlr_elx, actlr_elx;
 
-	assert(ctx != NULL);
-
-	security_state = GET_SECURITY_STATE(ep->h.attr);
-
 	/* Clear any residual register values from the context */
 	zeromem(ctx, sizeof(*ctx));
 
@@ -93,26 +198,7 @@
 	 */
 	scr_el3 = read_scr();
 	scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
-			SCR_ST_BIT | SCR_HCE_BIT);
-
-#if ENABLE_RME
-	/* When RME support is enabled, clear the NSE bit as well. */
-	scr_el3 &= ~SCR_NSE_BIT;
-#endif /* ENABLE_RME */
-
-	/*
-	 * SCR_NS: Set the security state of the next EL.
-	 */
-	if (security_state == NON_SECURE) {
-		scr_el3 |= SCR_NS_BIT;
-	}
-
-#if ENABLE_RME
-	/* Check for realm state if RME support enabled. */
-	if (security_state == REALM) {
-		scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT;
-	}
-#endif /* ENABLE_RME */
+			SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT);
 
 	/*
 	 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
@@ -121,6 +207,7 @@
 	if (GET_RW(ep->spsr) == MODE_RW_64) {
 		scr_el3 |= SCR_RW_BIT;
 	}
+
 	/*
 	 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
 	 *  Secure timer registers to EL3, from AArch64 state only, if specified
@@ -149,8 +236,8 @@
 #if !HANDLE_EA_EL3_FIRST
 	/*
 	 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
-	 *  to EL3 when executing at a lower EL. When executing at EL3, External
-	 *  Aborts are taken to EL3.
+	 * to EL3 when executing at a lower EL. When executing at EL3, External
+	 * Aborts are taken to EL3.
 	 */
 	scr_el3 &= ~SCR_EA_BIT;
 #endif
@@ -159,69 +246,12 @@
 	/* Enable fault injection from lower ELs */
 	scr_el3 |= SCR_FIEN_BIT;
 #endif
-
-#if !CTX_INCLUDE_PAUTH_REGS
-	/*
-	 * If the pointer authentication registers aren't saved during world
-	 * switches the value of the registers can be leaked from the Secure to
-	 * the Non-secure world. To prevent this, rather than enabling pointer
-	 * authentication everywhere, we only enable it in the Non-secure world.
-	 *
-	 * If the Secure world wants to use pointer authentication,
-	 * CTX_INCLUDE_PAUTH_REGS must be set to 1.
-	 */
-	if (security_state == NON_SECURE) {
-		scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
-	}
-#endif /* !CTX_INCLUDE_PAUTH_REGS */
-
-#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
-	/* Get Memory Tagging Extension support level */
-	unsigned int mte = get_armv8_5_mte_support();
-#endif
-	/*
-	 * Enable MTE support. Support is enabled unilaterally for the normal
-	 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
-	 * set.
-	 */
-#if CTX_INCLUDE_MTE_REGS
-	assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
-	scr_el3 |= SCR_ATA_BIT;
-#else
-	/*
-	 * When MTE is only implemented at EL0, it can be enabled
-	 * across both worlds as no MTE registers are used.
-	 */
-	if ((mte == MTE_IMPLEMENTED_EL0) ||
-	/*
-	 * When MTE is implemented at all ELs, it can be only enabled
-	 * in Non-Secure world without register saving.
-	 */
-	  (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) &&
-	    (security_state == NON_SECURE))) {
-		scr_el3 |= SCR_ATA_BIT;
-	}
-#endif	/* CTX_INCLUDE_MTE_REGS */
 
-#ifdef IMAGE_BL31
 	/*
-	 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
-	 *  indicated by the interrupt routing model for BL31.
-	 *
-	 * TODO: The interrupt routing model code is not updated for REALM
-	 * state. Use the default values of IRQ = FIQ = 0 for REALM security
-	 * state for now.
+	 * CPTR_EL3 was initialized out of reset, copy that value to the
+	 * context register.
 	 */
-	if (security_state != REALM) {
-		scr_el3 |= get_scr_el3_from_routing_model(security_state);
-	}
-#endif
-
-	/* Save the initialized value of CPTR_EL3 register */
 	write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3());
-	if (security_state == SECURE) {
-		manage_extensions_secure(ctx);
-	}
 
 	/*
 	 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
@@ -249,16 +279,6 @@
 		}
 	}
 
-	/* Enable S-EL2 if the next EL is EL2 and security state is secure */
-	if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) {
-		if (GET_RW(ep->spsr) != MODE_RW_64) {
-			ERROR("S-EL2 can not be used in AArch32.");
-			panic();
-		}
-
-		scr_el3 |= SCR_EEL2_BIT;
-	}
-
 	/*
 	 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3
 	 * and EL2, when clear, this bit traps accesses from EL2 so we set it
@@ -362,6 +382,66 @@
 }
 
 /*******************************************************************************
+ * Context management library initialization routine. This library is used by
+ * runtime services to share pointers to 'cpu_context' structures for secure
+ * non-secure and realm states. Management of the structures and their associated
+ * memory is not done by the context management library e.g. the PSCI service
+ * manages the cpu context used for entry from and exit to the non-secure state.
+ * The Secure payload dispatcher service manages the context(s) corresponding to
+ * the secure state. It also uses this library to get access to the non-secure
+ * state cpu context pointers.
+ * Lastly, this library provides the API to make SP_EL3 point to the cpu context
+ * which will be used for programming an entry into a lower EL. The same context
+ * will be used to save state upon exception entry from that EL.
+ ******************************************************************************/
+void __init cm_init(void)
+{
+	/*
+	 * The context management library has only global data to intialize, but
+	 * that will be done when the BSS is zeroed out.
+	 */
+}
+
+/*******************************************************************************
+ * This is the high-level function used to initialize the cpu_context 'ctx' for
+ * first use. It performs initializations that are common to all security states
+ * and initializations specific to the security state specified in 'ep'
+ ******************************************************************************/
+void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
+{
+	unsigned int security_state;
+
+	assert(ctx != NULL);
+
+	/*
+	 * Perform initializations that are common
+	 * to all security states
+	 */
+	setup_context_common(ctx, ep);
+
+	security_state = GET_SECURITY_STATE(ep->h.attr);
+
+	/* Perform security state specific initializations */
+	switch (security_state) {
+	case SECURE:
+		setup_secure_context(ctx, ep);
+		break;
+#if ENABLE_RME
+	case REALM:
+		setup_realm_context(ctx, ep);
+		break;
+#endif
+	case NON_SECURE:
+		setup_ns_context(ctx, ep);
+		break;
+	default:
+		ERROR("Invalid security state\n");
+		panic();
+		break;
+	}
+}
+
+/*******************************************************************************
  * Enable architecture extensions on first entry to Non-secure world.
  * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
  * it is zero.
@@ -738,6 +818,40 @@
 #endif /* CTX_INCLUDE_EL2_REGS */
 
 /*******************************************************************************
+ * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
+ * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
+ * updating EL1 and EL2 registers. Otherwise, it calls the generic
+ * cm_prepare_el3_exit function.
+ ******************************************************************************/
+void cm_prepare_el3_exit_ns(void)
+{
+#if CTX_INCLUDE_EL2_REGS
+	cpu_context_t *ctx = cm_get_context(NON_SECURE);
+	assert(ctx != NULL);
+
+	/*
+	 * Currently some extensions are configured using
+	 * direct register updates. Therefore, do this here
+	 * instead of when setting up context.
+	 */
+	manage_extensions_nonsecure(0, ctx);
+
+	/*
+	 * Set the NS bit to be able to access the ICC_SRE_EL2
+	 * register when restoring context.
+	 */
+	write_scr_el3(read_scr_el3() | SCR_NS_BIT);
+
+	/* Restore EL2 and EL1 sysreg contexts */
+	cm_el2_sysregs_context_restore(NON_SECURE);
+	cm_el1_sysregs_context_restore(NON_SECURE);
+	cm_set_next_eret_context(NON_SECURE);
+#else
+	cm_prepare_el3_exit(NON_SECURE);
+#endif /* CTX_INCLUDE_EL2_REGS */
+}
+
+/*******************************************************************************
  * The next four functions are used by runtime services to save and restore
  * EL1 context on the 'cpu_context' structure for the specified security
  * state.
diff --git a/lib/extensions/mpam/mpam.c b/lib/extensions/mpam/mpam.c
index 65601dd..884d480 100644
--- a/lib/extensions/mpam/mpam.c
+++ b/lib/extensions/mpam/mpam.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,7 +27,6 @@
 	/*
 	 * If EL2 is implemented but unused, disable trapping to EL2 when lower
 	 * ELs access their own MPAM registers.
-	 * If EL2 is implemented and used, enable trapping to EL2.
 	 */
 	if (el2_unused) {
 		write_mpam2_el2(0ULL);
@@ -35,12 +34,5 @@
 		if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U) {
 			write_mpamhcr_el2(0ULL);
 		}
-	} else {
-		write_mpam2_el2(MPAM2_EL2_TRAPMPAM0EL1 |
-				MPAM2_EL2_TRAPMPAM1EL1);
-
-		if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U) {
-			write_mpamhcr_el2(MPAMHCR_EL2_TRAP_MPAMIDR_EL1);
-		}
 	}
 }
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index dd48e10..c70b377 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -229,5 +229,5 @@
 	 * information that we had stashed away during the cpu_on
 	 * call to set this cpu on its way.
 	 */
-	cm_prepare_el3_exit(NON_SECURE);
+	cm_prepare_el3_exit_ns();
 }
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index da9f328..ffe3a91 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -331,5 +331,5 @@
 	 * information that we had stashed away during the suspend
 	 * call to set this cpu on its way.
 	 */
-	cm_prepare_el3_exit(NON_SECURE);
+	cm_prepare_el3_exit_ns();
 }
diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
index 3ee396c..fe521a9 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
@@ -57,8 +57,8 @@
 	{
 		.image_id = TOS_FW_CONFIG_ID,
 		.image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE,
-		.image_info.image_max_size = CORSTONE1000_TOS_FW_CONFIG_LIMIT - \
-			CORSTONE1000_TOS_FW_CONFIG_BASE,
+		.image_info.image_max_size = (CORSTONE1000_TOS_FW_CONFIG_LIMIT -
+					      CORSTONE1000_TOS_FW_CONFIG_BASE),
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
 			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
index a96baae..0235f8b 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
@@ -34,12 +34,13 @@
 {
 	const struct plat_io_policy *policy;
 	/*
-	* metadata for firmware update is written at 0x0000 offset of the flash.
-	* PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted.
-	* As per firmware update spec, at a given point of time, only one bank is active.
-	* This means, TF-A should boot from the same bank as TF-M.
-	*/
+	 * metadata for firmware update is written at 0x0000 offset of the flash.
+	 * PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted.
+	 * As per firmware update spec, at a given point of time, only one bank
+	 * is active. This means, TF-A should boot from the same bank as TF-M.
+	 */
 	volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG);
+
 	if (*boot_bank_flag > 1) {
 		VERBOSE("Boot_bank is set higher than possible values");
 	}
diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
index 98dea79..4b0a791 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
@@ -21,8 +21,8 @@
 	*(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL;
 	*watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE;
 	while (1) {
-		 wfi();
-	 }
+		wfi();
+	}
 }
 
 plat_psci_ops_t plat_arm_psci_pm_ops = {
diff --git a/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
index cec7332..7e8fbb2 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
@@ -38,8 +38,8 @@
  */
 int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
 {
-    *nv_ctr = CORSTONE1000_FW_NVCTR_VAL;
-    return 0;
+	*nv_ctr = CORSTONE1000_FW_NVCTR_VAL;
+	return 0;
 }
 
 /*
@@ -49,5 +49,5 @@
  */
 int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
 {
-    return 0;
+	return 0;
 }
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
index 2523d72..584d485 100644
--- a/plat/arm/board/corstone1000/common/include/platform_def.h
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -16,11 +16,11 @@
 #include <plat/common/common_def.h>
 #include <plat/arm/soc/common/soc_css_def.h>
 
-#define ARM_ROTPK_HEADER_LEN					19
-#define ARM_ROTPK_HASH_LEN					32
+#define ARM_ROTPK_HEADER_LEN		19
+#define ARM_ROTPK_HASH_LEN		32
 
 /* Special value used to verify platform parameters from BL2 to BL31 */
-#define ARM_BL31_PLAT_PARAM_VAL					ULL(0x0f1e2d3c4b5a6978)
+#define ARM_BL31_PLAT_PARAM_VAL		ULL(0x0f1e2d3c4b5a6978)
 
 /* PL011 UART related constants */
 #ifdef V2M_IOFPGA_UART0_CLK_IN_HZ
@@ -31,368 +31,324 @@
 #undef V2M_IOFPGA_UART1_CLK_IN_HZ
 #endif
 
-#define V2M_IOFPGA_UART0_CLK_IN_HZ				50000000
-#define V2M_IOFPGA_UART1_CLK_IN_HZ				50000000
+#define V2M_IOFPGA_UART0_CLK_IN_HZ	50000000
+#define V2M_IOFPGA_UART1_CLK_IN_HZ	50000000
 
 /* Core/Cluster/Thread counts for corstone1000 */
-#define CORSTONE1000_CLUSTER_COUNT				U(1)
-#define CORSTONE1000_MAX_CPUS_PER_CLUSTER			U(4)
-#define CORSTONE1000_MAX_PE_PER_CPU				U(1)
-#define CORSTONE1000_PRIMARY_CPU				U(0)
+#define CORSTONE1000_CLUSTER_COUNT		U(1)
+#define CORSTONE1000_MAX_CPUS_PER_CLUSTER	U(4)
+#define CORSTONE1000_MAX_PE_PER_CPU		U(1)
+#define CORSTONE1000_PRIMARY_CPU		U(0)
 
-#define PLAT_ARM_CLUSTER_COUNT					CORSTONE1000_CLUSTER_COUNT
+#define PLAT_ARM_CLUSTER_COUNT		CORSTONE1000_CLUSTER_COUNT
 
-#define PLATFORM_CORE_COUNT					(PLAT_ARM_CLUSTER_COUNT *      \
-								CORSTONE1000_MAX_CPUS_PER_CLUSTER *  \
-								CORSTONE1000_MAX_PE_PER_CPU)
+#define PLATFORM_CORE_COUNT		(PLAT_ARM_CLUSTER_COUNT * \
+					 CORSTONE1000_MAX_CPUS_PER_CLUSTER * \
+					 CORSTONE1000_MAX_PE_PER_CPU)
 
 /* UART related constants */
-#define PLAT_ARM_BOOT_UART_BASE					0x1a510000
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ				V2M_IOFPGA_UART0_CLK_IN_HZ
-#define PLAT_ARM_RUN_UART_BASE					0x1a520000
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ				V2M_IOFPGA_UART1_CLK_IN_HZ
-#define ARM_CONSOLE_BAUDRATE					115200
-#define PLAT_ARM_CRASH_UART_BASE				PLAT_ARM_RUN_UART_BASE
-#define PLAT_ARM_CRASH_UART_CLK_IN_HZ				PLAT_ARM_RUN_UART_CLK_IN_HZ
+#define PLAT_ARM_BOOT_UART_BASE		0x1a510000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ	V2M_IOFPGA_UART0_CLK_IN_HZ
+#define PLAT_ARM_RUN_UART_BASE		0x1a520000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ	V2M_IOFPGA_UART1_CLK_IN_HZ
+#define ARM_CONSOLE_BAUDRATE		115200
+#define PLAT_ARM_CRASH_UART_BASE	PLAT_ARM_RUN_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ	PLAT_ARM_RUN_UART_CLK_IN_HZ
 
 /* Memory related constants */
 
 /* SRAM (CVM) memory layout
  *
  * <ARM_TRUSTED_SRAM_BASE>
- *
- *         partition size: sizeof(meminfo_t) = 16 bytes
- *
- *         content: memory info area used by the next BL
+ *	partition size: sizeof(meminfo_t) = 16 bytes
+ *	content: memory info area used by the next BL
  *
  * <ARM_FW_CONFIG_BASE>
- *
- *         partition size: 4080 bytes
+ *	partition size: 4080 bytes
  *
  * <ARM_BL2_MEM_DESC_BASE>
- *
- *         partition size: 4 KB
- *
- *         content:
- *
- *             Area where BL2 copies the images descriptors
+ *	partition size: 4 KB
+ *	content: Area where BL2 copies the images descriptors
  *
  * <ARM_BL_RAM_BASE> = <BL32_BASE>
- *
- *         partition size: 688 KB
- *
- *         content:
- *
- *             BL32 (optee-os)
+ *	partition size: 688 KB
+ *	content: BL32 (optee-os)
  *
  * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
- *
- *         partition size: 8 KB
- *
- *         content:
- *
- *             BL32 config (TOS_FW_CONFIG)
+ *	partition size: 8 KB
+ *	content: BL32 config (TOS_FW_CONFIG)
  *
  * <BL31_BASE>
- *
- *         partition size: 140 KB
- *
- *         content:
- *
- *             BL31
+ *	partition size: 140 KB
+ *	content: BL31
  *
  * <BL2_SIGNATURE_BASE>
- *
- *     partition size: 4 KB
- *
- *     content:
- *
- *         MCUBOOT data needed to verify TF-A BL2
+ *	partition size: 4 KB
+ *	content: MCUBOOT data needed to verify TF-A BL2
  *
  * <BL2_BASE>
- *
- *     partition size: 176 KB
- *
- *         content:
- *
- *             BL2
+ *	partition size: 176 KB
+ *	content: BL2
  *
  * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
- *
- *         partition size: 512 KB
- *
- *         content:
- *
- *             BL33 (u-boot)
+ *	partition size: 512 KB
+ *	content: BL33 (u-boot)
  */
 
 /* DDR memory */
-#define ARM_DRAM1_BASE						UL(0x80000000)
-#define ARM_DRAM1_SIZE                 				(SZ_2G) /* 2GB*/
-#define ARM_DRAM1_END						(ARM_DRAM1_BASE +	\
-								ARM_DRAM1_SIZE - 1)
+#define ARM_DRAM1_BASE		UL(0x80000000)
+#define ARM_DRAM1_SIZE		(SZ_2G)  /* 2GB*/
+#define ARM_DRAM1_END		(ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1)
 
 /* DRAM1 and DRAM2 are the same for corstone1000 */
-#define ARM_DRAM2_BASE						ARM_DRAM1_BASE
-#define ARM_DRAM2_SIZE						ARM_DRAM1_SIZE
-#define ARM_DRAM2_END						ARM_DRAM1_END
+#define ARM_DRAM2_BASE		ARM_DRAM1_BASE
+#define ARM_DRAM2_SIZE		ARM_DRAM1_SIZE
+#define ARM_DRAM2_END		ARM_DRAM1_END
 
-#define ARM_NS_DRAM1_BASE					ARM_DRAM1_BASE
-#define ARM_NS_DRAM1_SIZE					ARM_DRAM1_SIZE
-#define ARM_NS_DRAM1_END					(ARM_NS_DRAM1_BASE +\
-								ARM_NS_DRAM1_SIZE - 1)
+#define ARM_NS_DRAM1_BASE	ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE	ARM_DRAM1_SIZE
+#define ARM_NS_DRAM1_END	(ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1)
 
 /* The first 8 KB of Trusted SRAM are used as shared memory */
-#define ARM_TRUSTED_SRAM_BASE					UL(0x02000000)
-#define ARM_SHARED_RAM_SIZE					(SZ_8K)  /* 8 KB */
-#define ARM_SHARED_RAM_BASE					ARM_TRUSTED_SRAM_BASE
+#define ARM_TRUSTED_SRAM_BASE	UL(0x02000000)
+#define ARM_SHARED_RAM_SIZE	(SZ_8K)  /* 8 KB */
+#define ARM_SHARED_RAM_BASE	ARM_TRUSTED_SRAM_BASE
 
 /* The remaining Trusted SRAM is used to load the BL images */
-#define TOTAL_SRAM_SIZE						(SZ_4M) /* 4 MB */
+#define TOTAL_SRAM_SIZE		(SZ_4M)  /* 4 MB */
 
-/* Last 512KB of CVM is allocated for shared RAM
- * as an example openAMP */
-#define ARM_NS_SHARED_RAM_SIZE					(512 * SZ_1K)
+/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */
+#define ARM_NS_SHARED_RAM_SIZE	(512 * SZ_1K)
 
-#define PLAT_ARM_TRUSTED_SRAM_SIZE				(TOTAL_SRAM_SIZE - \
-								ARM_NS_SHARED_RAM_SIZE - \
-								ARM_SHARED_RAM_SIZE)
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	(TOTAL_SRAM_SIZE - \
+					 ARM_NS_SHARED_RAM_SIZE - \
+					 ARM_SHARED_RAM_SIZE)
 
-#define PLAT_ARM_MAX_BL2_SIZE					(180 * SZ_1K)  /* 180 KB */
+#define PLAT_ARM_MAX_BL2_SIZE	(180 * SZ_1K)  /* 180 KB */
 
-#define PLAT_ARM_MAX_BL31_SIZE					(140 * SZ_1K)  /* 140 KB */
+#define PLAT_ARM_MAX_BL31_SIZE	(140 * SZ_1K)  /* 140 KB */
 
-#define ARM_BL_RAM_BASE						(ARM_SHARED_RAM_BASE +  \
-								ARM_SHARED_RAM_SIZE)
-#define ARM_BL_RAM_SIZE						(PLAT_ARM_TRUSTED_SRAM_SIZE - \
-								ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_BASE		(ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE		(PLAT_ARM_TRUSTED_SRAM_SIZE - \
+				 ARM_SHARED_RAM_SIZE)
 
-#define BL2_SIGNATURE_SIZE					(SZ_4K)  /* 4 KB */
+#define BL2_SIGNATURE_SIZE	(SZ_4K)  /* 4 KB */
 
-#define BL2_SIGNATURE_BASE					(BL2_LIMIT - \
-								PLAT_ARM_MAX_BL2_SIZE)
-#define BL2_BASE						(BL2_LIMIT - \
-								PLAT_ARM_MAX_BL2_SIZE + \
-								BL2_SIGNATURE_SIZE)
-#define BL2_LIMIT						(ARM_BL_RAM_BASE + \
-								ARM_BL_RAM_SIZE)
+#define BL2_SIGNATURE_BASE	(BL2_LIMIT - PLAT_ARM_MAX_BL2_SIZE)
+#define BL2_BASE		(BL2_LIMIT - \
+				 PLAT_ARM_MAX_BL2_SIZE + \
+				 BL2_SIGNATURE_SIZE)
+#define BL2_LIMIT		(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 
-#define BL31_BASE						(BL2_SIGNATURE_BASE - \
-								PLAT_ARM_MAX_BL31_SIZE)
-#define BL31_LIMIT						BL2_SIGNATURE_BASE
+#define BL31_BASE		(BL2_SIGNATURE_BASE - PLAT_ARM_MAX_BL31_SIZE)
+#define BL31_LIMIT		BL2_SIGNATURE_BASE
 
-#define CORSTONE1000_TOS_FW_CONFIG_BASE				(BL31_BASE - \
-								CORSTONE1000_TOS_FW_CONFIG_SIZE)
-#define CORSTONE1000_TOS_FW_CONFIG_SIZE				(SZ_8K)  /* 8 KB */
-#define CORSTONE1000_TOS_FW_CONFIG_LIMIT			BL31_BASE
+#define CORSTONE1000_TOS_FW_CONFIG_BASE		(BL31_BASE - \
+						 CORSTONE1000_TOS_FW_CONFIG_SIZE)
+#define CORSTONE1000_TOS_FW_CONFIG_SIZE		(SZ_8K)  /* 8 KB */
+#define CORSTONE1000_TOS_FW_CONFIG_LIMIT	BL31_BASE
 
-#define BL32_BASE						ARM_BL_RAM_BASE
-#define PLAT_ARM_MAX_BL32_SIZE					(CORSTONE1000_TOS_FW_CONFIG_BASE - \
-								BL32_BASE)
+#define BL32_BASE		ARM_BL_RAM_BASE
+#define PLAT_ARM_MAX_BL32_SIZE	(CORSTONE1000_TOS_FW_CONFIG_BASE - BL32_BASE)
 
-#define BL32_LIMIT						(BL32_BASE + \
-								PLAT_ARM_MAX_BL32_SIZE)
+#define BL32_LIMIT		(BL32_BASE + PLAT_ARM_MAX_BL32_SIZE)
 
 /* SPD_spmd settings */
 
-#define PLAT_ARM_SPMC_BASE					BL32_BASE
-#define PLAT_ARM_SPMC_SIZE					PLAT_ARM_MAX_BL32_SIZE
+#define PLAT_ARM_SPMC_BASE	BL32_BASE
+#define PLAT_ARM_SPMC_SIZE	PLAT_ARM_MAX_BL32_SIZE
 
 /* NS memory */
 
 /* The last 512KB of the SRAM is allocated as shared memory */
-#define ARM_NS_SHARED_RAM_BASE					(ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \
-								(PLAT_ARM_MAX_BL31_SIZE + \
-								PLAT_ARM_MAX_BL32_SIZE))
+#define ARM_NS_SHARED_RAM_BASE	(ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \
+				 (PLAT_ARM_MAX_BL31_SIZE + \
+				  PLAT_ARM_MAX_BL32_SIZE))
 
-#define BL33_BASE						ARM_DRAM1_BASE
-#define PLAT_ARM_MAX_BL33_SIZE					(12 * SZ_1M) /* 12 MB*/
-#define BL33_LIMIT						(ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
+#define BL33_BASE		ARM_DRAM1_BASE
+#define PLAT_ARM_MAX_BL33_SIZE	(12 * SZ_1M)  /* 12 MB*/
+#define BL33_LIMIT		(ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
 
 /* end of the definition of SRAM memory layout */
 
 /* NOR Flash */
 
-#define PLAT_ARM_BOOT_BANK_FLAG					UL(0x08002000)
-#define PLAT_ARM_FIP_BASE_BANK0					UL(0x081EF000)
-#define PLAT_ARM_FIP_BASE_BANK1					UL(0x0916F000)
-#define PLAT_ARM_FIP_MAX_SIZE					UL(0x1ff000)  /* 1.996 MB */
+#define PLAT_ARM_BOOT_BANK_FLAG		UL(0x08002000)
+#define PLAT_ARM_FIP_BASE_BANK0		UL(0x081EF000)
+#define PLAT_ARM_FIP_BASE_BANK1		UL(0x0916F000)
+#define PLAT_ARM_FIP_MAX_SIZE		UL(0x1ff000)  /* 1.996 MB */
 
-#define PLAT_ARM_NVM_BASE					V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE					(SZ_32M)  /* 32 MB */
+#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE		(SZ_32M)  /* 32 MB */
 
-#define PLAT_ARM_FLASH_IMAGE_BASE				PLAT_ARM_FIP_BASE_BANK0
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE				PLAT_ARM_FIP_MAX_SIZE
+#define PLAT_ARM_FLASH_IMAGE_BASE	PLAT_ARM_FIP_BASE_BANK0
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	PLAT_ARM_FIP_MAX_SIZE
 
 /*
  * Some data must be aligned on the biggest cache line size in the platform.
  * This is known only to the platform as it might have a combination of
  * integrated and external caches.
  */
-#define CACHE_WRITEBACK_GRANULE					(U(1) << ARM_CACHE_WRITEBACK_SHIFT)
-#define ARM_CACHE_WRITEBACK_SHIFT				6
+#define CACHE_WRITEBACK_GRANULE		(U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+#define ARM_CACHE_WRITEBACK_SHIFT	6
 
 /*
  * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
  * FW_CONFIG is intended to host the device tree. Currently, This area is not
  * used because corstone1000 platform doesn't use a device tree at TF-A level.
  */
-#define ARM_FW_CONFIG_BASE					(ARM_SHARED_RAM_BASE \
-								+ sizeof(meminfo_t))
-#define ARM_FW_CONFIG_LIMIT					(ARM_SHARED_RAM_BASE \
-								+ (ARM_SHARED_RAM_SIZE >> 1))
+#define ARM_FW_CONFIG_BASE	(ARM_SHARED_RAM_BASE + sizeof(meminfo_t))
+#define ARM_FW_CONFIG_LIMIT	(ARM_SHARED_RAM_BASE + \
+				 (ARM_SHARED_RAM_SIZE >> 1))
 
 /*
  * Boot parameters passed from BL2 to BL31/BL32 are stored here
  */
-#define ARM_BL2_MEM_DESC_BASE					ARM_FW_CONFIG_LIMIT
-#define ARM_BL2_MEM_DESC_LIMIT					ARM_BL_RAM_BASE
+#define ARM_BL2_MEM_DESC_BASE	ARM_FW_CONFIG_LIMIT
+#define ARM_BL2_MEM_DESC_LIMIT	ARM_BL_RAM_BASE
 
 /*
  * The max number of regions like RO(code), coherent and data required by
  * different BL stages which need to be mapped in the MMU.
  */
-#define ARM_BL_REGIONS						3
-#define PLAT_ARM_MMAP_ENTRIES					8
-#define MAX_XLAT_TABLES						5
-#define MAX_MMAP_REGIONS					(PLAT_ARM_MMAP_ENTRIES + \
-								ARM_BL_REGIONS)
-#define MAX_IO_DEVICES						2
-#define MAX_IO_HANDLES						3
-#define MAX_IO_BLOCK_DEVICES					1
+#define ARM_BL_REGIONS		3
+#define PLAT_ARM_MMAP_ENTRIES	8
+#define MAX_XLAT_TABLES		5
+#define MAX_MMAP_REGIONS	(PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS)
+#define MAX_IO_DEVICES		2
+#define MAX_IO_HANDLES		3
+#define MAX_IO_BLOCK_DEVICES	1
 
 /* GIC related constants */
-#define PLAT_ARM_GICD_BASE					0x1C010000
-#define PLAT_ARM_GICC_BASE					0x1C02F000
+#define PLAT_ARM_GICD_BASE	0x1C010000
+#define PLAT_ARM_GICC_BASE	0x1C02F000
 
 /* MHUv2 Secure Channel receiver and sender */
-#define PLAT_SDK700_MHU0_SEND					0x1B800000
-#define PLAT_SDK700_MHU0_RECV					0x1B810000
+#define PLAT_SDK700_MHU0_SEND	0x1B800000
+#define PLAT_SDK700_MHU0_RECV	0x1B810000
 
 /* Timer/watchdog related constants */
-#define ARM_SYS_CNTCTL_BASE					UL(0x1a200000)
-#define ARM_SYS_CNTREAD_BASE					UL(0x1a210000)
-#define ARM_SYS_TIMCTL_BASE					UL(0x1a220000)
+#define ARM_SYS_CNTCTL_BASE	UL(0x1a200000)
+#define ARM_SYS_CNTREAD_BASE	UL(0x1a210000)
+#define ARM_SYS_TIMCTL_BASE	UL(0x1a220000)
 
-#define SECURE_WATCHDOG_ADDR_CTRL_REG				0x1A320000
-#define SECURE_WATCHDOG_ADDR_VAL_REG      			0x1A320008
-#define SECURE_WATCHDOG_MASK_ENABLE       			0x01
-#define SECURE_WATCHDOG_COUNTDOWN_VAL     			0x1000
+#define SECURE_WATCHDOG_ADDR_CTRL_REG	0x1A320000
+#define SECURE_WATCHDOG_ADDR_VAL_REG	0x1A320008
+#define SECURE_WATCHDOG_MASK_ENABLE	0x01
+#define SECURE_WATCHDOG_COUNTDOWN_VAL	0x1000
 
-#define SYS_COUNTER_FREQ_IN_TICKS				UL(50000000) /* 50MHz */
+#define SYS_COUNTER_FREQ_IN_TICKS	UL(50000000)  /* 50MHz */
 
-#define CORSTONE1000_IRQ_TZ_WDOG				32
-#define CORSTONE1000_IRQ_SEC_SYS_TIMER				34
+#define CORSTONE1000_IRQ_TZ_WDOG	32
+#define CORSTONE1000_IRQ_SEC_SYS_TIMER	34
 
-#define PLAT_MAX_PWR_LVL					2
+#define PLAT_MAX_PWR_LVL	2
 /*
  * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
  * power levels have a 1:1 mapping with the MPIDR affinity levels.
  */
-#define ARM_PWR_LVL0						MPIDR_AFFLVL0
-#define ARM_PWR_LVL1						MPIDR_AFFLVL1
-#define ARM_PWR_LVL2						MPIDR_AFFLVL2
+#define ARM_PWR_LVL0	MPIDR_AFFLVL0
+#define ARM_PWR_LVL1	MPIDR_AFFLVL1
+#define ARM_PWR_LVL2	MPIDR_AFFLVL2
 
 /*
  *  Macros for local power states in ARM platforms encoded by State-ID field
  *  within the power-state parameter.
  */
 /* Local power state for power domains in Run state. */
-#define ARM_LOCAL_STATE_RUN					U(0)
+#define ARM_LOCAL_STATE_RUN	U(0)
 /* Local power state for retention. Valid only for CPU power domains */
-#define ARM_LOCAL_STATE_RET					U(1)
+#define ARM_LOCAL_STATE_RET	U(1)
 /* Local power state for OFF/power-down. Valid for CPU and cluster
  * power domains
  */
-#define ARM_LOCAL_STATE_OFF					U(2)
+#define ARM_LOCAL_STATE_OFF	U(2)
 
-#define PLAT_ARM_TRUSTED_MAILBOX_BASE				ARM_TRUSTED_SRAM_BASE
-#define PLAT_ARM_NSTIMER_FRAME_ID				U(1)
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE	ARM_TRUSTED_SRAM_BASE
+#define PLAT_ARM_NSTIMER_FRAME_ID	U(1)
 
-#define PLAT_ARM_NS_IMAGE_BASE					(ARM_NS_SHARED_RAM_BASE)
+#define PLAT_ARM_NS_IMAGE_BASE		(ARM_NS_SHARED_RAM_BASE)
 
-#define PLAT_PHY_ADDR_SPACE_SIZE				(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE				(1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
 
 /*
  * This macro defines the deepest retention state possible. A higher state
  * ID will represent an invalid or a power down state.
  */
-#define PLAT_MAX_RET_STATE					1
+#define PLAT_MAX_RET_STATE	1
 
 /*
  * This macro defines the deepest power down states possible. Any state ID
  * higher than this is invalid.
  */
-#define PLAT_MAX_OFF_STATE					2
+#define PLAT_MAX_OFF_STATE	2
 
-#define PLATFORM_STACK_SIZE					UL(0x440)
+#define PLATFORM_STACK_SIZE	UL(0x440)
 
-#define CORSTONE1000_EXTERNAL_FLASH				MAP_REGION_FLAT(		\
-								PLAT_ARM_NVM_BASE,		\
-								PLAT_ARM_NVM_SIZE,		\
-								MT_DEVICE | MT_RO | MT_SECURE)
+#define CORSTONE1000_EXTERNAL_FLASH	MAP_REGION_FLAT( \
+					PLAT_ARM_NVM_BASE, \
+					PLAT_ARM_NVM_SIZE, \
+					MT_DEVICE | MT_RO | MT_SECURE)
 
-#define ARM_MAP_SHARED_RAM					MAP_REGION_FLAT(		\
-								ARM_SHARED_RAM_BASE,	\
-								ARM_SHARED_RAM_SIZE,	\
-								MT_MEMORY | MT_RW | MT_SECURE)
+#define ARM_MAP_SHARED_RAM	MAP_REGION_FLAT( \
+				ARM_SHARED_RAM_BASE, \
+				ARM_SHARED_RAM_SIZE, \
+				MT_MEMORY | MT_RW | MT_SECURE)
 
-#define ARM_MAP_NS_SHARED_RAM					MAP_REGION_FLAT(	\
-								ARM_NS_SHARED_RAM_BASE, \
-								ARM_NS_SHARED_RAM_SIZE, \
-								MT_MEMORY | MT_RW | MT_NS)
+#define ARM_MAP_NS_SHARED_RAM	MAP_REGION_FLAT( \
+				ARM_NS_SHARED_RAM_BASE, \
+				ARM_NS_SHARED_RAM_SIZE, \
+				MT_MEMORY | MT_RW | MT_NS)
 
-#define ARM_MAP_NS_DRAM1					MAP_REGION_FLAT(	\
-								ARM_NS_DRAM1_BASE,	\
-								ARM_NS_DRAM1_SIZE,	\
-								MT_MEMORY | MT_RW | MT_NS)
+#define ARM_MAP_NS_DRAM1	MAP_REGION_FLAT( \
+				ARM_NS_DRAM1_BASE, \
+				ARM_NS_DRAM1_SIZE, \
+				MT_MEMORY | MT_RW | MT_NS)
 
-#define ARM_MAP_BL_RO						MAP_REGION_FLAT(	\
-								BL_CODE_BASE,		\
-								BL_CODE_END		\
-								- BL_CODE_BASE, \
-								MT_CODE | MT_SECURE),	\
-								MAP_REGION_FLAT(	\
-								BL_RO_DATA_BASE,	\
-								BL_RO_DATA_END	\
-								- BL_RO_DATA_BASE,	\
-								MT_RO_DATA | MT_SECURE)
+#define ARM_MAP_BL_RO		MAP_REGION_FLAT( \
+				BL_CODE_BASE, \
+				(BL_CODE_END - BL_CODE_BASE), \
+				MT_CODE | MT_SECURE), \
+				MAP_REGION_FLAT( \
+				BL_RO_DATA_BASE, \
+				(BL_RO_DATA_END - BL_RO_DATA_BASE), \
+				MT_RO_DATA | MT_SECURE)
 #if USE_COHERENT_MEM
-#define ARM_MAP_BL_COHERENT_RAM					MAP_REGION_FLAT(	\
-								BL_COHERENT_RAM_BASE,	\
-								BL_COHERENT_RAM_END	\
-								- BL_COHERENT_RAM_BASE, \
-								MT_DEVICE | MT_RW | MT_SECURE)
+#define ARM_MAP_BL_COHERENT_RAM		MAP_REGION_FLAT( \
+					BL_COHERENT_RAM_BASE, \
+					(BL_COHERENT_RAM_END \
+					 - BL_COHERENT_RAM_BASE), \
+					MT_DEVICE | MT_RW | MT_SECURE)
 #endif
 
 /*
  * Map the region for the optional device tree configuration with read and
  * write permissions
  */
-#define ARM_MAP_BL_CONFIG_REGION				MAP_REGION_FLAT(	\
-								ARM_FW_CONFIG_BASE,	\
-								(ARM_FW_CONFIG_LIMIT-   \
-								ARM_FW_CONFIG_BASE),   \
-								MT_MEMORY | MT_RW | MT_SECURE)
+#define ARM_MAP_BL_CONFIG_REGION	MAP_REGION_FLAT( \
+					ARM_FW_CONFIG_BASE, \
+					(ARM_FW_CONFIG_LIMIT \
+					 - ARM_FW_CONFIG_BASE), \
+					MT_MEMORY | MT_RW | MT_SECURE)
 
-#define CORSTONE1000_DEVICE_BASE				(0x1A000000)
-#define CORSTONE1000_DEVICE_SIZE				(0x26000000)
-#define CORSTONE1000_MAP_DEVICE					MAP_REGION_FLAT(	\
-								CORSTONE1000_DEVICE_BASE,	\
-								CORSTONE1000_DEVICE_SIZE,	\
-								MT_DEVICE | MT_RW | MT_SECURE)
+#define CORSTONE1000_DEVICE_BASE	(0x1A000000)
+#define CORSTONE1000_DEVICE_SIZE	(0x26000000)
+#define CORSTONE1000_MAP_DEVICE		MAP_REGION_FLAT( \
+					CORSTONE1000_DEVICE_BASE, \
+					CORSTONE1000_DEVICE_SIZE, \
+					MT_DEVICE | MT_RW | MT_SECURE)
 
-#define ARM_IRQ_SEC_PHY_TIMER					29
+#define ARM_IRQ_SEC_PHY_TIMER	29
 
-#define ARM_IRQ_SEC_SGI_0					8
-#define ARM_IRQ_SEC_SGI_1					9
-#define ARM_IRQ_SEC_SGI_2					10
-#define ARM_IRQ_SEC_SGI_3					11
-#define ARM_IRQ_SEC_SGI_4					12
-#define ARM_IRQ_SEC_SGI_5					13
-#define ARM_IRQ_SEC_SGI_6					14
-#define ARM_IRQ_SEC_SGI_7					15
+#define ARM_IRQ_SEC_SGI_0	8
+#define ARM_IRQ_SEC_SGI_1	9
+#define ARM_IRQ_SEC_SGI_2	10
+#define ARM_IRQ_SEC_SGI_3	11
+#define ARM_IRQ_SEC_SGI_4	12
+#define ARM_IRQ_SEC_SGI_5	13
+#define ARM_IRQ_SEC_SGI_6	14
+#define ARM_IRQ_SEC_SGI_7	15
 
 /*
  * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
@@ -424,12 +380,14 @@
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
  * as Group 0 interrupts.
  */
-#define PLAT_ARM_G1S_IRQ_PROPS(grp)	\
-	ARM_G1S_IRQ_PROPS(grp), \
-	INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
-		(grp), GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \
-		GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
+#define PLAT_ARM_G1S_IRQ_PROPS(grp)				\
+		ARM_G1S_IRQ_PROPS(grp),				\
+		INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG,	\
+			GIC_HIGHEST_SEC_PRIORITY,		\
+			(grp), GIC_INTR_CFG_LEVEL),		\
+		INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER,	\
+			GIC_HIGHEST_SEC_PRIORITY,		\
+			(grp), GIC_INTR_CFG_LEVEL)
 
 #define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
 
diff --git a/plat/arm/common/aarch64/execution_state_switch.c b/plat/arm/common/aarch64/execution_state_switch.c
index bed929a..2353e6a 100644
--- a/plat/arm/common/aarch64/execution_state_switch.c
+++ b/plat/arm/common/aarch64/execution_state_switch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -162,7 +162,7 @@
 	 * calling EL.
 	 */
 	cm_init_my_context(&ep);
-	cm_prepare_el3_exit(NON_SECURE);
+	cm_prepare_el3_exit_ns();
 
 	/*
 	 * State switch success. The caller of SMC wouldn't see the SMC
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index ea71571..c9efeb5 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -11,8 +11,6 @@
 #include <common/fdt_wrappers.h>
 #include <drivers/st/regulator.h>
 #include <drivers/st/stm32_gpio.h>
-#include <drivers/st/stm32mp1_ddr.h>
-#include <drivers/st/stm32mp1_ram.h>
 #include <libfdt.h>
 
 #include <platform_def.h>
@@ -328,48 +326,32 @@
 int dt_find_otp_name(const char *name, uint32_t *otp, uint32_t *otp_len)
 {
 	int node;
-	int index, len;
+	int len;
 	const fdt32_t *cuint;
 
 	if ((name == NULL) || (otp == NULL)) {
 		return -FDT_ERR_BADVALUE;
 	}
 
-	node = fdt_node_offset_by_compatible(fdt, -1, DT_NVMEM_LAYOUT_COMPAT);
+	node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT);
 	if (node < 0) {
 		return node;
 	}
 
-	index = fdt_stringlist_search(fdt, node, "nvmem-cell-names", name);
-	if (index < 0) {
-		return index;
-	}
-
-	cuint = fdt_getprop(fdt, node, "nvmem-cells", &len);
-	if (cuint == NULL) {
-		return -FDT_ERR_NOTFOUND;
-	}
-
-	if ((index * (int)sizeof(uint32_t)) > len) {
-		return -FDT_ERR_BADVALUE;
-	}
-
-	cuint += index;
-
-	node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
+	node = fdt_subnode_offset(fdt, node, name);
 	if (node < 0) {
-		ERROR("Malformed nvmem_layout node: ignored\n");
+		ERROR("nvmem node %s not found\n", name);
 		return node;
 	}
 
 	cuint = fdt_getprop(fdt, node, "reg", &len);
 	if ((cuint == NULL) || (len != (2 * (int)sizeof(uint32_t)))) {
-		ERROR("Malformed nvmem_layout node: ignored\n");
+		ERROR("Malformed nvmem node %s: ignored\n", name);
 		return -FDT_ERR_BADVALUE;
 	}
 
 	if (fdt32_to_cpu(*cuint) % sizeof(uint32_t)) {
-		ERROR("Misaligned nvmem_layout element: ignored\n");
+		ERROR("Misaligned nvmem %s element: ignored\n", name);
 		return -FDT_ERR_BADVALUE;
 	}
 
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index d869978..017e3b1 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -621,7 +621,6 @@
 #define DT_DDR_COMPAT			"st,stm32mp1-ddr"
 #endif
 #define DT_IWDG_COMPAT			"st,stm32mp1-iwdg"
-#define DT_NVMEM_LAYOUT_COMPAT		"st,stm32-nvmem-layout"
 #define DT_PWR_COMPAT			"st,stm32mp1,pwr-reg"
 #if STM32MP13
 #define DT_RCC_CLK_COMPAT		"st,stm32mp13-rcc"
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index cf5ff7b..746419e 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -60,10 +60,6 @@
 
 	cm_set_context(&(rmm_ctx->cpu_ctx), REALM);
 
-	/* Save the current el1/el2 context before loading realm context. */
-	cm_el1_sysregs_context_save(NON_SECURE);
-	cm_el2_sysregs_context_save(NON_SECURE);
-
 	/* Restore the realm context assigned above */
 	cm_el1_sysregs_context_restore(REALM);
 	cm_el2_sysregs_context_restore(REALM);
@@ -72,14 +68,15 @@
 	/* Enter RMM */
 	rc = rmmd_rmm_enter(&rmm_ctx->c_rt_ctx);
 
-	/* Save realm context */
+	/*
+	 * Save realm context. EL1 and EL2 Non-secure
+	 * contexts will be restored before exiting to
+	 * Non-secure world, therefore there is no need
+	 * to clear EL1 and EL2 context registers.
+	 */
 	cm_el1_sysregs_context_save(REALM);
 	cm_el2_sysregs_context_save(REALM);
 
-	/* Restore the el1/el2 context again. */
-	cm_el1_sysregs_context_restore(NON_SECURE);
-	cm_el2_sysregs_context_restore(NON_SECURE);
-
 	return rc;
 }