diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index a7ab650..e1abe14 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -350,7 +350,7 @@
 			.override_enable = OVERRIDE_ ## access \
 		}
 
-#endif /* __ASSMEBLY__ */
+#endif /* __ASSEMBLY__ */
 
 /*******************************************************************************
  * TZDRAM carveout configuration registers
@@ -367,15 +367,35 @@
 #define MC_VIDEO_PROTECT_SIZE_MB			0x64c
 
 /*******************************************************************************
- * TZRAM carveout configuration registers
+ * TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers
  ******************************************************************************/
-#define MC_TZRAM_BASE					0x1850
-#define MC_TZRAM_END					0x1854
-#define MC_TZRAM_HI_ADDR_BITS				0x1588
- #define TZRAM_ADDR_HI_BITS_MASK			0x3
- #define TZRAM_END_HI_BITS_SHIFT			8
-#define MC_TZRAM_REG_CTRL				0x185c
- #define DISABLE_TZRAM_ACCESS				1
+#define MC_TZRAM_BASE_LO				0x2194
+#define  TZRAM_BASE_LO_SHIFT				12
+#define  TZRAM_BASE_LO_MASK				0xFFFFF
+#define MC_TZRAM_BASE_HI				0x2198
+#define  TZRAM_BASE_HI_SHIFT				0
+#define  TZRAM_BASE_HI_MASK				3
+#define MC_TZRAM_SIZE					0x219C
+#define  TZRAM_SIZE_RANGE_4KB_SHIFT			27
+
+#define MC_TZRAM_CARVEOUT_CFG				0x2190
+#define  TZRAM_LOCK_CFG_SETTINGS_BIT			(1 << 1)
+#define  TZRAM_ENABLE_TZ_LOCK_BIT			(1 << 0)
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0		0x21A0
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1		0x21A4
+#define  TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT		(1 << 25)
+#define  TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT		(1 << 7)
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2		0x21A8
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3		0x21AC
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4		0x21B0
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5		0x21B4
+
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0	0x21B8
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1	0x21BC
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2	0x21C0
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3	0x21C4
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4	0x21C8
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5	0x21CC
 
 /*******************************************************************************
  * Memory Controller Reset Control registers