Merge "backtrace: Strip PAC field when PAUTH is enabled" into integration
diff --git a/.checkpatch.conf b/.checkpatch.conf
index 2a53961..baa983d 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -43,8 +43,8 @@
# Commit messages might contain a Gerrit Change-Id.
--ignore GERRIT_CHANGE_ID
-# Do not check the format of commit messages, as Github's merge commits do not
-# observe it.
+# Do not check the format of commit messages, as Gerrit's merge commits do not
+# preserve it.
--ignore GIT_COMMIT_ID
# FILE_PATH_CHANGES reports this kind of message:
diff --git a/.editorconfig b/.editorconfig
index 0e7a5c3..928c307 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -1,10 +1,10 @@
#
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-# ARM Trusted Firmware Coding style spec for editors.
+# Trusted Firmware-A Coding style spec for editors.
# References:
# [EC] http://editorconfig.org/
diff --git a/Makefile b/Makefile
index 471cf59..aca57b6 100644
--- a/Makefile
+++ b/Makefile
@@ -256,9 +256,14 @@
-Wvla
ifeq ($(findstring clang,$(notdir $(CC))),)
+# not using clang
WARNINGS += -Wunused-but-set-variable \
-Wmaybe-uninitialized \
- -Wpacked-bitfield-compat
+ -Wpacked-bitfield-compat \
+ -Wshift-overflow=2
+else
+# using clang
+WARNINGS += -Wshift-overflow -Wshift-sign-overflow
endif
ifneq (${E},0)
@@ -510,9 +515,8 @@
# Process platform overrideable behaviour
################################################################################
-# Using the ARM Trusted Firmware BL2 implies that a BL33 image also needs to be
-# supplied for the FIP and Certificate generation tools. This flag can be
-# overridden by the platform.
+# Using BL2 implies that a BL33 image also needs to be supplied for the FIP and
+# Certificate generation tools. This flag can be overridden by the platform.
ifdef BL2_SOURCES
ifdef EL3_PAYLOAD_BASE
# If booting an EL3 payload there is no need for a BL33 image
diff --git a/bl32/optee/optee.mk b/bl32/optee/optee.mk
index 462020f..c8aa7ce 100644
--- a/bl32/optee/optee.mk
+++ b/bl32/optee/optee.mk
@@ -1,10 +1,10 @@
#
-# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-# This makefile only aims at complying with ARM Trusted Firmware build process so
-# that "optee" is a valid ARM Trusted Firmware AArch32 Secure Playload identifier.
+# This makefile only aims at complying with Trusted Firmware-A build process so
+# that "optee" is a valid TF-A AArch32 Secure Playload identifier.
ifneq ($(ARCH),aarch32)
$(error This directory targets AArch32 support)
@@ -12,4 +12,4 @@
$(eval $(call add_define,AARCH32_SP_OPTEE))
-$(info ARM Trusted Firmware built for OP-TEE payload support)
+$(info Trusted Firmware-A built for OP-TEE payload support)
diff --git a/common/tf_log.c b/common/tf_log.c
index 3e174dd..08d3cf4 100644
--- a/common/tf_log.c
+++ b/common/tf_log.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,7 @@
static unsigned int max_log_level = LOG_LEVEL;
/*
- * The common log function which is invoked by ARM Trusted Firmware code.
+ * The common log function which is invoked by TF-A code.
* This function should not be directly invoked and is meant to be
* only used by the log macros defined in debug.h. The function
* expects the first character in the format string to be one of the
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 71f24fd..70aafc0 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -632,8 +632,8 @@
- Introduce External Abort handling on AArch64
External Abort routed to EL3 was reported as an unhandled exception
- and caused a panic. This change enables Arm Trusted Firmware-A to
- handle External Aborts routed to EL3.
+ and caused a panic. This change enables Trusted Firmware-A to handle
+ External Aborts routed to EL3.
- Save value of ACTLR_EL1 implementation-defined register in the CPU
context structure rather than forcing it to 0.
@@ -1626,7 +1626,7 @@
- `Power Domain Topology Design`_
- Applied the new image terminology to the code base and documentation, as
- described on the `TF-A wiki on GitHub`_.
+ described in the `image terminology document`_.
- The build system has been reworked to improve readability and facilitate
adding future extensions.
@@ -2420,7 +2420,7 @@
--------------
-*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
.. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
.. _PSCI Integration Guide: ./getting_started/psci-lib-integration-guide.rst
@@ -2431,7 +2431,7 @@
.. _Firmware Design: ./design/firmware-design.rst
.. _TF-A Reset Design: ./design/reset-design.rst
.. _Power Domain Topology Design: ./design/psci-pd-tree.rst
-.. _TF-A wiki on GitHub: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology
+.. _image terminology document: ./getting_started/image-terminology.rst
.. _Authentication Framework: ./design/auth-framework.rst
.. _OP-TEE Dispatcher: ./spd/optee-dispatcher.rst
.. _tf-issue#501: https://github.com/ARM-software/tf-issues/issues/501
diff --git a/docs/components/firmware-update.rst b/docs/components/firmware-update.rst
index d6bb6ce..30bdc24 100644
--- a/docs/components/firmware-update.rst
+++ b/docs/components/firmware-update.rst
@@ -392,11 +392,11 @@
--------------
-*Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.*
.. _Trusted Board Boot: ../design/trusted-board-boot.rst
.. _Porting Guide: ../getting_started/porting-guide.rst
-.. _here: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology
+.. _here: ../getting_started/image-terminology.rst
.. _Authentication Framework Design: ../design/auth-framework.rst
.. _Universally Unique Identifier: https://tools.ietf.org/rfc/rfc4122.txt
diff --git a/docs/components/sdei.rst b/docs/components/sdei.rst
index 6d0e156..2a777b3 100644
--- a/docs/components/sdei.rst
+++ b/docs/components/sdei.rst
@@ -26,7 +26,7 @@
at EL2 and an event dispatch resulting from the triggering of a bound interrupt.
A commentary is provided below:
-.. image:: ../resources/diagrams/plantuml/sdei_general.svg
+.. uml:: ../resources/diagrams/plantuml/sdei_general.puml
As part of initialisation, the SDEI client binds a Non-secure interrupt [1], and
the SDEI dispatcher returns a platform dynamic event number [2]. The client then
@@ -234,7 +234,7 @@
The following figure depicts a scenario involving explicit dispatch of SDEI
event. A commentary is provided below:
-.. image:: ../resources/diagrams/plantuml/sdei_explicit_dispatch.svg
+.. uml:: ../resources/diagrams/plantuml/sdei_explicit_dispatch.puml
As part of initialisation, the SDEI client registers a handler for a platform
event [1], enables the event [3], and unmasks the current PE [5]. Note that,
diff --git a/docs/components/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst
index ac1172c..de0792d 100644
--- a/docs/components/secure-partition-manager-design.rst
+++ b/docs/components/secure-partition-manager-design.rst
@@ -250,7 +250,7 @@
A SVC causes an exception to be taken to S-EL1. TF-A assumes ownership of S-EL1
and installs a simple exception vector table in S-EL1 that relays a SVC request
from a Secure Partition as a SMC request to the SPM in EL3. Upon servicing the
-SMC request, Arm Trusted Firmware returns control directly to S-EL0 through an
+SMC request, Trusted Firmware-A returns control directly to S-EL0 through an
ERET instruction.
Calling conventions
@@ -806,7 +806,7 @@
--------------
-*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.*
.. _Armv8-A ARM: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
.. _instructions in the EDK2 repository: https://github.com/tianocore/edk2-staging/blob/AArch64StandaloneMm/HowtoBuild.MD
diff --git a/docs/conf.py b/docs/conf.py
index 64f1243..b267de0 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -23,7 +23,7 @@
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
-extensions = ['sphinx.ext.autosectionlabel']
+extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.plantuml']
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
@@ -82,4 +82,8 @@
# -- Options for autosectionlabel --------------------------------------------
# Only generate automatic section labels for document titles
-autosectionlabel_maxdepth = 1
\ No newline at end of file
+autosectionlabel_maxdepth = 1
+
+# -- Options for plantuml ----------------------------------------------------
+
+plantuml_output_format = 'svg_img'
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index 02f8c5f..858996c 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -1720,8 +1720,8 @@
- ``FVP_Base_Cortex-A76x4``
- ``FVP_Base_Cortex-A76AEx4``
- ``FVP_Base_Cortex-A76AEx8``
+- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
- ``FVP_Base_Neoverse-N1x4``
-- ``FVP_Base_Deimos``
- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
diff --git a/docs/index.rst b/docs/index.rst
index 7ac0584..2023ceb 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -176,8 +176,8 @@
- ``FVP_Base_Cortex-A76x4``
- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
+- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
-- ``FVP_Base_Deimos``
- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index b6fd8c8..4cc4302 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -2,9 +2,9 @@
==============================================================
This document summarises the findings of performance measurements of key
-operations in the ARM Trusted Firmware (TF) Power State Coordination Interface
-(PSCI) implementation, using the in-built Performance Measurement Framework
-(PMF) and runtime instrumentation timestamps.
+operations in the Trusted Firmware-A Power State Coordination Interface (PSCI)
+implementation, using the in-built Performance Measurement Framework (PMF) and
+runtime instrumentation timestamps.
Method
------
@@ -284,5 +284,9 @@
We suspect the time for lead CPU 4 is shorter than CPU 5 due to subtle cache
effects, given that these measurements are at the nano-second level.
+--------------
+
+*Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.*
+
.. _Juno R1 platform: https://www.arm.com/files/pdf/Juno_r1_ARM_Dev_datasheet.pdf
.. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
diff --git a/docs/plat/fvp_ve.rst b/docs/plat/fvp_ve.rst
index 5253863..6abf9e5 100644
--- a/docs/plat/fvp_ve.rst
+++ b/docs/plat/fvp_ve.rst
@@ -1,12 +1,11 @@
Arm Versatile Express
=====================
-Versatile Express (VE) family development platform provides an
-ultra fast environment for prototyping arm-v7 System-on-Chip designs.
-VE Fixed Virtual Platforms (FVP) are simulations of Versatile Express boards.
-The platform in arm-trusted-firmware has been verified with Arm Cortex-A5
-and Cortex-A7 VE FVP's. This platform is tested on and only expected to work
-with single core models.
+Versatile Express (VE) family development platform provides an ultra fast
+environment for prototyping Armv7 System-on-Chip designs. VE Fixed Virtual
+Platforms (FVP) are simulations of Versatile Express boards. The platform in
+Trusted Firmware-A has been verified with Arm Cortex-A5 and Cortex-A7 VE FVP's.
+This platform is tested on and only expected to work with single core models.
Boot Sequence
-------------
@@ -20,7 +19,7 @@
~~~~~~~~~~~~~~
- `U-boot <https://git.linaro.org/landing-teams/working/arm/u-boot.git>`__
-- `arm-trusted-firmware <https://github.com/ARM-software/arm-trusted-firmware>`__
+- `Trusted Firmware-A <https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git>`__
Build Procedure
~~~~~~~~~~~~~~~
@@ -71,7 +70,7 @@
~~~~~~~~~~~~~
The following model parameters should be used to boot Linux using the build of
-arm-trusted-firmware-a made using the above make commands:
+Trusted Firmware-A made using the above make commands:
.. code:: shell
diff --git a/docs/process/coding-guidelines.rst b/docs/process/coding-guidelines.rst
index 093d66b..a53da77 100644
--- a/docs/process/coding-guidelines.rst
+++ b/docs/process/coding-guidelines.rst
@@ -272,15 +272,15 @@
+------------------------+-----------+--------------------------------------+
| libc function | Status | Comments |
+========================+===========+======================================+
-| ``strcpy, wcscpy`` | Banned | use strlcpy instead |
+| ``strcpy, wcscpy``, | Banned | use strlcpy instead |
| ``strncpy`` | | |
+------------------------+-----------+--------------------------------------+
-| ``strcat, wcscat`` | Banned | use strlcat instead |
+| ``strcat, wcscat``, | Banned | use strlcat instead |
| ``strncat`` | | |
-+----------------------- +-----------+--------------------------------------+
++------------------------+-----------+--------------------------------------+
| ``sprintf, vsprintf`` | Banned | use snprintf, vsnprintf |
| | | instead |
-+---------------------- -+-----------+--------------------------------------+
++------------------------+-----------+--------------------------------------+
| ``snprintf`` | Caution | ensure result fits in buffer |
| | | i.e : snprintf(buf,size...) < size |
+------------------------+-----------+--------------------------------------+
diff --git a/docs/process/platform-compatibility-policy.rst b/docs/process/platform-compatibility-policy.rst
index 1c80eb5..a11ba38 100644
--- a/docs/process/platform-compatibility-policy.rst
+++ b/docs/process/platform-compatibility-policy.rst
@@ -20,18 +20,19 @@
the contributor of the change is expected to make good effort to migrate the
upstream platforms to the new interface.
-The `Release information`_ documents the deprecated interfaces and the intended
-release after which it will be removed. When an interface is deprecated, the
-page must be updated to indicate the release after which the interface will be
-removed. This must be at least 1 full release cycle in future. For non-trivial
-interface changes, a `tf-issue`_ should be posted to notify platforms that they
-should migrate away from the deprecated interfaces. Platforms are expected to
-migrate before the removal of the deprecated interface.
+The deprecated interfaces are listed inside `Release information`_ as well as
+the release after which each one will be removed. When an interface is
+deprecated, the page must be updated to indicate the release after which the
+interface will be removed. This must be at least 1 full release cycle in future.
+For non-trivial interface changes, an email should be sent out to the `TF-A
+public mailing list`_ to notify platforms that they should migrate away from the
+deprecated interfaces. Platforms are expected to migrate before the removal of
+the deprecated interface.
--------------
-*Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.*
.. _Porting Guide: ../getting_started/porting-guide.rst
-.. _Release information: https://github.com/ARM-software/arm-trusted-firmware/wiki/TF-A-Release-information#removal-of-deprecated-interfaces
-.. _tf-issue: https://github.com/ARM-software/tf-issues/issues
+.. _Release information: ./release-information.rst#removal-of-deprecated-interfaces
+.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a
diff --git a/docs/requirements.txt b/docs/requirements.txt
index 8f95774..358ed0e 100644
--- a/docs/requirements.txt
+++ b/docs/requirements.txt
@@ -1,2 +1,3 @@
sphinx>=2.0.0
-sphinx-rtd-theme>=0.4.3
\ No newline at end of file
+sphinx-rtd-theme>=0.4.3
+sphinxcontrib-plantuml>=0.15
diff --git a/docs/resources/diagrams/Makefile b/docs/resources/diagrams/Makefile
index de7d8f3..7f583b5 100644
--- a/docs/resources/diagrams/Makefile
+++ b/docs/resources/diagrams/Makefile
@@ -1,10 +1,10 @@
#
-# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
#
-# This Makefile generates the image files used in the ARM Trusted Firmware
+# This Makefile generates the image files used in the Trusted Firmware-A
# document from the dia file.
#
# The PNG files in the present directory have been generated using Dia version
diff --git a/docs/resources/diagrams/plantuml/plantuml_to_svg.sh b/docs/resources/diagrams/plantuml/plantuml_to_svg.sh
deleted file mode 100644
index 0bf8588..0000000
--- a/docs/resources/diagrams/plantuml/plantuml_to_svg.sh
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/bash
-
-# Convert all PlantUML files in this directory to SVG files. The plantuml_jar
-# environment variable must be set to the path to PlantUML JAR file.
-
-if [ -z "$plantuml_jar" ]; then
- echo "Usage: plantuml_jar=/path/to/plantuml.jar $0 *.puml" >&2
- exit 1
-fi
-
-java -jar "$plantuml_jar" -nometadata -tsvg "$@"
-
-# vim:set noet sts=8 tw=80:
diff --git a/docs/resources/diagrams/plantuml/sdei_explicit_dispatch.svg b/docs/resources/diagrams/plantuml/sdei_explicit_dispatch.svg
deleted file mode 100644
index e12cae2..0000000
--- a/docs/resources/diagrams/plantuml/sdei_explicit_dispatch.svg
+++ /dev/null
@@ -1 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" contentScriptType="application/ecmascript" contentStyleType="text/css" height="783px" preserveAspectRatio="none" style="width:745px;height:783px;" version="1.1" viewBox="0 0 745 783" width="745px" zoomAndPan="magnify"><defs><filter height="300%" id="f18zq03ani7xpz" width="300%" x="-1" y="-1"><feGaussianBlur result="blurOut" stdDeviation="2.0"/><feColorMatrix in="blurOut" result="blurOut2" type="matrix" values="0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .4 0"/><feOffset dx="4.0" dy="4.0" in="blurOut2" result="blurOut3"/><feBlend in="SourceGraphic" in2="blurOut3" mode="normal"/></filter></defs><g><rect fill="#FFFFFF" filter="url(#f18zq03ani7xpz)" height="174.7969" style="stroke: #FFFFFF; stroke-width: 1.0;" width="10" x="56.5" y="48.2969"/><line style="stroke: #A80036; stroke-width: 1.0;" x1="56.5" x2="56.5" y1="48.2969" y2="223.0938"/><line style="stroke: #A80036; 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stroke-width: 1.0;"/><path d="M441,298.0313 L441,308.0313 L451,308.0313 L441,298.0313 " fill="#FBFB77" style="stroke: #A80036; stroke-width: 1.0;"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacingAndGlyphs" textLength="124" x="312" y="315.0981">Critical event triage</text><polygon fill="#A80036" points="629,349.2969,639,353.2969,629,357.2969,633,353.2969" style="stroke: #A80036; stroke-width: 1.0;"/><line style="stroke: #A80036; stroke-width: 1.0;" x1="380.5" x2="635" y1="353.2969" y2="353.2969"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacingAndGlyphs" textLength="21" x="387.5" y="348.231">[8]</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacingAndGlyphs" textLength="118" x="412.5" y="348.231">dispatch to handle</text><path d="M563,366.2969 L563,391.2969 L725,391.2969 L725,376.2969 L715,366.2969 L563,366.2969 " fill="#FBFB77" filter="url(#f18zq03ani7xpz)" style="stroke: #A80036; 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stroke-width: 1.0;"/><path d="M101,502.8281 L101,512.8281 L111,512.8281 L101,502.8281 " fill="#FBFB77" style="stroke: #A80036; stroke-width: 1.0;"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacingAndGlyphs" textLength="82" x="14" y="519.895">SDEI handler</text><polygon fill="#A80036" points="420,554.0938,430,558.0938,420,562.0938,424,558.0938" style="stroke: #A80036; stroke-width: 1.0;"/><line style="stroke: #A80036; stroke-width: 1.0;" x1="66.5" x2="426" y1="558.0938" y2="558.0938"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacingAndGlyphs" textLength="30" x="73.5" y="553.0278">[11]</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacingAndGlyphs" textLength="184" x="107.5" y="553.0278">SDEI_EVENT_COMPLETE()</text><path d="M347,571.0938 L347,596.0938 L522,596.0938 L522,581.0938 L512,571.0938 L347,571.0938 " fill="#FBFB77" filter="url(#f18zq03ani7xpz)" style="stroke: #A80036; stroke-width: 1.0;"/><path d="M512,571.0938 L512,581.0938 L522,581.0938 L512,571.0938 " fill="#FBFB77" style="stroke: #A80036; stroke-width: 1.0;"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacingAndGlyphs" textLength="154" x="353" y="588.1606">Complete SDEI dispatch</text><polygon fill="#A80036" points="629,622.3594,639,626.3594,629,630.3594,633,626.3594" style="stroke: #A80036; stroke-width: 1.0;"/><line style="stroke: #A80036; stroke-width: 1.0; stroke-dasharray: 2.0,2.0;" x1="437" x2="635" y1="626.3594" y2="626.3594"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacingAndGlyphs" textLength="30" x="444" y="621.2935">[12]</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacingAndGlyphs" textLength="39" x="478" y="621.2935">return</text><polygon fill="#A80036" points="391.5,651.4922,381.5,655.4922,391.5,659.4922,387.5,655.4922" style="stroke: #A80036; stroke-width: 1.0;"/><line style="stroke: #A80036; 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+++ /dev/null
@@ -1 +0,0 @@
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\ No newline at end of file
diff --git a/drivers/console/aarch32/skeleton_console.S b/drivers/console/aarch32/skeleton_console.S
index da4cecd..45ad139 100644
--- a/drivers/console/aarch32/skeleton_console.S
+++ b/drivers/console/aarch32/skeleton_console.S
@@ -1,108 +1,176 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
+#include <console_macros.S>
/*
- * This file contains a skeleton console implementation that can
- * be used as basis for a real console implementation by platforms
- * that do not contain PL011 hardware.
+ * This file contains a skeleton console driver that can be used as a
+ * basis for a real console driver. Console drivers in Trusted Firmware
+ * can be instantiated multiple times. Each instance is described by a
+ * separate console_t structure which must be registered with the common
+ * console framework via console_register(). Console drivers should
+ * define a console_xxx_register() function that initializes a new
+ * console_t structure passed in from the caller and registers it after
+ * initializing the console hardware. Drivers may define their own
+ * structures extending console_t to store private driver information.
+ * Console drivers *MUST* ensure that the console callbacks they
+ * implement only change registers allowed in the clobber lists defined
+ * in this file. (Note that in addition to the explicit clobber lists,
+ * any function may always clobber the intra-procedure-call register
+ * r12, but may never depend on it retaining its value across any
+ * function call.)
*/
- .globl console_core_init
- .globl console_core_putc
- .globl console_core_getc
- .globl console_core_flush
+ .globl console_xxx_register
+ .globl console_xxx_putc
+ .globl console_xxx_getc
+ .globl console_xxx_flush
/* -----------------------------------------------
- * int console_core_init(uintptr_t base_addr,
- * unsigned int uart_clk, unsigned int baud_rate)
- * Function to initialize the console without a
- * C Runtime to print debug information. This
- * function will be accessed by console_init and
- * crash reporting.
- * In: r0 - console base address
- * r1 - Uart clock in Hz
- * r2 - Baud rate
- * Out: return 1 on success else 0 on error
- * Clobber list : r1, r2
+ * int console_xxx_register(console_xxx_t *console,
+ * ...additional parameters as desired...)
+ * Function to initialize and register the console.
+ * The caller needs to pass an empty console_xxx_t
+ * structure in which *MUST* be allocated in
+ * persistent memory (e.g. a global or static local
+ * variable, *NOT* on the stack).
+ * In : r0 - pointer to empty console_t structure
+ * r1 through r7: additional parameters as desired
+ * Out: r0 - 1 on success, 0 on error
+ * Clobber list : r0 - r7
* -----------------------------------------------
*/
-func console_core_init
- /* Check the input base address */
- cmp r0, #0
- beq core_init_fail
- /* Check baud rate and uart clock for sanity */
- cmp r1, #0
- beq core_init_fail
- cmp r2, #0
- beq core_init_fail
- /* Insert implementation here */
- mov r0, #1
- bx lr
-core_init_fail:
+func console_xxx_register
+ /*
+ * Store parameters (e.g. hardware base address) in driver-specific
+ * console_xxx_t structure field if they will need to be retrieved
+ * by later console callback (e.g. putc).
+ * Example:
+ */
+ str r1, [r0, #CONSOLE_T_XXX_BASE]
+ str r2, [r0, #CONSOLE_T_XXX_SOME_OTHER_VALUE]
+
+ /*
+ * Initialize console hardware, using r1 - r7 parameters as needed.
+ * Keep console_t pointer in r0 for later.
+ */
+
+ /*
+ * Macro to finish up registration and return (needs valid r0 + lr).
+ * If any of the argument is unspecified, then the corresponding
+ * entry in console_t is set to 0.
+ */
+ finish_console_register xxx putc=1, getc=1, flush=1
+
+ /* Jump here if hardware init fails or parameters are invalid. */
+register_fail:
mov r0, #0
bx lr
-endfunc console_core_init
+endfunc console_xxx_register
/* --------------------------------------------------------
- * int console_core_putc(int c, uintptr_t base_addr)
+ * int console_xxx_putc(int c, console_xxx_t *console)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
* In : r0 - character to be printed
- * r1 - console base address
- * Out : return -1 on error else return character.
- * Clobber list : r2
+ * r1 - pointer to console_t struct
+ * Out: r0 - printed character on success, < 0 on error.
+ * Clobber list : r0, r1, r2
* --------------------------------------------------------
*/
+func console_xxx_putc
+ /*
+ * Retrieve values we need (e.g. hardware base address) from
+ * console_xxx_t structure pointed to by r1.
+ * Example:
+ */
-func console_core_putc
- /* Check the input parameter */
- cmp r1, #0
- beq putc_error
- /* Insert implementation here */
+ ldr r1, [r1, #CONSOLE_T_XXX_BASE]
+
+ /*
+ * Write r0 to hardware.
+ */
+
bx lr
+
+ /* Jump here if output fails for any reason. */
putc_error:
mov r0, #-1
bx lr
-endfunc console_core_putc
+endfunc console_xxx_putc
/* ---------------------------------------------
- * int console_core_getc(uintptr_t base_addr)
+ * int console_xxx_getc(console_xxx_t *console)
* Function to get a character from the console.
- * It returns the character grabbed on success
- * or -1 on error.
- * In : r0 - console base address
+ * Even though console_getc() is blocking, this
+ * callback has to be non-blocking and always
+ * return immediately to allow polling multiple
+ * drivers concurrently.
+ * Returns the character grabbed on success,
+ * ERROR_NO_PENDING_CHAR if no character was
+ * available at this time, or any value
+ * between -2 and -127 if there was an error.
+ * In : r0 - pointer to console_t struct
+ * Out: r0 - character on success,
+ * ERROR_NO_PENDING_CHAR if no char,
+ * < -1 on error
* Clobber list : r0, r1
* ---------------------------------------------
*/
-func console_core_getc
- cmp r0, #0
- beq getc_error
- /* Insert implementation here */
+func console_xxx_getc
+ /*
+ * Retrieve values we need (e.g. hardware base address) from
+ * console_xxx_t structure pointed to by r0.
+ * Example:
+ */
+ ldr r1, [r0, #CONSOLE_T_XXX_BASE]
+
+ /*
+ * Try to read character into r0 from hardware.
+ */
+
bx lr
+
+ /* Jump here if there is no character available at this time. */
+getc_no_char:
+ mov r0, #ERROR_NO_PENDING_CHAR
+ bx lr
+
+ /* Jump here if there was any hardware error. */
getc_error:
- mov r0, #-1
+ mov r0, #-2 /* may pick error codes between -2 and -127 */
bx lr
-endfunc console_core_getc
+endfunc console_xxx_getc
/* ---------------------------------------------
- * int console_core_flush(uintptr_t base_addr)
+ * int console_xxx_flush(console_xxx_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
- * In : r0 - console base address
- * Out : return -1 on error else return 0.
- * Clobber list : r0, r1
+ * In : r0 - pointer to console_xxx_t struct
+ * Out: r0 - 0 on success, < 0 on error
+ * Clobber list : r0, r1, r2, r3, r4, r5
* ---------------------------------------------
*/
+func console_xxx_flush
+ /*
+ * Retrieve values we need (e.g. hardware base address) from
+ * console_xxx_t structure pointed to by r0.
+ * Example:
+ */
+ ldr r1, [r0, #CONSOLE_T_XXX_BASE]
+
+ /*
+ * Flush all remaining output from hardware FIFOs. Do not return until
+ * all data has been flushed or there was an unrecoverable error.
+ */
-func console_core_flush
- cmp r0, #0
- beq flush_error
- /* Insert implementation here */
+
mov r0, #0
bx lr
+
+ /* Jump here if an unrecoverable error has been encountered. */
flush_error:
mov r0, #-1
bx lr
-endfunc console_core_flush
+endfunc console_xxx_flush
diff --git a/drivers/console/aarch64/skeleton_console.S b/drivers/console/aarch64/skeleton_console.S
index c695dde..957ed83 100644
--- a/drivers/console/aarch64/skeleton_console.S
+++ b/drivers/console/aarch64/skeleton_console.S
@@ -7,7 +7,7 @@
#include <console_macros.S>
/*
- * This file contains a skeleton console driver that can be used as
+ * This file contains a skeleton console driver that can be used as a
* basis for a real console driver. Console drivers in Trusted Firmware
* can be instantiated multiple times. Each instance is described by a
* separate console_t structure which must be registered with the common
@@ -16,7 +16,7 @@
* console_t structure passed in from the caller and registers it after
* initializing the console hardware. Drivers may define their own
* structures extending console_t to store private driver information.
- * Console drivers *MUST* take care that the console callbacks they
+ * Console drivers *MUST* ensure that the console callbacks they
* implement only change registers allowed in the clobber lists defined
* in this file. (Note that in addition to the explicit clobber lists,
* any function may always clobber the intra-procedure-call registers
diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c
index 3a9859c..06fe88e 100644
--- a/drivers/marvell/mci.c
+++ b/drivers/marvell/mci.c
@@ -245,7 +245,7 @@
MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET)
#define MCI_PHY_CTRL_PIDI_MODE_OFFSET 31
#define MCI_PHY_CTRL_PIDI_MODE \
- (1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
+ (1U << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
/* Number of times to wait for the MCI link ready after MCI configurations
* Normally takes 34-35 successive reads
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index d7d7373..b4b4e0c 100644
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c
@@ -56,11 +56,11 @@
(0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16
#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \
- (0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
+ (0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
#define MVEBU_SAMPLE_AT_RESET_REG (0x440600)
#define SAR_PCIE1_CLK_CFG_OFFSET 31
-#define SAR_PCIE1_CLK_CFG_MASK (0x1 << SAR_PCIE1_CLK_CFG_OFFSET)
+#define SAR_PCIE1_CLK_CFG_MASK (0x1u << SAR_PCIE1_CLK_CFG_OFFSET)
#define SAR_PCIE0_CLK_CFG_OFFSET 30
#define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
#define SAR_I2C_INIT_EN_OFFSET 24
diff --git a/drivers/meson/gxl/crypto/sha_dma.c b/drivers/meson/gxl/crypto/sha_dma.c
index 565099c..a969dea 100644
--- a/drivers/meson/gxl/crypto/sha_dma.c
+++ b/drivers/meson/gxl/crypto/sha_dma.c
@@ -104,8 +104,8 @@
#define ASD_DESC_ERR_SET(d, v) \
(ASD_DESC_SET((d)->cfg, v, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF))
-#define ASD_DESC_OWNER_OFF 31
-#define ASD_DESC_OWNER_MASK 0x1
+#define ASD_DESC_OWNER_OFF 31u
+#define ASD_DESC_OWNER_MASK 0x1u
#define ASD_DESC_OWNER(d) \
(ASD_DESC_GET((d)->cfg, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF))
#define ASD_DESC_OWNER_SET(d, v) \
@@ -126,7 +126,7 @@
assert((uintptr_t)&desc == (uintptr_t)&desc);
ASD_DESC_LEN_SET(&desc, len);
- ASD_DESC_OWNER_SET(&desc, 1);
+ ASD_DESC_OWNER_SET(&desc, 1u);
ASD_DESC_ENCONLY_SET(&desc, 1);
ASD_DESC_EOD_SET(&desc, 1);
if (ctx->started == 0) {
diff --git a/drivers/renesas/rcar/auth/auth_mod.c b/drivers/renesas/rcar/auth/auth_mod.c
index f7d8ec0..ece3462 100644
--- a/drivers/renesas/rcar/auth/auth_mod.c
+++ b/drivers/renesas/rcar/auth/auth_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -25,7 +25,7 @@
#define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U)
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
-#define MFISSOFTMDR (0xE6260600U)
+#define MFISOFTMDR (0xE6260600U)
#define MODEMR_MD5_MASK (0x00000020U)
#define MODEMR_MD5_SHIFT (5U)
#define SOFTMD_BOOTMODE_MASK (0x00000001U)
@@ -139,7 +139,7 @@
void auth_mod_init(void)
{
#if RCAR_SECURE_BOOT
- uint32_t soft_md = mmio_read_32(MFISSOFTMDR) & SOFTMD_BOOTMODE_MASK;
+ uint32_t soft_md = mmio_read_32(MFISOFTMDR) & SOFTMD_BOOTMODE_MASK;
uint32_t md = mmio_read_32(RST_MODEMR) & MODEMR_MD5_MASK;
uint32_t lcs, ret;
diff --git a/drivers/renesas/rcar/cpld/ulcb_cpld.c b/drivers/renesas/rcar/cpld/ulcb_cpld.c
index 4830853..5ffb2e1 100644
--- a/drivers/renesas/rcar/cpld/ulcb_cpld.c
+++ b/drivers/renesas/rcar/cpld/ulcb_cpld.c
@@ -68,7 +68,7 @@
for (i = 0; i < 32; i++) {
/* MSB first */
- gpio_set_value(GPIO_OUTDT6, MOSI, data & (1 << 31));
+ gpio_set_value(GPIO_OUTDT6, MOSI, data & (1U << 31));
gpio_set_value(GPIO_OUTDT6, SCLK, 1);
data <<= 1;
gpio_set_value(GPIO_OUTDT6, SCLK, 0);
diff --git a/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
index 7e9bde9..aaa3b43 100644
--- a/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
+++ b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
@@ -610,7 +610,7 @@
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, 0xC00FFFFFU);
- pfc_reg_write(PFC_POCCTRL1, 0XFFFFFFFEU);
+ pfc_reg_write(PFC_POCCTRL2, 0XFFFFFFFEU);
pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
/* initialize LSI pin pull-up/down control */
diff --git a/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
index 2946cba..bd0048e 100644
--- a/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
+++ b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
@@ -122,7 +122,7 @@
#define GPSR5_SCK2_A BIT(7)
#define GPSR5_TX1 BIT(6)
#define GPSR5_RX1 BIT(5)
-#define GPSR5_RTS0_TANS_A BIT(4)
+#define GPSR5_RTS0_A BIT(4)
#define GPSR5_CTS0_A BIT(3)
#define GPSR5_TX0_A BIT(2)
#define GPSR5_RX0_A BIT(1)
@@ -155,7 +155,7 @@
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
-#define IOCTRL30_MASK (0x0007F000U)
+#define POCCTRL0_MASK (0x0007F000U)
#define POC_SD3_DS_33V BIT(29)
#define POC_SD3_DAT7_33V BIT(28)
#define POC_SD3_DAT6_33V BIT(27)
@@ -180,7 +180,7 @@
#define POC_SD0_CMD_33V BIT(1)
#define POC_SD0_CLK_33V BIT(0)
-#define IOCTRL32_MASK (0xFFFFFFFEU)
+#define POCCTRL2_MASK (0xFFFFFFFEU)
#define POC2_VREF_33V BIT(0)
#define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U)
@@ -561,7 +561,7 @@
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2_A
- | GPSR5_RTS0_TANS_A
+ | GPSR5_RTS0_A
| GPSR5_CTS0_A);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
| GPSR6_SSI_SDATA6
@@ -581,7 +581,7 @@
/* initialize POC control */
reg = mmio_read_32(PFC_POCCTRL0);
- reg = ((reg & IOCTRL30_MASK) | POC_SD1_DAT3_33V
+ reg = ((reg & POCCTRL0_MASK) | POC_SD1_DAT3_33V
| POC_SD1_DAT2_33V
| POC_SD1_DAT1_33V
| POC_SD1_DAT0_33V
@@ -594,9 +594,9 @@
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
pfc_reg_write(PFC_POCCTRL0, reg);
- reg = mmio_read_32(PFC_POCCTRL1);
- reg = (reg & IOCTRL32_MASK);
- pfc_reg_write(PFC_POCCTRL1, reg);
+ reg = mmio_read_32(PFC_POCCTRL2);
+ reg = (reg & POCCTRL2_MASK);
+ pfc_reg_write(PFC_POCCTRL2, reg);
/* initialize LSI pin pull-up/down control */
pfc_reg_write(PFC_PUD0, 0xFDF80000U);
diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
index 7287c83..effdc76 100644
--- a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
@@ -119,11 +119,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
-#define GPSR5_RTS1_TANS BIT(8)
+#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
-#define GPSR5_RTS0_TANS BIT(4)
+#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
@@ -160,8 +160,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
-#define GPSR7_HDMI1_CEC BIT(3)
-#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
@@ -323,8 +321,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
@@ -673,7 +671,6 @@
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
- | IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
@@ -829,11 +826,11 @@
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
- | GPSR5_RTS1_TANS
+ | GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
- | GPSR5_RTS0_TANS
+ | GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
@@ -856,9 +853,7 @@
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
- pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
- | GPSR7_HDMI0_CEC
- | GPSR7_AVS2
+ pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
@@ -996,8 +991,8 @@
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
- | DRVCTRL11_HDMI0_CEC(7)
- | DRVCTRL11_HDMI1_CEC(7)
+ | DRVCTRL11_GP7_02(7)
+ | DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
@@ -1153,6 +1148,7 @@
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@@ -1162,6 +1158,7 @@
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@@ -1182,4 +1179,5 @@
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}
diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
index 8bba3c1..a54b14b 100644
--- a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
@@ -121,11 +121,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
-#define GPSR5_RTS1_TANS BIT(8)
+#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
-#define GPSR5_RTS0_TANS BIT(4)
+#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
@@ -162,8 +162,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
-#define GPSR7_HDMI1_CEC BIT(3)
-#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
@@ -325,8 +323,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
@@ -697,7 +695,6 @@
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
- | IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
@@ -862,11 +859,11 @@
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
- | GPSR5_RTS1_TANS
+ | GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
- | GPSR5_RTS0_TANS
+ | GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
@@ -889,9 +886,7 @@
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
- pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
- | GPSR7_HDMI0_CEC
- | GPSR7_AVS2
+ pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
@@ -1029,8 +1024,8 @@
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
- | DRVCTRL11_HDMI0_CEC(7)
- | DRVCTRL11_HDMI1_CEC(7)
+ | DRVCTRL11_GP7_02(7)
+ | DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
@@ -1186,6 +1181,7 @@
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@@ -1195,6 +1191,7 @@
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@@ -1215,4 +1212,5 @@
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}
diff --git a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
index 380899d..0aa3bff 100644
--- a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+++ b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -124,11 +124,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
-#define GPSR5_RTS1_TANS BIT(8)
+#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
-#define GPSR5_RTS0_TANS BIT(4)
+#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
@@ -165,8 +165,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
-#define GPSR7_HDMI1_CEC BIT(3)
-#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
@@ -328,8 +326,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
@@ -792,7 +790,6 @@
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
- | IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
@@ -957,11 +954,11 @@
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
- | GPSR5_RTS1_TANS
+ | GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
- | GPSR5_RTS0_TANS
+ | GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
@@ -984,9 +981,7 @@
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
- pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
- | GPSR7_HDMI0_CEC
- | GPSR7_AVS2
+ pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
@@ -1124,8 +1119,8 @@
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
- | DRVCTRL11_HDMI0_CEC(7)
- | DRVCTRL11_HDMI1_CEC(7)
+ | DRVCTRL11_GP7_02(7)
+ | DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
@@ -1281,6 +1276,7 @@
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@@ -1290,6 +1286,7 @@
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@@ -1310,4 +1307,5 @@
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}
diff --git a/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
index 3fac375..5014556 100644
--- a/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+++ b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
@@ -123,11 +123,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
-#define GPSR5_RTS1_TANS BIT(8)
+#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
-#define GPSR5_RTS0_TANS BIT(4)
+#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
@@ -164,8 +164,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
-#define GPSR7_HDMI1_CEC BIT(3)
-#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
@@ -327,8 +325,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
-#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
@@ -699,7 +697,6 @@
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
- | IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
@@ -864,11 +861,11 @@
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
- | GPSR5_RTS1_TANS
+ | GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
- | GPSR5_RTS0_TANS
+ | GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
@@ -891,9 +888,7 @@
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
- pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
- | GPSR7_HDMI0_CEC
- | GPSR7_AVS2
+ pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
@@ -1031,8 +1026,8 @@
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
- | DRVCTRL11_HDMI0_CEC(7)
- | DRVCTRL11_HDMI1_CEC(7)
+ | DRVCTRL11_GP7_02(7)
+ | DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
@@ -1188,6 +1183,7 @@
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@@ -1197,6 +1193,7 @@
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@@ -1217,4 +1214,5 @@
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}
diff --git a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
index 51d6f42..6063758 100644
--- a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+++ b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
@@ -709,7 +709,7 @@
| IOCTRL31_POC_VI0_DATA7
| IOCTRL31_POC_VI0_DATA6);
- pfc_reg_write(PFC_POCCTRL1, 0x00000000);
+ pfc_reg_write(PFC_POCCTRL2, 0x00000000);
pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);
diff --git a/drivers/renesas/rcar/pfc/pfc_regs.h b/drivers/renesas/rcar/pfc/pfc_regs.h
index b0b4e6f..e7dd543 100644
--- a/drivers/renesas/rcar/pfc/pfc_regs.h
+++ b/drivers/renesas/rcar/pfc/pfc_regs.h
@@ -206,7 +206,7 @@
#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U)
#define PFC_POCCTRL0 (PFC_BASE + 0x0380U)
#define PFC_IOCTRL31 (PFC_BASE + 0x0384U)
-#define PFC_POCCTRL1 (PFC_BASE + 0x0388U)
+#define PFC_POCCTRL2 (PFC_BASE + 0x0388U)
#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U)
#define PFC_IOCTRL (PFC_BASE + 0x03E0U)
#define PFC_TSREG (PFC_BASE + 0x03E4U)
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
index d97e593..f4c9d3a 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -763,10 +763,10 @@
reg = mmio_read_32(RCAR_PRR);
- if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
+ if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
return RCAR_CLUSTER_CA57;
- if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+ if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
return RCAR_CLUSTER_CA53;
return RCAR_CLUSTER_A53A57;
@@ -810,7 +810,7 @@
count_ca57:
if (IS_A53A57(c) || IS_CA57(c)) {
- if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+ if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
goto done;
for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
diff --git a/drivers/renesas/rcar/pwrc/pwrc.h b/drivers/renesas/rcar/pwrc/pwrc.h
index cfb35ff..e67c6ef 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.h
+++ b/drivers/renesas/rcar/pwrc/pwrc.h
@@ -15,7 +15,7 @@
#define PWKUPR_WEN (1ull << 31)
-#define PSYSR_AFF_L2 (1 << 31)
+#define PSYSR_AFF_L2 (1U << 31)
#define PSYSR_AFF_L1 (1 << 30)
#define PSYSR_AFF_L0 (1 << 29)
#define PSYSR_WEN (1 << 28)
diff --git a/drivers/renesas/rcar/rpc/rpc_driver.c b/drivers/renesas/rcar/rpc/rpc_driver.c
index bea2752..5c11b62 100644
--- a/drivers/renesas/rcar/rpc/rpc_driver.c
+++ b/drivers/renesas/rcar/rpc/rpc_driver.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,11 +11,15 @@
#include <lib/mmio.h>
#include "cpg_registers.h"
-#include "rpc_registers.h"
+#include "rcar_def.h"
#include "rcar_private.h"
+#include "rpc_registers.h"
#define MSTPSR9_RPC_BIT (0x00020000U)
#define RPC_CMNCR_MD_BIT (0x80000000U)
+#define RPC_PHYCNT_CAL BIT(31)
+#define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL)
+#define RPC_PHYCNT_STRTIM (0x7 << 15UL)
static void rpc_enable(void)
{
@@ -25,8 +29,25 @@
static void rpc_setup(void)
{
+ uint32_t product, cut, reg, phy_strtim;
+
if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
+
+ product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+ cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+
+ if ((product == RCAR_PRODUCT_M3) && (cut < RCAR_CUT_VER30))
+ phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
+ else
+ phy_strtim = RPC_PHYCNT_STRTIM;
+
+ reg = mmio_read_32(RPC_PHYCNT);
+ reg &= ~RPC_PHYCNT_STRTIM;
+ reg |= phy_strtim;
+ mmio_write_32(RPC_PHYCNT, reg);
+ reg |= RPC_PHYCNT_CAL;
+ mmio_write_32(RPC_PHYCNT, reg);
}
void rcar_rpc_init(void)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
new file mode 100644
index 0000000..397bde0
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOOT_INIT_DRAM_REGDEF_H_
+#define BOOT_INIT_DRAM_REGDEF_H_
+
+/* DBSC registers */
+#define DBSC_DBSYSCONF0 0xE6790000U
+#define DBSC_DBSYSCONF1 0xE6790004U
+#define DBSC_DBPHYCONF0 0xE6790010U
+#define DBSC_DBKIND 0xE6790020U
+#define DBSC_DBMEMCONF00 0xE6790030U
+#define DBSC_DBMEMCONF01 0xE6790034U
+#define DBSC_DBMEMCONF02 0xE6790038U
+#define DBSC_DBMEMCONF03 0xE679003CU
+#define DBSC_DBMEMCONF10 0xE6790040U
+#define DBSC_DBMEMCONF11 0xE6790044U
+#define DBSC_DBMEMCONF12 0xE6790048U
+#define DBSC_DBMEMCONF13 0xE679004CU
+#define DBSC_DBMEMCONF20 0xE6790050U
+#define DBSC_DBMEMCONF21 0xE6790054U
+#define DBSC_DBMEMCONF22 0xE6790058U
+#define DBSC_DBMEMCONF23 0xE679005CU
+#define DBSC_DBMEMCONF30 0xE6790060U
+#define DBSC_DBMEMCONF31 0xE6790064U
+#define DBSC_DBMEMCONF32 0xE6790068U
+#define DBSC_DBMEMCONF33 0xE679006CU
+#define DBSC_DBSYSCNT0 0xE6790100U
+#define DBSC_DBSVCR1 0xE6790104U
+#define DBSC_DBSTATE0 0xE6790108U
+#define DBSC_DBSTATE1 0xE679010CU
+#define DBSC_DBINTEN 0xE6790180U
+#define DBSC_DBINTSTAT0 0xE6790184U
+#define DBSC_DBACEN 0xE6790200U
+#define DBSC_DBRFEN 0xE6790204U
+#define DBSC_DBCMD 0xE6790208U
+#define DBSC_DBWAIT 0xE6790210U
+#define DBSC_DBSYSCTRL0 0xE6790280U
+#define DBSC_DBTR0 0xE6790300U
+#define DBSC_DBTR1 0xE6790304U
+#define DBSC_DBTR2 0xE6790308U
+#define DBSC_DBTR3 0xE679030CU
+#define DBSC_DBTR4 0xE6790310U
+#define DBSC_DBTR5 0xE6790314U
+#define DBSC_DBTR6 0xE6790318U
+#define DBSC_DBTR7 0xE679031CU
+#define DBSC_DBTR8 0xE6790320U
+#define DBSC_DBTR9 0xE6790324U
+#define DBSC_DBTR10 0xE6790328U
+#define DBSC_DBTR11 0xE679032CU
+#define DBSC_DBTR12 0xE6790330U
+#define DBSC_DBTR13 0xE6790334U
+#define DBSC_DBTR14 0xE6790338U
+#define DBSC_DBTR15 0xE679033CU
+#define DBSC_DBTR16 0xE6790340U
+#define DBSC_DBTR17 0xE6790344U
+#define DBSC_DBTR18 0xE6790348U
+#define DBSC_DBTR19 0xE679034CU
+#define DBSC_DBTR20 0xE6790350U
+#define DBSC_DBTR21 0xE6790354U
+#define DBSC_DBTR22 0xE6790358U
+#define DBSC_DBTR23 0xE679035CU
+#define DBSC_DBTR24 0xE6790360U
+#define DBSC_DBTR25 0xE6790364U
+#define DBSC_DBBL 0xE6790400U
+#define DBSC_DBRFCNF1 0xE6790414U
+#define DBSC_DBRFCNF2 0xE6790418U
+#define DBSC_DBTSPCNF 0xE6790420U
+#define DBSC_DBCALCNF 0xE6790424U
+#define DBSC_DBRNK2 0xE6790438U
+#define DBSC_DBRNK3 0xE679043CU
+#define DBSC_DBRNK4 0xE6790440U
+#define DBSC_DBRNK5 0xE6790444U
+#define DBSC_DBPDNCNF 0xE6790450U
+#define DBSC_DBODT0 0xE6790460U
+#define DBSC_DBODT1 0xE6790464U
+#define DBSC_DBODT2 0xE6790468U
+#define DBSC_DBODT3 0xE679046CU
+#define DBSC_DBODT4 0xE6790470U
+#define DBSC_DBODT5 0xE6790474U
+#define DBSC_DBODT6 0xE6790478U
+#define DBSC_DBODT7 0xE679047CU
+#define DBSC_DBADJ0 0xE6790500U
+#define DBSC_DBDBICNT 0xE6790518U
+#define DBSC_DBDFIPMSTRCNF 0xE6790520U
+#define DBSC_DBDFIPMSTRSTAT 0xE6790524U
+#define DBSC_DBDFILPCNF 0xE6790528U
+#define DBSC_DBDFICUPDCNF 0xE679052CU
+#define DBSC_DBDFISTAT0 0xE6790600U
+#define DBSC_DBDFICNT0 0xE6790604U
+#define DBSC_DBPDCNT00 0xE6790610U
+#define DBSC_DBPDCNT01 0xE6790614U
+#define DBSC_DBPDCNT02 0xE6790618U
+#define DBSC_DBPDCNT03 0xE679061CU
+#define DBSC_DBPDLK0 0xE6790620U
+#define DBSC_DBPDRGA0 0xE6790624U
+#define DBSC_DBPDRGD0 0xE6790628U
+#define DBSC_DBPDSTAT00 0xE6790630U
+#define DBSC_DBDFISTAT1 0xE6790640U
+#define DBSC_DBDFICNT1 0xE6790644U
+#define DBSC_DBPDCNT10 0xE6790650U
+#define DBSC_DBPDCNT11 0xE6790654U
+#define DBSC_DBPDCNT12 0xE6790658U
+#define DBSC_DBPDCNT13 0xE679065CU
+#define DBSC_DBPDLK1 0xE6790660U
+#define DBSC_DBPDRGA1 0xE6790664U
+#define DBSC_DBPDRGD1 0xE6790668U
+#define DBSC_DBPDSTAT10 0xE6790670U
+#define DBSC_DBDFISTAT2 0xE6790680U
+#define DBSC_DBDFICNT2 0xE6790684U
+#define DBSC_DBPDCNT20 0xE6790690U
+#define DBSC_DBPDCNT21 0xE6790694U
+#define DBSC_DBPDCNT22 0xE6790698U
+#define DBSC_DBPDCNT23 0xE679069CU
+#define DBSC_DBPDLK2 0xE67906A0U
+#define DBSC_DBPDRGA2 0xE67906A4U
+#define DBSC_DBPDRGD2 0xE67906A8U
+#define DBSC_DBPDSTAT20 0xE67906B0U
+#define DBSC_DBDFISTAT3 0xE67906C0U
+#define DBSC_DBDFICNT3 0xE67906C4U
+#define DBSC_DBPDCNT30 0xE67906D0U
+#define DBSC_DBPDCNT31 0xE67906D4U
+#define DBSC_DBPDCNT32 0xE67906D8U
+#define DBSC_DBPDCNT33 0xE67906DCU
+#define DBSC_DBPDLK3 0xE67906E0U
+#define DBSC_DBPDRGA3 0xE67906E4U
+#define DBSC_DBPDRGD3 0xE67906E8U
+#define DBSC_DBPDSTAT30 0xE67906F0U
+#define DBSC_DBBUS0CNF0 0xE6790800U
+#define DBSC_DBBUS0CNF1 0xE6790804U
+#define DBSC_DBCAM0CNF1 0xE6790904U
+#define DBSC_DBCAM0CNF2 0xE6790908U
+#define DBSC_DBCAM0CNF3 0xE679090CU
+#define DBSC_DBCAM0CTRL0 0xE6790940U
+#define DBSC_DBCAM0STAT0 0xE6790980U
+#define DBSC_DBCAM1STAT0 0xE6790990U
+#define DBSC_DBBCAMSWAP 0xE67909F0U
+#define DBSC_DBBCAMDIS 0xE67909FCU
+#define DBSC_DBSCHCNT0 0xE6791000U
+#define DBSC_DBSCHCNT1 0xE6791004U
+#define DBSC_DBSCHSZ0 0xE6791010U
+#define DBSC_DBSCHRW0 0xE6791020U
+#define DBSC_DBSCHRW1 0xE6791024U
+#define DBSC_DBSCHQOS00 0xE6791030U
+#define DBSC_DBSCHQOS01 0xE6791034U
+#define DBSC_DBSCHQOS02 0xE6791038U
+#define DBSC_DBSCHQOS03 0xE679103CU
+#define DBSC_DBSCHQOS10 0xE6791040U
+#define DBSC_DBSCHQOS11 0xE6791044U
+#define DBSC_DBSCHQOS12 0xE6791048U
+#define DBSC_DBSCHQOS13 0xE679104CU
+#define DBSC_DBSCHQOS20 0xE6791050U
+#define DBSC_DBSCHQOS21 0xE6791054U
+#define DBSC_DBSCHQOS22 0xE6791058U
+#define DBSC_DBSCHQOS23 0xE679105CU
+#define DBSC_DBSCHQOS30 0xE6791060U
+#define DBSC_DBSCHQOS31 0xE6791064U
+#define DBSC_DBSCHQOS32 0xE6791068U
+#define DBSC_DBSCHQOS33 0xE679106CU
+#define DBSC_DBSCHQOS40 0xE6791070U
+#define DBSC_DBSCHQOS41 0xE6791074U
+#define DBSC_DBSCHQOS42 0xE6791078U
+#define DBSC_DBSCHQOS43 0xE679107CU
+#define DBSC_DBSCHQOS50 0xE6791080U
+#define DBSC_DBSCHQOS51 0xE6791084U
+#define DBSC_DBSCHQOS52 0xE6791088U
+#define DBSC_DBSCHQOS53 0xE679108CU
+#define DBSC_DBSCHQOS60 0xE6791090U
+#define DBSC_DBSCHQOS61 0xE6791094U
+#define DBSC_DBSCHQOS62 0xE6791098U
+#define DBSC_DBSCHQOS63 0xE679109CU
+#define DBSC_DBSCHQOS70 0xE67910A0U
+#define DBSC_DBSCHQOS71 0xE67910A4U
+#define DBSC_DBSCHQOS72 0xE67910A8U
+#define DBSC_DBSCHQOS73 0xE67910ACU
+#define DBSC_DBSCHQOS80 0xE67910B0U
+#define DBSC_DBSCHQOS81 0xE67910B4U
+#define DBSC_DBSCHQOS82 0xE67910B8U
+#define DBSC_DBSCHQOS83 0xE67910BCU
+#define DBSC_DBSCHQOS90 0xE67910C0U
+#define DBSC_DBSCHQOS91 0xE67910C4U
+#define DBSC_DBSCHQOS92 0xE67910C8U
+#define DBSC_DBSCHQOS93 0xE67910CCU
+#define DBSC_DBSCHQOS100 0xE67910D0U
+#define DBSC_DBSCHQOS101 0xE67910D4U
+#define DBSC_DBSCHQOS102 0xE67910D8U
+#define DBSC_DBSCHQOS103 0xE67910DCU
+#define DBSC_DBSCHQOS110 0xE67910E0U
+#define DBSC_DBSCHQOS111 0xE67910E4U
+#define DBSC_DBSCHQOS112 0xE67910E8U
+#define DBSC_DBSCHQOS113 0xE67910ECU
+#define DBSC_DBSCHQOS120 0xE67910F0U
+#define DBSC_DBSCHQOS121 0xE67910F4U
+#define DBSC_DBSCHQOS122 0xE67910F8U
+#define DBSC_DBSCHQOS123 0xE67910FCU
+#define DBSC_DBSCHQOS130 0xE6791100U
+#define DBSC_DBSCHQOS131 0xE6791104U
+#define DBSC_DBSCHQOS132 0xE6791108U
+#define DBSC_DBSCHQOS133 0xE679110CU
+#define DBSC_DBSCHQOS140 0xE6791110U
+#define DBSC_DBSCHQOS141 0xE6791114U
+#define DBSC_DBSCHQOS142 0xE6791118U
+#define DBSC_DBSCHQOS143 0xE679111CU
+#define DBSC_DBSCHQOS150 0xE6791120U
+#define DBSC_DBSCHQOS151 0xE6791124U
+#define DBSC_DBSCHQOS152 0xE6791128U
+#define DBSC_DBSCHQOS153 0xE679112CU
+#define DBSC_SCFCTST0 0xE6791700U
+#define DBSC_SCFCTST1 0xE6791708U
+#define DBSC_SCFCTST2 0xE679170CU
+#define DBSC_DBMRRDR0 0xE6791800U
+#define DBSC_DBMRRDR1 0xE6791804U
+#define DBSC_DBMRRDR2 0xE6791808U
+#define DBSC_DBMRRDR3 0xE679180CU
+#define DBSC_DBMRRDR4 0xE6791810U
+#define DBSC_DBMRRDR5 0xE6791814U
+#define DBSC_DBMRRDR6 0xE6791818U
+#define DBSC_DBMRRDR7 0xE679181CU
+#define DBSC_DBDTMP0 0xE6791820U
+#define DBSC_DBDTMP1 0xE6791824U
+#define DBSC_DBDTMP2 0xE6791828U
+#define DBSC_DBDTMP3 0xE679182CU
+#define DBSC_DBDTMP4 0xE6791830U
+#define DBSC_DBDTMP5 0xE6791834U
+#define DBSC_DBDTMP6 0xE6791838U
+#define DBSC_DBDTMP7 0xE679183CU
+#define DBSC_DBDQSOSC00 0xE6791840U
+#define DBSC_DBDQSOSC01 0xE6791844U
+#define DBSC_DBDQSOSC10 0xE6791848U
+#define DBSC_DBDQSOSC11 0xE679184CU
+#define DBSC_DBDQSOSC20 0xE6791850U
+#define DBSC_DBDQSOSC21 0xE6791854U
+#define DBSC_DBDQSOSC30 0xE6791858U
+#define DBSC_DBDQSOSC31 0xE679185CU
+#define DBSC_DBDQSOSC40 0xE6791860U
+#define DBSC_DBDQSOSC41 0xE6791864U
+#define DBSC_DBDQSOSC50 0xE6791868U
+#define DBSC_DBDQSOSC51 0xE679186CU
+#define DBSC_DBDQSOSC60 0xE6791870U
+#define DBSC_DBDQSOSC61 0xE6791874U
+#define DBSC_DBDQSOSC70 0xE6791878U
+#define DBSC_DBDQSOSC71 0xE679187CU
+#define DBSC_DBOSCTHH00 0xE6791880U
+#define DBSC_DBOSCTHH01 0xE6791884U
+#define DBSC_DBOSCTHH10 0xE6791888U
+#define DBSC_DBOSCTHH11 0xE679188CU
+#define DBSC_DBOSCTHH20 0xE6791890U
+#define DBSC_DBOSCTHH21 0xE6791894U
+#define DBSC_DBOSCTHH30 0xE6791898U
+#define DBSC_DBOSCTHH31 0xE679189CU
+#define DBSC_DBOSCTHH40 0xE67918A0U
+#define DBSC_DBOSCTHH41 0xE67918A4U
+#define DBSC_DBOSCTHH50 0xE67918A8U
+#define DBSC_DBOSCTHH51 0xE67918ACU
+#define DBSC_DBOSCTHH60 0xE67918B0U
+#define DBSC_DBOSCTHH61 0xE67918B4U
+#define DBSC_DBOSCTHH70 0xE67918B8U
+#define DBSC_DBOSCTHH71 0xE67918BCU
+#define DBSC_DBOSCTHL00 0xE67918C0U
+#define DBSC_DBOSCTHL01 0xE67918C4U
+#define DBSC_DBOSCTHL10 0xE67918C8U
+#define DBSC_DBOSCTHL11 0xE67918CCU
+#define DBSC_DBOSCTHL20 0xE67918D0U
+#define DBSC_DBOSCTHL21 0xE67918D4U
+#define DBSC_DBOSCTHL30 0xE67918D8U
+#define DBSC_DBOSCTHL31 0xE67918DCU
+#define DBSC_DBOSCTHL40 0xE67918E0U
+#define DBSC_DBOSCTHL41 0xE67918E4U
+#define DBSC_DBOSCTHL50 0xE67918E8U
+#define DBSC_DBOSCTHL51 0xE67918ECU
+#define DBSC_DBOSCTHL60 0xE67918F0U
+#define DBSC_DBOSCTHL61 0xE67918F4U
+#define DBSC_DBOSCTHL70 0xE67918F8U
+#define DBSC_DBOSCTHL71 0xE67918FCU
+#define DBSC_DBMEMSWAPCONF0 0xE6792000U
+
+/* CPG registers */
+#define CPG_SRCR4 0xE61500BCU
+#define CPG_PLLECR 0xE61500D0U
+#define CPG_CPGWPR 0xE6150900U
+#define CPG_CPGWPCR 0xE6150904U
+#define CPG_SRSTCLR4 0xE6150950U
+
+/* MODE Monitor registers */
+#define RST_MODEMR 0xE6160060U
+
+#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h
deleted file mode 100644
index e157ab1..0000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/*
- * Revision history
- *
- * rev.0.01 2017/05/22 New
- */
-
-#ifndef BOOT_INIT_DRAM_REGDEF_D3_H_
-#define BOOT_INIT_DRAM_REGDEF_D3_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-#define BIT0 0x00000001U
-#define BIT30 0x40000000U
-
-/* DBSC registers */
-
-#define DBSC_D3_DBSYSCONF1 0xE6790004U
-#define DBSC_D3_DBPHYCONF0 0xE6790010U
-#define DBSC_D3_DBKIND 0xE6790020U
-#define DBSC_D3_DBMEMCONF00 0xE6790030U
-#define DBSC_D3_DBMEMCONF01 0xE6790034U
-#define DBSC_D3_DBMEMCONF02 0xE6790038U
-#define DBSC_D3_DBMEMCONF03 0xE679003CU
-#define DBSC_D3_DBMEMCONF10 0xE6790040U
-#define DBSC_D3_DBMEMCONF11 0xE6790044U
-#define DBSC_D3_DBMEMCONF12 0xE6790048U
-#define DBSC_D3_DBMEMCONF13 0xE679004CU
-#define DBSC_D3_DBMEMCONF20 0xE6790050U
-#define DBSC_D3_DBMEMCONF21 0xE6790054U
-#define DBSC_D3_DBMEMCONF22 0xE6790058U
-#define DBSC_D3_DBMEMCONF23 0xE679005CU
-#define DBSC_D3_DBMEMCONF30 0xE6790060U
-#define DBSC_D3_DBMEMCONF31 0xE6790064U
-#define DBSC_D3_DBMEMCONF32 0xE6790068U
-#define DBSC_D3_DBMEMCONF33 0xE679006CU
-#define DBSC_D3_DBSYSCNT0 0xE6790100U
-#define DBSC_D3_DBSVCR1 0xE6790104U
-#define DBSC_D3_DBSTATE0 0xE6790108U
-#define DBSC_D3_DBSTATE1 0xE679010CU
-#define DBSC_D3_DBINTEN 0xE6790180U
-#define DBSC_D3_DBINTSTAT0 0xE6790184U
-#define DBSC_D3_DBACEN 0xE6790200U
-#define DBSC_D3_DBRFEN 0xE6790204U
-#define DBSC_D3_DBCMD 0xE6790208U
-#define DBSC_D3_DBWAIT 0xE6790210U
-#define DBSC_D3_DBSYSCTRL0 0xE6790280U
-#define DBSC_D3_DBTR0 0xE6790300U
-#define DBSC_D3_DBTR1 0xE6790304U
-#define DBSC_D3_DBTR2 0xE6790308U
-#define DBSC_D3_DBTR3 0xE679030CU
-#define DBSC_D3_DBTR4 0xE6790310U
-#define DBSC_D3_DBTR5 0xE6790314U
-#define DBSC_D3_DBTR6 0xE6790318U
-#define DBSC_D3_DBTR7 0xE679031CU
-#define DBSC_D3_DBTR8 0xE6790320U
-#define DBSC_D3_DBTR9 0xE6790324U
-#define DBSC_D3_DBTR10 0xE6790328U
-#define DBSC_D3_DBTR11 0xE679032CU
-#define DBSC_D3_DBTR12 0xE6790330U
-#define DBSC_D3_DBTR13 0xE6790334U
-#define DBSC_D3_DBTR14 0xE6790338U
-#define DBSC_D3_DBTR15 0xE679033CU
-#define DBSC_D3_DBTR16 0xE6790340U
-#define DBSC_D3_DBTR17 0xE6790344U
-#define DBSC_D3_DBTR18 0xE6790348U
-#define DBSC_D3_DBTR19 0xE679034CU
-#define DBSC_D3_DBTR20 0xE6790350U
-#define DBSC_D3_DBTR21 0xE6790354U
-#define DBSC_D3_DBTR22 0xE6790358U
-#define DBSC_D3_DBTR24 0xE6790360U
-#define DBSC_D3_DBTR25 0xE6790364U
-#define DBSC_D3_DBBL 0xE6790400U
-#define DBSC_D3_DBRFCNF1 0xE6790414U
-#define DBSC_D3_DBRFCNF2 0xE6790418U
-#define DBSC_D3_DBCALCNF 0xE6790424U
-#define DBSC_D3_DBRNK2 0xE6790438U
-#define DBSC_D3_DBRNK3 0xE679043CU
-#define DBSC_D3_DBRNK4 0xE6790440U
-#define DBSC_D3_DBRNK5 0xE6790444U
-#define DBSC_D3_DBPDNCNF 0xE6790450U
-#define DBSC_D3_DBODT0 0xE6790460U
-#define DBSC_D3_DBODT1 0xE6790464U
-#define DBSC_D3_DBODT2 0xE6790468U
-#define DBSC_D3_DBODT3 0xE679046CU
-#define DBSC_D3_DBADJ0 0xE6790500U
-#define DBSC_D3_DBDBICNT 0xE6790518U
-#define DBSC_D3_DBDFICUPDCNF 0xE679052CU
-#define DBSC_D3_DBDFICNT0 0xE6790604U
-#define DBSC_D3_DBPDLK0 0xE6790620U
-#define DBSC_D3_DBPDRGA0 0xE6790624U
-#define DBSC_D3_DBPDRGD0 0xE6790628U
-#define DBSC_D3_DBPDSTAT00 0xE6790630U
-#define DBSC_D3_DBDFISTAT1 0xE6790640U
-#define DBSC_D3_DBDFICNT1 0xE6790644U
-#define DBSC_D3_DBPDLK1 0xE6790660U
-#define DBSC_D3_DBPDRGA1 0xE6790664U
-#define DBSC_D3_DBPDRGD1 0xE6790668U
-#define DBSC_D3_DBDFICNT2 0xE6790684U
-#define DBSC_D3_DBPDLK2 0xE67906A0U
-#define DBSC_D3_DBPDRGA2 0xE67906A4U
-#define DBSC_D3_DBPDRGD2 0xE67906A8U
-#define DBSC_D3_DBPDSTAT20 0xE67906B0U
-#define DBSC_D3_DBDFISTAT3 0xE67906C0U
-#define DBSC_D3_DBDFICNT3 0xE67906C4U
-#define DBSC_D3_DBPDLK3 0xE67906E0U
-#define DBSC_D3_DBPDRGA3 0xE67906E4U
-#define DBSC_D3_DBPDRGD3 0xE67906E8U
-#define DBSC_D3_DBBUS0CNF1 0xE6790804U
-#define DBSC_D3_DBCAM0CNF1 0xE6790904U
-#define DBSC_D3_DBCAM0CNF2 0xE6790908U
-#define DBSC_D3_DBCAM0STAT0 0xE6790980U
-#define DBSC_D3_DBCAM1STAT0 0xE6790990U
-#define DBSC_D3_DBBCAMDIS 0xE67909FCU
-#define DBSC_D3_DBSCHCNT0 0xE6791000U
-#define DBSC_D3_DBSCHSZ0 0xE6791010U
-#define DBSC_D3_DBSCHRW0 0xE6791020U
-#define DBSC_D3_DBSCHRW1 0xE6791024U
-#define DBSC_D3_DBSCHQOS00 0xE6791030U
-#define DBSC_D3_DBSCHQOS01 0xE6791034U
-#define DBSC_D3_DBSCHQOS02 0xE6791038U
-#define DBSC_D3_DBSCHQOS03 0xE679103CU
-#define DBSC_D3_DBSCHQOS10 0xE6791040U
-#define DBSC_D3_DBSCHQOS11 0xE6791044U
-#define DBSC_D3_DBSCHQOS12 0xE6791048U
-#define DBSC_D3_DBSCHQOS13 0xE679104CU
-#define DBSC_D3_DBSCHQOS20 0xE6791050U
-#define DBSC_D3_DBSCHQOS21 0xE6791054U
-#define DBSC_D3_DBSCHQOS22 0xE6791058U
-#define DBSC_D3_DBSCHQOS23 0xE679105CU
-#define DBSC_D3_DBSCHQOS30 0xE6791060U
-#define DBSC_D3_DBSCHQOS31 0xE6791064U
-#define DBSC_D3_DBSCHQOS32 0xE6791068U
-#define DBSC_D3_DBSCHQOS33 0xE679106CU
-#define DBSC_D3_DBSCHQOS40 0xE6791070U
-#define DBSC_D3_DBSCHQOS41 0xE6791074U
-#define DBSC_D3_DBSCHQOS42 0xE6791078U
-#define DBSC_D3_DBSCHQOS43 0xE679107CU
-#define DBSC_D3_DBSCHQOS50 0xE6791080U
-#define DBSC_D3_DBSCHQOS51 0xE6791084U
-#define DBSC_D3_DBSCHQOS52 0xE6791088U
-#define DBSC_D3_DBSCHQOS53 0xE679108CU
-#define DBSC_D3_DBSCHQOS60 0xE6791090U
-#define DBSC_D3_DBSCHQOS61 0xE6791094U
-#define DBSC_D3_DBSCHQOS62 0xE6791098U
-#define DBSC_D3_DBSCHQOS63 0xE679109CU
-#define DBSC_D3_DBSCHQOS70 0xE67910A0U
-#define DBSC_D3_DBSCHQOS71 0xE67910A4U
-#define DBSC_D3_DBSCHQOS72 0xE67910A8U
-#define DBSC_D3_DBSCHQOS73 0xE67910ACU
-#define DBSC_D3_DBSCHQOS80 0xE67910B0U
-#define DBSC_D3_DBSCHQOS81 0xE67910B4U
-#define DBSC_D3_DBSCHQOS82 0xE67910B8U
-#define DBSC_D3_DBSCHQOS83 0xE67910BCU
-#define DBSC_D3_DBSCHQOS90 0xE67910C0U
-#define DBSC_D3_DBSCHQOS91 0xE67910C4U
-#define DBSC_D3_DBSCHQOS92 0xE67910C8U
-#define DBSC_D3_DBSCHQOS93 0xE67910CCU
-#define DBSC_D3_DBSCHQOS100 0xE67910D0U
-#define DBSC_D3_DBSCHQOS101 0xE67910D4U
-#define DBSC_D3_DBSCHQOS102 0xE67910D8U
-#define DBSC_D3_DBSCHQOS103 0xE67910DCU
-#define DBSC_D3_DBSCHQOS110 0xE67910E0U
-#define DBSC_D3_DBSCHQOS111 0xE67910E4U
-#define DBSC_D3_DBSCHQOS112 0xE67910E8U
-#define DBSC_D3_DBSCHQOS113 0xE67910ECU
-#define DBSC_D3_DBSCHQOS120 0xE67910F0U
-#define DBSC_D3_DBSCHQOS121 0xE67910F4U
-#define DBSC_D3_DBSCHQOS122 0xE67910F8U
-#define DBSC_D3_DBSCHQOS123 0xE67910FCU
-#define DBSC_D3_DBSCHQOS130 0xE6791100U
-#define DBSC_D3_DBSCHQOS131 0xE6791104U
-#define DBSC_D3_DBSCHQOS132 0xE6791108U
-#define DBSC_D3_DBSCHQOS133 0xE679110CU
-#define DBSC_D3_DBSCHQOS140 0xE6791110U
-#define DBSC_D3_DBSCHQOS141 0xE6791114U
-#define DBSC_D3_DBSCHQOS142 0xE6791118U
-#define DBSC_D3_DBSCHQOS143 0xE679111CU
-#define DBSC_D3_DBSCHQOS150 0xE6791120U
-#define DBSC_D3_DBSCHQOS151 0xE6791124U
-#define DBSC_D3_DBSCHQOS152 0xE6791128U
-#define DBSC_D3_DBSCHQOS153 0xE679112CU
-#define DBSC_D3_SCFCTST0 0xE6791700U
-#define DBSC_D3_SCFCTST1 0xE6791708U
-#define DBSC_D3_SCFCTST2 0xE679170CU
-#define DBSC_D3_DBMRRDR0 0xE6791800U
-#define DBSC_D3_DBMRRDR1 0xE6791804U
-#define DBSC_D3_DBMRRDR2 0xE6791808U
-#define DBSC_D3_DBMRRDR3 0xE679180CU
-#define DBSC_D3_DBMRRDR4 0xE6791810U
-#define DBSC_D3_DBMRRDR5 0xE6791814U
-#define DBSC_D3_DBMRRDR6 0xE6791818U
-#define DBSC_D3_DBMRRDR7 0xE679181CU
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* BOOT_INIT_DRAM_REGDEF_D3_H_*/
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h
deleted file mode 100644
index 8606f76..0000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_REGDEF_E3_H
-#define BOOT_INIT_DRAM_REGDEF_E3_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-#define BIT0 0x00000001U
-#define BIT11 0x00000800U
-#define BIT30 0x40000000U
-
-/* DBSC registers */
-
-#define DBSC_E3_DBSYSCONF1 0xE6790004U
-#define DBSC_E3_DBPHYCONF0 0xE6790010U
-#define DBSC_E3_DBKIND 0xE6790020U
-#define DBSC_E3_DBMEMCONF00 0xE6790030U
-#define DBSC_E3_DBSYSCNT0 0xE6790100U
-#define DBSC_E3_DBACEN 0xE6790200U
-#define DBSC_E3_DBRFEN 0xE6790204U
-#define DBSC_E3_DBCMD 0xE6790208U
-#define DBSC_E3_DBWAIT 0xE6790210U
-#define DBSC_E3_DBTR0 0xE6790300U
-#define DBSC_E3_DBTR1 0xE6790304U
-#define DBSC_E3_DBTR2 0xE6790308U
-#define DBSC_E3_DBTR3 0xE679030CU
-#define DBSC_E3_DBTR4 0xE6790310U
-#define DBSC_E3_DBTR5 0xE6790314U
-#define DBSC_E3_DBTR6 0xE6790318U
-#define DBSC_E3_DBTR7 0xE679031CU
-#define DBSC_E3_DBTR8 0xE6790320U
-#define DBSC_E3_DBTR9 0xE6790324U
-#define DBSC_E3_DBTR10 0xE6790328U
-#define DBSC_E3_DBTR11 0xE679032CU
-#define DBSC_E3_DBTR12 0xE6790330U
-#define DBSC_E3_DBTR13 0xE6790334U
-#define DBSC_E3_DBTR14 0xE6790338U
-#define DBSC_E3_DBTR15 0xE679033CU
-#define DBSC_E3_DBTR16 0xE6790340U
-#define DBSC_E3_DBTR17 0xE6790344U
-#define DBSC_E3_DBTR18 0xE6790348U
-#define DBSC_E3_DBTR19 0xE679034CU
-#define DBSC_E3_DBTR20 0xE6790350U
-#define DBSC_E3_DBTR21 0xE6790354U
-#define DBSC_E3_DBBL 0xE6790400U
-#define DBSC_E3_DBRFCNF1 0xE6790414U
-#define DBSC_E3_DBRFCNF2 0xE6790418U
-#define DBSC_E3_DBCALCNF 0xE6790424U
-#define DBSC_E3_DBODT0 0xE6790460U
-#define DBSC_E3_DBADJ0 0xE6790500U
-#define DBSC_E3_DBDFICUPDCNF 0xE679052CU
-#define DBSC_E3_DBDFICNT0 0xE6790604U
-#define DBSC_E3_DBPDLK0 0xE6790620U
-#define DBSC_E3_DBPDRGA0 0xE6790624U
-#define DBSC_E3_DBPDRGD0 0xE6790628U
-#define DBSC_E3_DBBUS0CNF1 0xE6790804U
-#define DBSC_E3_DBCAM0CNF1 0xE6790904U
-#define DBSC_E3_DBCAM0CNF2 0xE6790908U
-#define DBSC_E3_DBCAM0STAT0 0xE6790980U
-#define DBSC_E3_DBBCAMDIS 0xE67909FCU
-#define DBSC_E3_DBSCHCNT0 0xE6791000U
-#define DBSC_E3_DBSCHSZ0 0xE6791010U
-#define DBSC_E3_DBSCHRW0 0xE6791020U
-#define DBSC_E3_DBSCHRW1 0xE6791024U
-#define DBSC_E3_DBSCHQOS00 0xE6791030U
-#define DBSC_E3_DBSCHQOS01 0xE6791034U
-#define DBSC_E3_DBSCHQOS02 0xE6791038U
-#define DBSC_E3_DBSCHQOS03 0xE679103CU
-#define DBSC_E3_DBSCHQOS40 0xE6791070U
-#define DBSC_E3_DBSCHQOS41 0xE6791074U
-#define DBSC_E3_DBSCHQOS42 0xE6791078U
-#define DBSC_E3_DBSCHQOS43 0xE679107CU
-#define DBSC_E3_DBSCHQOS90 0xE67910C0U
-#define DBSC_E3_DBSCHQOS91 0xE67910C4U
-#define DBSC_E3_DBSCHQOS92 0xE67910C8U
-#define DBSC_E3_DBSCHQOS93 0xE67910CCU
-#define DBSC_E3_DBSCHQOS130 0xE6791100U
-#define DBSC_E3_DBSCHQOS131 0xE6791104U
-#define DBSC_E3_DBSCHQOS132 0xE6791108U
-#define DBSC_E3_DBSCHQOS133 0xE679110CU
-#define DBSC_E3_DBSCHQOS140 0xE6791110U
-#define DBSC_E3_DBSCHQOS141 0xE6791114U
-#define DBSC_E3_DBSCHQOS142 0xE6791118U
-#define DBSC_E3_DBSCHQOS143 0xE679111CU
-#define DBSC_E3_DBSCHQOS150 0xE6791120U
-#define DBSC_E3_DBSCHQOS151 0xE6791124U
-#define DBSC_E3_DBSCHQOS152 0xE6791128U
-#define DBSC_E3_DBSCHQOS153 0xE679112CU
-#define DBSC_E3_SCFCTST0 0xE6791700U
-#define DBSC_E3_SCFCTST1 0xE6791708U
-#define DBSC_E3_SCFCTST2 0xE679170CU
-
-/* CPG registers */
-
-#define CPG_SRCR4 0xE61500BCU
-#define CPG_PLLECR 0xE61500D0U
-#define CPG_CPGWPR 0xE6150900U
-#define CPG_CPGWPCR 0xE6150904U
-#define CPG_SRSTCLR4 0xE6150950U
-
-/* MODE Monitor registers */
-
-#define RST_MODEMR 0xE6160060U
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* BOOT_INIT_DRAM_REGDEF_E3_H */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h
deleted file mode 100644
index ecb8e62..0000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Copyright (c) 2015-2016, Renesas Electronics Corporation
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_REGDEF_V3M_H_
-#define BOOT_INIT_DRAM_REGDEF_V3M_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-#define BIT0 0x00000001U
-#define BIT30 0x40000000U
-
-/* DBSC registers */
-
-// modified , last 2016.12.08
-
-#define DBSC_V3M_DBSYSCONF0 0xE6790000U
-#define DBSC_V3M_DBSYSCONF1 0xE6790004U
-#define DBSC_V3M_DBPHYCONF0 0xE6790010U
-#define DBSC_V3M_DBKIND 0xE6790020U
-#define DBSC_V3M_DBMEMCONF00 0xE6790030U
-#define DBSC_V3M_DBMEMCONF01 0xE6790034U
-#define DBSC_V3M_DBMEMCONF02 0xE6790038U
-#define DBSC_V3M_DBMEMCONF03 0xE679003CU
-#define DBSC_V3M_DBMEMCONF10 0xE6790040U
-#define DBSC_V3M_DBMEMCONF11 0xE6790044U
-#define DBSC_V3M_DBMEMCONF12 0xE6790048U
-#define DBSC_V3M_DBMEMCONF13 0xE679004CU
-#define DBSC_V3M_DBMEMCONF20 0xE6790050U
-#define DBSC_V3M_DBMEMCONF21 0xE6790054U
-#define DBSC_V3M_DBMEMCONF22 0xE6790058U
-#define DBSC_V3M_DBMEMCONF23 0xE679005CU
-#define DBSC_V3M_DBMEMCONF30 0xE6790060U
-#define DBSC_V3M_DBMEMCONF31 0xE6790064U
-#define DBSC_V3M_DBMEMCONF32 0xE6790068U
-#define DBSC_V3M_DBMEMCONF33 0xE679006CU
-#define DBSC_V3M_DBSYSCNT0 0xE6790100U
-#define DBSC_V3M_DBSVCR1 0xE6790104U
-#define DBSC_V3M_DBSTATE0 0xE6790108U
-#define DBSC_V3M_DBSTATE1 0xE679010CU
-#define DBSC_V3M_DBINTEN 0xE6790180U
-#define DBSC_V3M_DBINTSTAT0 0xE6790184U
-#define DBSC_V3M_DBACEN 0xE6790200U
-#define DBSC_V3M_DBRFEN 0xE6790204U
-#define DBSC_V3M_DBCMD 0xE6790208U
-#define DBSC_V3M_DBWAIT 0xE6790210U
-#define DBSC_V3M_DBSYSCTRL0 0xE6790280U
-#define DBSC_V3M_DBTR0 0xE6790300U
-#define DBSC_V3M_DBTR1 0xE6790304U
-#define DBSC_V3M_DBTR2 0xE6790308U
-#define DBSC_V3M_DBTR3 0xE679030CU
-#define DBSC_V3M_DBTR4 0xE6790310U
-#define DBSC_V3M_DBTR5 0xE6790314U
-#define DBSC_V3M_DBTR6 0xE6790318U
-#define DBSC_V3M_DBTR7 0xE679031CU
-#define DBSC_V3M_DBTR8 0xE6790320U
-#define DBSC_V3M_DBTR9 0xE6790324U
-#define DBSC_V3M_DBTR10 0xE6790328U
-#define DBSC_V3M_DBTR11 0xE679032CU
-#define DBSC_V3M_DBTR12 0xE6790330U
-#define DBSC_V3M_DBTR13 0xE6790334U
-#define DBSC_V3M_DBTR14 0xE6790338U
-#define DBSC_V3M_DBTR15 0xE679033CU
-#define DBSC_V3M_DBTR16 0xE6790340U
-#define DBSC_V3M_DBTR17 0xE6790344U
-#define DBSC_V3M_DBTR18 0xE6790348U
-#define DBSC_V3M_DBTR19 0xE679034CU
-#define DBSC_V3M_DBTR20 0xE6790350U
-#define DBSC_V3M_DBTR21 0xE6790354U
-#define DBSC_V3M_DBTR22 0xE6790358U
-#define DBSC_V3M_DBTR23 0xE679035CU
-#define DBSC_V3M_DBTR24 0xE6790360U
-#define DBSC_V3M_DBTR25 0xE6790364U
-#define DBSC_V3M_DBBL 0xE6790400U
-#define DBSC_V3M_DBRFCNF1 0xE6790414U
-#define DBSC_V3M_DBRFCNF2 0xE6790418U
-#define DBSC_V3M_DBTSPCNF 0xE6790420U
-#define DBSC_V3M_DBCALCNF 0xE6790424U
-#define DBSC_V3M_DBRNK2 0xE6790438U
-#define DBSC_V3M_DBRNK3 0xE679043CU
-#define DBSC_V3M_DBRNK4 0xE6790440U
-#define DBSC_V3M_DBRNK5 0xE6790444U
-#define DBSC_V3M_DBPDNCNF 0xE6790450U
-#define DBSC_V3M_DBODT0 0xE6790460U
-#define DBSC_V3M_DBODT1 0xE6790464U
-#define DBSC_V3M_DBODT2 0xE6790468U
-#define DBSC_V3M_DBODT3 0xE679046CU
-#define DBSC_V3M_DBODT4 0xE6790470U
-#define DBSC_V3M_DBODT5 0xE6790474U
-#define DBSC_V3M_DBODT6 0xE6790478U
-#define DBSC_V3M_DBODT7 0xE679047CU
-#define DBSC_V3M_DBADJ0 0xE6790500U
-#define DBSC_V3M_DBDBICNT 0xE6790518U
-#define DBSC_V3M_DBDFIPMSTRCNF 0xE6790520U
-#define DBSC_V3M_DBDFIPMSTRSTAT 0xE6790524U
-#define DBSC_V3M_DBDFILPCNF 0xE6790528U
-#define DBSC_V3M_DBDFICUPDCNF 0xE679052CU
-#define DBSC_V3M_DBDFISTAT0 0xE6790600U
-#define DBSC_V3M_DBDFICNT0 0xE6790604U
-#define DBSC_V3M_DBPDCNT00 0xE6790610U
-#define DBSC_V3M_DBPDCNT01 0xE6790614U
-#define DBSC_V3M_DBPDCNT02 0xE6790618U
-#define DBSC_V3M_DBPDCNT03 0xE679061CU
-#define DBSC_V3M_DBPDLK0 0xE6790620U
-#define DBSC_V3M_DBPDRGA0 0xE6790624U
-#define DBSC_V3M_DBPDRGD0 0xE6790628U
-#define DBSC_V3M_DBPDSTAT00 0xE6790630U
-#define DBSC_V3M_DBDFISTAT1 0xE6790640U
-#define DBSC_V3M_DBDFICNT1 0xE6790644U
-#define DBSC_V3M_DBPDCNT10 0xE6790650U
-#define DBSC_V3M_DBPDCNT11 0xE6790654U
-#define DBSC_V3M_DBPDCNT12 0xE6790658U
-#define DBSC_V3M_DBPDCNT13 0xE679065CU
-#define DBSC_V3M_DBPDLK1 0xE6790660U
-#define DBSC_V3M_DBPDRGA1 0xE6790664U
-#define DBSC_V3M_DBPDRGD1 0xE6790668U
-#define DBSC_V3M_DBPDSTAT10 0xE6790670U
-#define DBSC_V3M_DBDFISTAT2 0xE6790680U
-#define DBSC_V3M_DBDFICNT2 0xE6790684U
-#define DBSC_V3M_DBPDCNT20 0xE6790690U
-#define DBSC_V3M_DBPDCNT21 0xE6790694U
-#define DBSC_V3M_DBPDCNT22 0xE6790698U
-#define DBSC_V3M_DBPDCNT23 0xE679069CU
-#define DBSC_V3M_DBPDLK2 0xE67906A0U
-#define DBSC_V3M_DBPDRGA2 0xE67906A4U
-#define DBSC_V3M_DBPDRGD2 0xE67906A8U
-#define DBSC_V3M_DBPDSTAT20 0xE67906B0U
-#define DBSC_V3M_DBDFISTAT3 0xE67906C0U
-#define DBSC_V3M_DBDFICNT3 0xE67906C4U
-#define DBSC_V3M_DBPDCNT30 0xE67906D0U
-#define DBSC_V3M_DBPDCNT31 0xE67906D4U
-#define DBSC_V3M_DBPDCNT32 0xE67906D8U
-#define DBSC_V3M_DBPDCNT33 0xE67906DCU
-#define DBSC_V3M_DBPDLK3 0xE67906E0U
-#define DBSC_V3M_DBPDRGA3 0xE67906E4U
-#define DBSC_V3M_DBPDRGD3 0xE67906E8U
-#define DBSC_V3M_DBPDSTAT30 0xE67906F0U
-#define DBSC_V3M_DBBUS0CNF0 0xE6790800U
-#define DBSC_V3M_DBBUS0CNF1 0xE6790804U
-#define DBSC_V3M_DBCAM0CNF1 0xE6790904U
-#define DBSC_V3M_DBCAM0CNF2 0xE6790908U
-#define DBSC_V3M_DBCAM0CNF3 0xE679090CU
-#define DBSC_V3M_DBCAM0CTRL0 0xE6790940U
-#define DBSC_V3M_DBCAM0STAT0 0xE6790980U
-#define DBSC_V3M_DBCAM1STAT0 0xE6790990U
-#define DBSC_V3M_DBBCAMSWAP 0xE67909F0U
-#define DBSC_V3M_DBBCAMDIS 0xE67909FCU
-#define DBSC_V3M_DBSCHCNT0 0xE6791000U
-#define DBSC_V3M_DBSCHCNT1 0xE6791004U
-#define DBSC_V3M_DBSCHSZ0 0xE6791010U
-#define DBSC_V3M_DBSCHRW0 0xE6791020U
-#define DBSC_V3M_DBSCHRW1 0xE6791024U
-#define DBSC_V3M_DBSCHQOS00 0xE6791030U
-#define DBSC_V3M_DBSCHQOS01 0xE6791034U
-#define DBSC_V3M_DBSCHQOS02 0xE6791038U
-#define DBSC_V3M_DBSCHQOS03 0xE679103CU
-#define DBSC_V3M_DBSCHQOS10 0xE6791040U
-#define DBSC_V3M_DBSCHQOS11 0xE6791044U
-#define DBSC_V3M_DBSCHQOS12 0xE6791048U
-#define DBSC_V3M_DBSCHQOS13 0xE679104CU
-#define DBSC_V3M_DBSCHQOS20 0xE6791050U
-#define DBSC_V3M_DBSCHQOS21 0xE6791054U
-#define DBSC_V3M_DBSCHQOS22 0xE6791058U
-#define DBSC_V3M_DBSCHQOS23 0xE679105CU
-#define DBSC_V3M_DBSCHQOS30 0xE6791060U
-#define DBSC_V3M_DBSCHQOS31 0xE6791064U
-#define DBSC_V3M_DBSCHQOS32 0xE6791068U
-#define DBSC_V3M_DBSCHQOS33 0xE679106CU
-#define DBSC_V3M_DBSCHQOS40 0xE6791070U
-#define DBSC_V3M_DBSCHQOS41 0xE6791074U
-#define DBSC_V3M_DBSCHQOS42 0xE6791078U
-#define DBSC_V3M_DBSCHQOS43 0xE679107CU
-#define DBSC_V3M_DBSCHQOS50 0xE6791080U
-#define DBSC_V3M_DBSCHQOS51 0xE6791084U
-#define DBSC_V3M_DBSCHQOS52 0xE6791088U
-#define DBSC_V3M_DBSCHQOS53 0xE679108CU
-#define DBSC_V3M_DBSCHQOS60 0xE6791090U
-#define DBSC_V3M_DBSCHQOS61 0xE6791094U
-#define DBSC_V3M_DBSCHQOS62 0xE6791098U
-#define DBSC_V3M_DBSCHQOS63 0xE679109CU
-#define DBSC_V3M_DBSCHQOS70 0xE67910A0U
-#define DBSC_V3M_DBSCHQOS71 0xE67910A4U
-#define DBSC_V3M_DBSCHQOS72 0xE67910A8U
-#define DBSC_V3M_DBSCHQOS73 0xE67910ACU
-#define DBSC_V3M_DBSCHQOS80 0xE67910B0U
-#define DBSC_V3M_DBSCHQOS81 0xE67910B4U
-#define DBSC_V3M_DBSCHQOS82 0xE67910B8U
-#define DBSC_V3M_DBSCHQOS83 0xE67910BCU
-#define DBSC_V3M_DBSCHQOS90 0xE67910C0U
-#define DBSC_V3M_DBSCHQOS91 0xE67910C4U
-#define DBSC_V3M_DBSCHQOS92 0xE67910C8U
-#define DBSC_V3M_DBSCHQOS93 0xE67910CCU
-#define DBSC_V3M_DBSCHQOS100 0xE67910D0U
-#define DBSC_V3M_DBSCHQOS101 0xE67910D4U
-#define DBSC_V3M_DBSCHQOS102 0xE67910D8U
-#define DBSC_V3M_DBSCHQOS103 0xE67910DCU
-#define DBSC_V3M_DBSCHQOS110 0xE67910E0U
-#define DBSC_V3M_DBSCHQOS111 0xE67910E4U
-#define DBSC_V3M_DBSCHQOS112 0xE67910E8U
-#define DBSC_V3M_DBSCHQOS113 0xE67910ECU
-#define DBSC_V3M_DBSCHQOS120 0xE67910F0U
-#define DBSC_V3M_DBSCHQOS121 0xE67910F4U
-#define DBSC_V3M_DBSCHQOS122 0xE67910F8U
-#define DBSC_V3M_DBSCHQOS123 0xE67910FCU
-#define DBSC_V3M_DBSCHQOS130 0xE6791100U
-#define DBSC_V3M_DBSCHQOS131 0xE6791104U
-#define DBSC_V3M_DBSCHQOS132 0xE6791108U
-#define DBSC_V3M_DBSCHQOS133 0xE679110CU
-#define DBSC_V3M_DBSCHQOS140 0xE6791110U
-#define DBSC_V3M_DBSCHQOS141 0xE6791114U
-#define DBSC_V3M_DBSCHQOS142 0xE6791118U
-#define DBSC_V3M_DBSCHQOS143 0xE679111CU
-#define DBSC_V3M_DBSCHQOS150 0xE6791120U
-#define DBSC_V3M_DBSCHQOS151 0xE6791124U
-#define DBSC_V3M_DBSCHQOS152 0xE6791128U
-#define DBSC_V3M_DBSCHQOS153 0xE679112CU
-#define DBSC_V3M_SCFCTST0 0xE6791700U
-#define DBSC_V3M_SCFCTST1 0xE6791708U
-#define DBSC_V3M_SCFCTST2 0xE679170CU
-#define DBSC_V3M_DBMRRDR0 0xE6791800U
-#define DBSC_V3M_DBMRRDR1 0xE6791804U
-#define DBSC_V3M_DBMRRDR2 0xE6791808U
-#define DBSC_V3M_DBMRRDR3 0xE679180CU
-#define DBSC_V3M_DBMRRDR4 0xE6791810U
-#define DBSC_V3M_DBMRRDR5 0xE6791814U
-#define DBSC_V3M_DBMRRDR6 0xE6791818U
-#define DBSC_V3M_DBMRRDR7 0xE679181CU
-#define DBSC_V3M_DBDTMP0 0xE6791820U
-#define DBSC_V3M_DBDTMP1 0xE6791824U
-#define DBSC_V3M_DBDTMP2 0xE6791828U
-#define DBSC_V3M_DBDTMP3 0xE679182CU
-#define DBSC_V3M_DBDTMP4 0xE6791830U
-#define DBSC_V3M_DBDTMP5 0xE6791834U
-#define DBSC_V3M_DBDTMP6 0xE6791838U
-#define DBSC_V3M_DBDTMP7 0xE679183CU
-#define DBSC_V3M_DBDQSOSC00 0xE6791840U
-#define DBSC_V3M_DBDQSOSC01 0xE6791844U
-#define DBSC_V3M_DBDQSOSC10 0xE6791848U
-#define DBSC_V3M_DBDQSOSC11 0xE679184CU
-#define DBSC_V3M_DBDQSOSC20 0xE6791850U
-#define DBSC_V3M_DBDQSOSC21 0xE6791854U
-#define DBSC_V3M_DBDQSOSC30 0xE6791858U
-#define DBSC_V3M_DBDQSOSC31 0xE679185CU
-#define DBSC_V3M_DBDQSOSC40 0xE6791860U
-#define DBSC_V3M_DBDQSOSC41 0xE6791864U
-#define DBSC_V3M_DBDQSOSC50 0xE6791868U
-#define DBSC_V3M_DBDQSOSC51 0xE679186CU
-#define DBSC_V3M_DBDQSOSC60 0xE6791870U
-#define DBSC_V3M_DBDQSOSC61 0xE6791874U
-#define DBSC_V3M_DBDQSOSC70 0xE6791878U
-#define DBSC_V3M_DBDQSOSC71 0xE679187CU
-#define DBSC_V3M_DBOSCTHH00 0xE6791880U
-#define DBSC_V3M_DBOSCTHH01 0xE6791884U
-#define DBSC_V3M_DBOSCTHH10 0xE6791888U
-#define DBSC_V3M_DBOSCTHH11 0xE679188CU
-#define DBSC_V3M_DBOSCTHH20 0xE6791890U
-#define DBSC_V3M_DBOSCTHH21 0xE6791894U
-#define DBSC_V3M_DBOSCTHH30 0xE6791898U
-#define DBSC_V3M_DBOSCTHH31 0xE679189CU
-#define DBSC_V3M_DBOSCTHH40 0xE67918A0U
-#define DBSC_V3M_DBOSCTHH41 0xE67918A4U
-#define DBSC_V3M_DBOSCTHH50 0xE67918A8U
-#define DBSC_V3M_DBOSCTHH51 0xE67918ACU
-#define DBSC_V3M_DBOSCTHH60 0xE67918B0U
-#define DBSC_V3M_DBOSCTHH61 0xE67918B4U
-#define DBSC_V3M_DBOSCTHH70 0xE67918B8U
-#define DBSC_V3M_DBOSCTHH71 0xE67918BCU
-#define DBSC_V3M_DBOSCTHL00 0xE67918C0U
-#define DBSC_V3M_DBOSCTHL01 0xE67918C4U
-#define DBSC_V3M_DBOSCTHL10 0xE67918C8U
-#define DBSC_V3M_DBOSCTHL11 0xE67918CCU
-#define DBSC_V3M_DBOSCTHL20 0xE67918D0U
-#define DBSC_V3M_DBOSCTHL21 0xE67918D4U
-#define DBSC_V3M_DBOSCTHL30 0xE67918D8U
-#define DBSC_V3M_DBOSCTHL31 0xE67918DCU
-#define DBSC_V3M_DBOSCTHL40 0xE67918E0U
-#define DBSC_V3M_DBOSCTHL41 0xE67918E4U
-#define DBSC_V3M_DBOSCTHL50 0xE67918E8U
-#define DBSC_V3M_DBOSCTHL51 0xE67918ECU
-#define DBSC_V3M_DBOSCTHL60 0xE67918F0U
-#define DBSC_V3M_DBOSCTHL61 0xE67918F4U
-#define DBSC_V3M_DBOSCTHL70 0xE67918F8U
-#define DBSC_V3M_DBOSCTHL71 0xE67918FCU
-#define DBSC_V3M_DBMEMSWAPCONF0 0xE6792000U
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* BOOT_INIT_DRAM_REGDEF_V3M_H_*/
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
index 9a9d06a..d03b1b9 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,660 +9,668 @@
#include <lib/mmio.h>
#include <common/debug.h>
-#include "boot_init_dram_regdef_d3.h"
+#include "boot_init_dram_regdef.h"
-#define RCAR_DDR_VERSION "rev.0.01"
+#define RCAR_DDR_VERSION "rev.0.01"
#if RCAR_LSI != RCAR_D3
#error "Don't have DDR initialize routine."
#endif
-static void WriteReg_32(uint32_t a, uint32_t v)
+static void init_ddr_d3_1866(void)
{
- (*(volatile uint32_t*)(uintptr_t)a) = v;
-}
+ uint32_t i, r2, r3, r5, r6, r7, r12;
-static uint32_t ReadReg_32(uint32_t a)
-{
- uint32_t w = (*(volatile uint32_t*)(uintptr_t)a);
- return w;
-}
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ mmio_write_32(DBSC_DBKIND, 0x00000007);
+ mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
+ mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
+ mmio_write_32(DBSC_DBTR0, 0x0000000D);
+ mmio_write_32(DBSC_DBTR1, 0x00000009);
+ mmio_write_32(DBSC_DBTR2, 0x00000000);
+ mmio_write_32(DBSC_DBTR3, 0x0000000D);
+ mmio_write_32(DBSC_DBTR4, 0x000D000D);
+ mmio_write_32(DBSC_DBTR5, 0x0000002D);
+ mmio_write_32(DBSC_DBTR6, 0x00000020);
+ mmio_write_32(DBSC_DBTR7, 0x00060006);
+ mmio_write_32(DBSC_DBTR8, 0x00000021);
+ mmio_write_32(DBSC_DBTR9, 0x00000007);
+ mmio_write_32(DBSC_DBTR10, 0x0000000E);
+ mmio_write_32(DBSC_DBTR11, 0x0000000C);
+ mmio_write_32(DBSC_DBTR12, 0x00140014);
+ mmio_write_32(DBSC_DBTR13, 0x000000F2);
+ mmio_write_32(DBSC_DBTR14, 0x00170006);
+ mmio_write_32(DBSC_DBTR15, 0x00060005);
+ mmio_write_32(DBSC_DBTR16, 0x09210507);
+ mmio_write_32(DBSC_DBTR17, 0x040E0000);
+ mmio_write_32(DBSC_DBTR18, 0x00000200);
+ mmio_write_32(DBSC_DBTR19, 0x012B004B);
+ mmio_write_32(DBSC_DBTR20, 0x020000FB);
+ mmio_write_32(DBSC_DBTR21, 0x00040004);
+ mmio_write_32(DBSC_DBBL, 0x00000000);
+ mmio_write_32(DBSC_DBODT0, 0x00000001);
+ mmio_write_32(DBSC_DBADJ0, 0x00000001);
+ mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+ mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+ mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
+ mmio_write_32(DBSC_SCFCTST0, 0x0D020D04);
+ mmio_write_32(DBSC_SCFCTST1, 0x0306040C);
-static void init_ddr_d3_1866(void)
-{
- uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
+ mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBCMD, 0x01000001);
+ mmio_write_32(DBSC_DBCMD, 0x08000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
- WriteReg_32(DBSC_D3_DBKIND,0x00000007);
- WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
- WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
- WriteReg_32(DBSC_D3_DBTR0,0x0000000D);
- WriteReg_32(DBSC_D3_DBTR1,0x00000009);
- WriteReg_32(DBSC_D3_DBTR2,0x00000000);
- WriteReg_32(DBSC_D3_DBTR3,0x0000000D);
- WriteReg_32(DBSC_D3_DBTR4,0x000D000D);
- WriteReg_32(DBSC_D3_DBTR5,0x0000002D);
- WriteReg_32(DBSC_D3_DBTR6,0x00000020);
- WriteReg_32(DBSC_D3_DBTR7,0x00060006);
- WriteReg_32(DBSC_D3_DBTR8,0x00000021);
- WriteReg_32(DBSC_D3_DBTR9,0x00000007);
- WriteReg_32(DBSC_D3_DBTR10,0x0000000E);
- WriteReg_32(DBSC_D3_DBTR11,0x0000000C);
- WriteReg_32(DBSC_D3_DBTR12,0x00140014);
- WriteReg_32(DBSC_D3_DBTR13,0x000000F2);
- WriteReg_32(DBSC_D3_DBTR14,0x00170006);
- WriteReg_32(DBSC_D3_DBTR15,0x00060005);
- WriteReg_32(DBSC_D3_DBTR16,0x09210507);
- WriteReg_32(DBSC_D3_DBTR17,0x040E0000);
- WriteReg_32(DBSC_D3_DBTR18,0x00000200);
- WriteReg_32(DBSC_D3_DBTR19,0x012B004B);
- WriteReg_32(DBSC_D3_DBTR20,0x020000FB);
- WriteReg_32(DBSC_D3_DBTR21,0x00040004);
- WriteReg_32(DBSC_D3_DBBL,0x00000000);
- WriteReg_32(DBSC_D3_DBODT0,0x00000001);
- WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
- WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
- WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
- WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
- WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
- WriteReg_32(DBSC_D3_SCFCTST0,0x0D020D04);
- WriteReg_32(DBSC_D3_SCFCTST1,0x0306040C);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058A04);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
- WriteReg_32(DBSC_D3_DBCMD,0x01000001);
- WriteReg_32(DBSC_D3_DBCMD,0x08000000);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A04);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058A00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0A206F89);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
+ mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
+ mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
+ mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
+ mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
- while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0A206F89);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x35A00D77);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x2A8A2C28);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x30005E00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0014CB49);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00000F14);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x000000A0);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
+ r3 = (r2 << 16) + (r2 << 8) + r2;
+ r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
+ mmio_write_32(DBSC_DBPDRGD0, r3);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
+ mmio_write_32(DBSC_DBPDRGD0, r3);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
+ mmio_write_32(DBSC_DBPDRGD0, r6);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
+ mmio_write_32(DBSC_DBPDRGD0, r6);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
+ mmio_write_32(DBSC_DBPDRGD0, r6);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
+ mmio_write_32(DBSC_DBPDRGD0, r6);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
+ mmio_write_32(DBSC_DBCMD, 0x08000001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
- RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
- RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
- RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
- WriteReg_32(DBSC_D3_DBCMD,0x08000001);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ for (i = 0; i < 2; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ if (r6 > 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- for (uint32_t i = 0; i<2; i++)
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
- RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
- RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
- RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
- if ( RegVal_R6 > 0 )
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
- } else
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 |
+ ((r6 + (r5 << 1)) & 0xFF));
+ }
+ }
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
- }
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
- WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
- WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
+ r2 = mmio_read_32(DBSC_DBPDRGD0);
+ mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
+ r2 = mmio_read_32(DBSC_DBPDRGD0);
+ mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
- RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
- WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
- RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
- WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ for (i = 0; i < 2; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- for (uint32_t i = 0; i < 2; i++)
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
- RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
- RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ r12 = (r5 >> 0x2);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
- RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
- RegVal_R12 = (RegVal_R5 >> 0x2);
- if ( RegVal_R12 < RegVal_R6 )
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+ if (r12 < r6) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
- }
- else
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
- }
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 |
+ ((r6 + r5 +
+ (r5 >> 1) + r12) & 0xFF));
+ }
+ }
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
- while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ ;
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
- WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
- WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
- WriteReg_32(DBSC_D3_DBRFCNF1,0x00080E23);
- WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
- WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
- WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
- WriteReg_32(DBSC_D3_DBACEN,0x00000001);
- WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
- WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+ mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
+ mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
+ mmio_write_32(DBSC_DBRFCNF1, 0x00080E23);
+ mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+ mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+ mmio_write_32(DBSC_DBRFEN, 0x00000001);
+ mmio_write_32(DBSC_DBACEN, 0x00000001);
+ mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
#ifdef ddr_qos_init_setting // only for non qos_init
- WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
- WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
- WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
- WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
- WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
- WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
- WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
- WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
- WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
- WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
- WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
- WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
- WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
- WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
- WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
- WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
- WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
- WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
- WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
- WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
- WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
- WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
- WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
- WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
- WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
- WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
- WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
- WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
- WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
- WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
- WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
- WriteReg_32(0xE67F0018,0x00000001);
- WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+ mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+ mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
+ mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+ mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+ mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+ mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+ mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+ mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
+ mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
+ mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
+ mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+ mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
+ mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS90, 0x00000300);
+ mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0);
+ mmio_write_32(DBSC_DBSCHQOS92, 0x00000200);
+ mmio_write_32(DBSC_DBSCHQOS93, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+ mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+ mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+ mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+ mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
+ mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
+ mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
+ mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
+ mmio_write_32(0xE67F0018, 0x00000001);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
#endif
}
static void init_ddr_d3_1600(void)
{
- uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
+ uint32_t i, r2, r3, r5, r6, r7, r12;
+
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ mmio_write_32(DBSC_DBKIND, 0x00000007);
+ mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
+ mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
+ mmio_write_32(DBSC_DBTR0, 0x0000000B);
+ mmio_write_32(DBSC_DBTR1, 0x00000008);
+ mmio_write_32(DBSC_DBTR2, 0x00000000);
+ mmio_write_32(DBSC_DBTR3, 0x0000000B);
+ mmio_write_32(DBSC_DBTR4, 0x000B000B);
+ mmio_write_32(DBSC_DBTR5, 0x00000027);
+ mmio_write_32(DBSC_DBTR6, 0x0000001C);
+ mmio_write_32(DBSC_DBTR7, 0x00060006);
+ mmio_write_32(DBSC_DBTR8, 0x00000020);
+ mmio_write_32(DBSC_DBTR9, 0x00000006);
+ mmio_write_32(DBSC_DBTR10, 0x0000000C);
+ mmio_write_32(DBSC_DBTR11, 0x0000000A);
+ mmio_write_32(DBSC_DBTR12, 0x00120012);
+ mmio_write_32(DBSC_DBTR13, 0x000000D0);
+ mmio_write_32(DBSC_DBTR14, 0x00140005);
+ mmio_write_32(DBSC_DBTR15, 0x00050004);
+ mmio_write_32(DBSC_DBTR16, 0x071F0305);
+ mmio_write_32(DBSC_DBTR17, 0x040C0000);
+ mmio_write_32(DBSC_DBTR18, 0x00000200);
+ mmio_write_32(DBSC_DBTR19, 0x01000040);
+ mmio_write_32(DBSC_DBTR20, 0x020000D8);
+ mmio_write_32(DBSC_DBTR21, 0x00040004);
+ mmio_write_32(DBSC_DBBL, 0x00000000);
+ mmio_write_32(DBSC_DBODT0, 0x00000001);
+ mmio_write_32(DBSC_DBADJ0, 0x00000001);
+ mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+ mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+ mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
+ mmio_write_32(DBSC_SCFCTST0, 0x0D020C04);
+ mmio_write_32(DBSC_SCFCTST1, 0x0305040C);
+
+ mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBCMD, 0x01000001);
+ mmio_write_32(DBSC_DBCMD, 0x08000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
- WriteReg_32(DBSC_D3_DBKIND,0x00000007);
- WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
- WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
- WriteReg_32(DBSC_D3_DBTR0,0x0000000B);
- WriteReg_32(DBSC_D3_DBTR1,0x00000008);
- WriteReg_32(DBSC_D3_DBTR2,0x00000000);
- WriteReg_32(DBSC_D3_DBTR3,0x0000000B);
- WriteReg_32(DBSC_D3_DBTR4,0x000B000B);
- WriteReg_32(DBSC_D3_DBTR5,0x00000027);
- WriteReg_32(DBSC_D3_DBTR6,0x0000001C);
- WriteReg_32(DBSC_D3_DBTR7,0x00060006);
- WriteReg_32(DBSC_D3_DBTR8,0x00000020);
- WriteReg_32(DBSC_D3_DBTR9,0x00000006);
- WriteReg_32(DBSC_D3_DBTR10,0x0000000C);
- WriteReg_32(DBSC_D3_DBTR11,0x0000000A);
- WriteReg_32(DBSC_D3_DBTR12,0x00120012);
- WriteReg_32(DBSC_D3_DBTR13,0x000000D0);
- WriteReg_32(DBSC_D3_DBTR14,0x00140005);
- WriteReg_32(DBSC_D3_DBTR15,0x00050004);
- WriteReg_32(DBSC_D3_DBTR16,0x071F0305);
- WriteReg_32(DBSC_D3_DBTR17,0x040C0000);
- WriteReg_32(DBSC_D3_DBTR18,0x00000200);
- WriteReg_32(DBSC_D3_DBTR19,0x01000040);
- WriteReg_32(DBSC_D3_DBTR20,0x020000D8);
- WriteReg_32(DBSC_D3_DBTR21,0x00040004);
- WriteReg_32(DBSC_D3_DBBL,0x00000000);
- WriteReg_32(DBSC_D3_DBODT0,0x00000001);
- WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
- WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
- WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
- WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
- WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
- WriteReg_32(DBSC_D3_SCFCTST0,0x0D020C04);
- WriteReg_32(DBSC_D3_SCFCTST1,0x0305040C);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
- WriteReg_32(DBSC_D3_DBCMD,0x01000001);
- WriteReg_32(DBSC_D3_DBCMD,0x08000000);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x04058904);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058900);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGD0, 0x08C05FF0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
+ mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
+ mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
+ mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000098);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
+ mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
- while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x08C05FF0);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x2D9C0B66);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x2A88C400);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x30005200);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0014A9C9);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00000D70);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00000098);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
+ r3 = (r2 << 16) + (r2 << 8) + r2;
+ r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
+ mmio_write_32(DBSC_DBPDRGD0, r3);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
+ mmio_write_32(DBSC_DBPDRGD0, r3);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
+ mmio_write_32(DBSC_DBPDRGD0, r6);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
+ mmio_write_32(DBSC_DBPDRGD0, r6);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
+ mmio_write_32(DBSC_DBPDRGD0, r6);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
+ mmio_write_32(DBSC_DBPDRGD0, r6);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
+ mmio_write_32(DBSC_DBCMD, 0x08000001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
- RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
- RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
- RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
- WriteReg_32(DBSC_D3_DBCMD,0x08000001);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ for (i = 0; i < 2; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ if (r6 > 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
- for (uint32_t i = 0; i<2; i++)
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
- RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
- RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
- RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
- if ( RegVal_R6 > 0 )
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 |
+ ((r6 + (r5 << 1)) & 0xFF));
+ }
+ }
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
- } else
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
- }
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
- WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
+ r2 = mmio_read_32(DBSC_DBPDRGD0);
+ mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
+ r2 = mmio_read_32(DBSC_DBPDRGD0);
+ mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
- WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
- RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
- WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
- RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
- WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+ for (i = 0; i < 2; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ r12 = (r5 >> 0x2);
- for (uint32_t i = 0; i < 2; i++)
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
- RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
- RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
+ if (r12 < r6) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
- RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
- RegVal_R12 = (RegVal_R5 >> 0x2);
- if ( RegVal_R12 < RegVal_R6 )
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 |
+ ((r6 + r5 +
+ (r5 >> 1) + r12) & 0xFF));
+ }
+ }
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
- }
- else
- {
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
- WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
- }
- }
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
- while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
- while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
- WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
- WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ ;
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
- WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
- WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
- WriteReg_32(DBSC_D3_DBRFCNF1,0x00080C30);
- WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
- WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
- WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
- WriteReg_32(DBSC_D3_DBACEN,0x00000001);
- WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
- WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+ mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
+ mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
+ mmio_write_32(DBSC_DBRFCNF1, 0x00080C30);
+ mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+ mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+ mmio_write_32(DBSC_DBRFEN, 0x00000001);
+ mmio_write_32(DBSC_DBACEN, 0x00000001);
+ mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
#ifdef ddr_qos_init_setting // only for non qos_init
- WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
- WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
- WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
- WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
- WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
- WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
- WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
- WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
- WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
- WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
- WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
- WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
- WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
- WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
- WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
- WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
- WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
- WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
- WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
- WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
- WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
- WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
- WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
- WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
- WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
- WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
- WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
- WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
- WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
- WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
- WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
- WriteReg_32(0xE67F0018,0x00000001);
- WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+ mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+ mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
+ mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+ mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+ mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+ mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+ mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+ mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
+ mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
+ mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
+ mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+ mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
+ mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS90, 0x00000300);
+ mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0);
+ mmio_write_32(DBSC_DBSCHQOS92, 0x00000200);
+ mmio_write_32(DBSC_DBSCHQOS93, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+ mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+ mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+ mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+ mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
+ mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
+ mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
+ mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
+ mmio_write_32(0xE67F0018, 0x00000001);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
#endif
}
-#define PRR (0xFFF00044U)
-#define PRR_PRODUCT_MASK (0x00007F00U)
-#define PRR_PRODUCT_D3 (0x00005800U)
+#define PRR 0xFFF00044U
+#define PRR_PRODUCT_MASK 0x00007F00U
+#define PRR_PRODUCT_D3 0x00005800U
-#define RST_MODEMR (0xE6160060)
-#define MODEMR_MD19 (0x00080000U)
+#define MODEMR_MD19 BIT(19)
int32_t rcar_dram_init(void)
{
@@ -669,15 +678,14 @@
uint32_t ddr_mbps;
reg = mmio_read_32(PRR);
-
- if (PRR_PRODUCT_D3 != (reg & PRR_PRODUCT_MASK)) {
+ if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_D3) {
ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n",
reg);
panic();
}
reg = mmio_read_32(RST_MODEMR);
- if (MODEMR_MD19 == (reg & MODEMR_MD19)) {
+ if (reg & MODEMR_MD19) {
init_ddr_d3_1866();
ddr_mbps = 1866;
} else {
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
index c289c88..7aedc88 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
@@ -1,1703 +1,1711 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <lib/mmio.h>
#include <stdint.h>
#include <common/debug.h>
-#include "boot_init_dram_regdef_e3.h"
-#include "ddr_init_e3.h"
+#include "boot_init_dram.h"
+#include "boot_init_dram_regdef.h"
#include "../dram_sub_func.h"
-/* rev.0.04 add variables */
-/*******************************************************************************
- * variables
- ******************************************************************************/
-uint32_t ddrBackup;
+#define RCAR_E3_DDR_VERSION "rev.0.12"
-/* rev.0.03 add Prototypes */
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/* static uint32_t init_ddr(void); rev.0.04 */
-/* static uint32_t recovery_from_backup_mode(void); rev.0.04 */
-/* int32_t dram_update_boot_status(uint32_t status); rev.0.04 */
-
-/* rev.0.03 add Comment */
-/*******************************************************************************
- * register write/read function
- ******************************************************************************/
-static void WriteReg_32(uint32_t a, uint32_t v)
-{
- (*(volatile uint32_t*)(uintptr_t)a) = v;
-} /* WriteReg_32 */
-
-static uint32_t ReadReg_32(uint32_t a)
-{
- uint32_t w = (*(volatile uint32_t*)(uintptr_t)a);
- return w;
-} /* ReadReg_32 */
+/* Average periodic refresh interval[ns]. Support 3900,7800 */
+#ifdef ddr_qos_init_setting
+#define REFRESH_RATE 3900U
+#else
+#if RCAR_REF_INT == 1
+#define REFRESH_RATE 7800U
+#else
+#define REFRESH_RATE 3900U
+#endif
+#endif
-/* rev.0.04 add Comment */
-/*******************************************************************************
+/*
* Initialize ddr
- ******************************************************************************/
+ */
uint32_t init_ddr(void)
{
- uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
- uint32_t ddr_md;
+ uint32_t i, r2, r5, r6, r7, r12;
+ uint32_t ddr_md;
+ uint32_t regval, j;
+ uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4;
+ uint32_t bdlcount_0c_div8, bdlcount_0c_div16;
+ uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
+ uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
+ uint32_t pdr_ctl;
+ uint32_t byp_ctl;
-/* rev.0.08 */
- uint32_t RegVal, j;
- uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
- uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
- uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
-/* rev.0.10 */
- uint32_t pdr_ctl;
-/* rev.0.11 */
- uint32_t byp_ctl;
+ if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
+ pdqsr_ctl = 1;
+ lcdl_ctl = 1;
+ pdr_ctl = 1;
+ byp_ctl = 1;
+ } else {
+ pdqsr_ctl = 0;
+ lcdl_ctl = 0;
+ pdr_ctl = 0;
+ byp_ctl = 0;
+ }
-/* rev.0.08 */
- if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
- pdqsr_ctl = 1;
- lcdl_ctl = 1;
- pdr_ctl = 1; /* rev.0.10 */
- byp_ctl = 1; /* rev.0.11 */
- } else {
- pdqsr_ctl = 0;
- lcdl_ctl = 0;
- pdr_ctl = 0; /* rev.0.10 */
- byp_ctl = 0; /* rev.0.11 */
- }
+ /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
+ ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0);
- /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
- ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0;
+ /* 1584Mbps setting */
+ if (ddr_md == 0) {
+ mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF);
+ mmio_write_32(CPG_CPGWPCR, 0xA5A50000);
- /* 1584Mbps setting */
- if (ddr_md == 0) {
- /* CPG setting ===============================================*/
- WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF);
- WriteReg_32(CPG_CPGWPCR, 0xA5A50000);
+ mmio_write_32(CPG_SRCR4, 0x20000000);
- WriteReg_32(CPG_SRCR4, 0x20000000);
+ mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */
+ while (!(mmio_read_32(CPG_PLLECR) & BIT(11)))
+ ;
- WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */
- while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0);
+ mmio_write_32(CPG_SRSTCLR4, 0x20000000);
- WriteReg_32(CPG_SRSTCLR4, 0x20000000);
+ mmio_write_32(CPG_CPGWPCR, 0xA5A50001);
+ }
- WriteReg_32(CPG_CPGWPCR, 0xA5A50001);
-
- /* CPG setting ===============================================*/
- } /* ddr_md */
-
- WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
- WriteReg_32(DBSC_E3_DBKIND, 0x00000007);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ mmio_write_32(DBSC_DBKIND, 0x00000007);
#if RCAR_DRAM_DDR3L_MEMCONF == 0
- WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /* 1GB */
-#elif RCAR_DRAM_DDR3L_MEMCONF == 1
- WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */
-#elif RCAR_DRAM_DDR3L_MEMCONF == 2
- WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); /* 4GB */
+ mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); /* 1GB */
#else
- WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB */
+ mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); /* 2GB(default) */
#endif
#if RCAR_DRAM_DDR3L_MEMDUAL == 1
- RegVal_R2 = (ReadReg_32(0xE6790614));
- WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
+ r2 = mmio_read_32(0xE6790614);
+ mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */
#endif
+ mmio_write_32(DBSC_DBPHYCONF0, 0x1);
- WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001);
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBTR0, 0xB);
+ mmio_write_32(DBSC_DBTR1, 0x8);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBTR0, 0xD);
+ mmio_write_32(DBSC_DBTR1, 0x9);
+ }
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBTR0, 0x0000000B);
- WriteReg_32(DBSC_E3_DBTR1, 0x00000008);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBTR0, 0x0000000D);
- WriteReg_32(DBSC_E3_DBTR1, 0x00000009);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBTR2, 0x00000000);
- WriteReg_32(DBSC_E3_DBTR2, 0x00000000);
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBTR3, 0x0000000B);
+ mmio_write_32(DBSC_DBTR4, 0x000B000B);
+ mmio_write_32(DBSC_DBTR5, 0x00000027);
+ mmio_write_32(DBSC_DBTR6, 0x0000001C);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBTR3, 0x0000000D);
+ mmio_write_32(DBSC_DBTR4, 0x000D000D);
+ mmio_write_32(DBSC_DBTR5, 0x0000002D);
+ mmio_write_32(DBSC_DBTR6, 0x00000020);
+ }
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBTR3, 0x0000000B);
- WriteReg_32(DBSC_E3_DBTR4, 0x000B000B);
- WriteReg_32(DBSC_E3_DBTR5, 0x00000027);
- WriteReg_32(DBSC_E3_DBTR6, 0x0000001C);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBTR3, 0x0000000D);
- WriteReg_32(DBSC_E3_DBTR4, 0x000D000D);
- WriteReg_32(DBSC_E3_DBTR5, 0x0000002D);
- WriteReg_32(DBSC_E3_DBTR6, 0x00000020);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBTR7, 0x00060006);
- WriteReg_32(DBSC_E3_DBTR7, 0x00060006);
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBTR8, 0x00000020);
+ mmio_write_32(DBSC_DBTR9, 0x00000006);
+ mmio_write_32(DBSC_DBTR10, 0x0000000C);
+ mmio_write_32(DBSC_DBTR11, 0x0000000A);
+ mmio_write_32(DBSC_DBTR12, 0x00120012);
+ mmio_write_32(DBSC_DBTR13, 0x000000CE);
+ mmio_write_32(DBSC_DBTR14, 0x00140005);
+ mmio_write_32(DBSC_DBTR15, 0x00050004);
+ mmio_write_32(DBSC_DBTR16, 0x071F0305);
+ mmio_write_32(DBSC_DBTR17, 0x040C0000);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBTR8, 0x00000021);
+ mmio_write_32(DBSC_DBTR9, 0x00000007);
+ mmio_write_32(DBSC_DBTR10, 0x0000000E);
+ mmio_write_32(DBSC_DBTR11, 0x0000000C);
+ mmio_write_32(DBSC_DBTR12, 0x00140014);
+ mmio_write_32(DBSC_DBTR13, 0x000000F2);
+ mmio_write_32(DBSC_DBTR14, 0x00170006);
+ mmio_write_32(DBSC_DBTR15, 0x00060005);
+ mmio_write_32(DBSC_DBTR16, 0x09210507);
+ mmio_write_32(DBSC_DBTR17, 0x040E0000);
+ }
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBTR8, 0x00000020);
- WriteReg_32(DBSC_E3_DBTR9, 0x00000006);
- WriteReg_32(DBSC_E3_DBTR10, 0x0000000C);
- WriteReg_32(DBSC_E3_DBTR11, 0x0000000A);
- WriteReg_32(DBSC_E3_DBTR12, 0x00120012);
- WriteReg_32(DBSC_E3_DBTR13, 0x000000CE);
- WriteReg_32(DBSC_E3_DBTR14, 0x00140005);
- WriteReg_32(DBSC_E3_DBTR15, 0x00050004);
- WriteReg_32(DBSC_E3_DBTR16, 0x071F0305);
- WriteReg_32(DBSC_E3_DBTR17, 0x040C0000);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBTR8, 0x00000021);
- WriteReg_32(DBSC_E3_DBTR9, 0x00000007);
- WriteReg_32(DBSC_E3_DBTR10, 0x0000000E);
- WriteReg_32(DBSC_E3_DBTR11, 0x0000000C);
- WriteReg_32(DBSC_E3_DBTR12, 0x00140014);
- WriteReg_32(DBSC_E3_DBTR13, 0x000000F2);
- WriteReg_32(DBSC_E3_DBTR14, 0x00170006);
- WriteReg_32(DBSC_E3_DBTR15, 0x00060005);
- WriteReg_32(DBSC_E3_DBTR16, 0x09210507);
- WriteReg_32(DBSC_E3_DBTR17, 0x040E0000);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBTR18, 0x00000200);
- WriteReg_32(DBSC_E3_DBTR18, 0x00000200);
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBTR19, 0x01000040);
+ mmio_write_32(DBSC_DBTR20, 0x020000D6);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBTR19, 0x0129004B);
+ mmio_write_32(DBSC_DBTR20, 0x020000FB);
+ }
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBTR19, 0x01000040);
- WriteReg_32(DBSC_E3_DBTR20, 0x020000D6);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBTR19, 0x0129004B);
- WriteReg_32(DBSC_E3_DBTR20, 0x020000FB);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBTR21, 0x00040004);
+ mmio_write_32(DBSC_DBBL, 0x00000000);
+ mmio_write_32(DBSC_DBODT0, 0x00000001);
+ mmio_write_32(DBSC_DBADJ0, 0x00000001);
+ mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+ mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+ mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
- WriteReg_32(DBSC_E3_DBTR21, 0x00040004);
- WriteReg_32(DBSC_E3_DBBL, 0x00000000);
- WriteReg_32(DBSC_E3_DBODT0, 0x00000001);
- WriteReg_32(DBSC_E3_DBADJ0, 0x00000001);
- WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002);
- WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010);
- WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001);
- WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046);
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_SCFCTST0, 0x0D050B03);
+ mmio_write_32(DBSC_SCFCTST1, 0x0306030C);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_SCFCTST0, 0x0C050B03);
+ mmio_write_32(DBSC_SCFCTST1, 0x0305030C);
+ }
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03);
- WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03);
- WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C);
- } /* ddr_md */
+ /*
+ * Initial_Step0( INITBYP )
+ */
+ mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBCMD, 0x01840001);
+ mmio_write_32(DBSC_DBCMD, 0x08840000);
+ NOTICE("BL2: [COLD_BOOT]\n");
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- /* rev.0.03 add Comment */
- /****************************************************************************
- * Initial_Step0( INITBYP )
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A);
- WriteReg_32(DBSC_E3_DBCMD, 0x01840001);
- WriteReg_32(DBSC_E3_DBCMD, 0x08840000);
- NOTICE("BL2: [COLD_BOOT]\n"); /* rev.0.11 */
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /*
+ * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
+ */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- /* rev.0.03 add Comment */
- /****************************************************************************
- * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058A04);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058904);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A04);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /*
+ * Initial_Step2( DRAMRST/DRAMINT training )
+ */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- /* rev.0.03 add Comment */
- /****************************************************************************
- * Initial_Step2( DRAMRST/DRAMINT training )
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ if (byp_ctl == 1)
+ mmio_write_32(DBSC_DBPDRGD0, 0x0780C720);
+ else
+ mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
- if (byp_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720);
- } else {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700);
- }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
- while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) -
+ 400 + 0x08B00000);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) -
+ 400 + 0x0A300000);
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- if (REFRESH_RATE > 3900) {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */
- } else {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */
- }
- } else { /* 1856Mbps */
- if (REFRESH_RATE > 3900) {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */
- } else {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */
- } /* REFRESH_RATE */
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ if (REFRESH_RATE > 3900) /* [7]SRT=0 */
+ mmio_write_32(DBSC_DBPDRGD0, 0x18);
+ else /* [7]SRT=1 */
+ mmio_write_32(DBSC_DBPDRGD0, 0x98);
+ } else { /* 1856Mbps */
+ if (REFRESH_RATE > 3900) /* [7]SRT=0 */
+ mmio_write_32(DBSC_DBPDRGD0, 0x20);
+ else /* [7]SRT=1 */
+ mmio_write_32(DBSC_DBPDRGD0, 0xA0);
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
+ mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010181);
- WriteReg_32(DBSC_E3_DBCMD, 0x08840001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
+ mmio_write_32(DBSC_DBCMD, 0x08840001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- /* rev.0.03 add Comment */
- /****************************************************************************
- * Initial_Step3( WL/QSG training )
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010601);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /*
+ * Initial_Step3( WL/QSG training )
+ */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- for (i = 0; i < 4; i++) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
- RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
- RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
- RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
- if (RegVal_R6 > 0) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6);
- } else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
- } /* RegVal_R6 */
- } /* for i */
+ for (i = 0; i < 4; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
- /* rev.0.10 move Comment */
- /****************************************************************************
- * Initial_Step4( WLADJ training )
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0);
+ if (r6 > 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 |
+ ((r6 + ((r5) << 1)) &
+ 0xFF));
+ }
+ }
- /* rev.0.08 */
- if (pdqsr_ctl == 1){} else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- }
+ /*
+ * Initial_Step4( WLADJ training )
+ */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
- /* PDR always off */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- }
+ if (pdqsr_ctl == 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /* PDR always off */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ }
- /****************************************************************************
- * Initial_Step5(Read Data Bit Deskew)
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- /* rev.0.08 */
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /*
+ * Initial_Step5(Read Data Bit Deskew)
+ */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
-if (pdqsr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-}
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00011001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- /* PDR dynamic */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- }
+ if (pdqsr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
- /****************************************************************************
- * Initial_Step6(Write Data Bit Deskew)
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /* PDR dynamic */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ }
- /****************************************************************************
- * Initial_Step7(Read Data Eye Training)
- ***************************************************************************/
-if (pdqsr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-}
+ /*
+ * Initial_Step6(Write Data Bit Deskew)
+ */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00012001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- /* PDR always off */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- }
+ /*
+ * Initial_Step7(Read Data Eye Training)
+ */
+ if (pdqsr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /* PDR always off */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ }
-if (pdqsr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-}
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00014001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- /* PDR dynamic */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- }
+ if (pdqsr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
- /****************************************************************************
- * Initial_Step8(Write Data Eye Training)
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /* PDR dynamic */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ }
- /* rev.0.03 add Comment */
- /****************************************************************************
- * Initial_Step3_2( DQS Gate Training )
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /*
+ * Initial_Step8(Write Data Eye Training)
+ */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00018001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- for (i = 0; i < 4; i++) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
- RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
- RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
- RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
- RegVal_R12 = (RegVal_R5 >> 0x2);
- if (RegVal_R12 < RegVal_R6) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
- } else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
- } /* RegVal_R12 < RegVal_R6 */
- } /* for i */
+ /*
+ * Initial_Step3_2( DQS Gate Training )
+ */
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- /* rev.0.10 move Comment */
- /****************************************************************************
- * Initial_Step5-2_7-2( Rd bit Rd eye )
- ***************************************************************************/
-/* rev.0.08 */
- if (pdqsr_ctl == 1){} else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- }
+ for (i = 0; i < 4; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ r12 = (r5 >> 0x2);
+ if (r12 < r6) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 + r5 +
+ (r5 >> 1) + r12) & 0xFF));
+ }
+ }
- /* PDR always off */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- }
+ /*
+ * Initial_Step5-2_7-2( Rd bit Rd eye )
+ */
+ if (pdqsr_ctl == 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /* PDR always off */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ }
-/* rev.0.08 */
- if (lcdl_ctl == 1) {
- for (i = 0; i < 4; i++) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
- bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
- bdlcount_0c_div2 = (bdlcount_0c >> 1);
- bdlcount_0c_div4 = (bdlcount_0c >> 2);
- bdlcount_0c_div8 = (bdlcount_0c >> 3);
- bdlcount_0c_div16 = (bdlcount_0c >> 4);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- if (ddr_md == 0) { /* 1584Mbps */
- lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8;
- lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16;
- } else { /* 1856Mbps */
- lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4;
- lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4;
- } /* ddr_md */
+ if (lcdl_ctl == 1) {
+ for (i = 0; i < 4; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >>
+ 8;
+ bdlcount_0c_div2 = bdlcount_0c >> 1;
+ bdlcount_0c_div4 = bdlcount_0c >> 2;
+ bdlcount_0c_div8 = bdlcount_0c >> 3;
+ bdlcount_0c_div16 = bdlcount_0c >> 4;
- if (dqsgd_0c > lcdl_judge1) {
- if (dqsgd_0c <= lcdl_judge2) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
- } else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
- rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
- rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
- rbd_0c[0] = (RegVal) &0x0000001f;
- rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
- rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
- rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
- for (j = 0; j < 4; j++) {
- rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
- if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
- RegVal = RegVal | (rbd_0c[j] << 8 * j);
- }
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
- rbd_0c[0] = (RegVal) &0x0000001f;
- rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
- rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
- rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
- for (j = 0; j < 4; j++) {
- rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
- if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
- RegVal = RegVal | (rbd_0c[j] << 8 * j);
- }
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
- }
- }
- }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37);
- }
+ if (ddr_md == 0) { /* 1584Mbps */
+ lcdl_judge1 = bdlcount_0c_div2 +
+ bdlcount_0c_div4 +
+ bdlcount_0c_div8;
+ lcdl_judge2 = bdlcount_0c +
+ bdlcount_0c_div4 +
+ bdlcount_0c_div16;
+ } else { /* 1856Mbps */
+ lcdl_judge1 = bdlcount_0c_div2 +
+ bdlcount_0c_div4;
+ lcdl_judge2 = bdlcount_0c +
+ bdlcount_0c_div4;
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
- if (byp_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720);
- } else {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700);
- }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
- while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0);
+ if (dqsgd_0c <= lcdl_judge1)
+ continue;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E);
+ if (dqsgd_0c <= lcdl_judge2) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGD0,
+ (dqsgd_0c - bdlcount_0c_div8) |
+ regval);
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGD0, regval);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGD0, regval |
+ (gatesl_0c + 1));
+ mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD0));
+ rdqsd_0c = (regval & 0xFF00) >> 8;
+ rdqsnd_0c = (regval & 0xFF0000) >> 16;
+ mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0,
+ (regval & 0xFF0000FF) |
+ ((rdqsd_0c +
+ bdlcount_0c_div4) << 8) |
+ ((rdqsnd_0c +
+ bdlcount_0c_div4) << 16));
+ mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD0));
+ rbd_0c[0] = (regval) & 0x1f;
+ rbd_0c[1] = (regval >> 8) & 0x1f;
+ rbd_0c[2] = (regval >> 16) & 0x1f;
+ rbd_0c[3] = (regval >> 24) & 0x1f;
+ mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xE0E0E0E0;
+ for (j = 0; j < 4; j++) {
+ rbd_0c[j] = rbd_0c[j] +
+ bdlcount_0c_div4;
+ if (rbd_0c[j] > 0x1F)
+ rbd_0c[j] = 0x1F;
+ regval = regval | (rbd_0c[j] << 8 * j);
+ }
+ mmio_write_32(DBSC_DBPDRGD0, regval);
+ mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD0));
+ rbd_0c[0] = (regval) & 0x1f;
+ rbd_0c[1] = (regval >> 8) & 0x1f;
+ rbd_0c[2] = (regval >> 16) & 0x1f;
+ rbd_0c[3] = (regval >> 24) & 0x1f;
+ mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xE0E0E0E0;
+ for (j = 0; j < 4; j++) {
+ rbd_0c[j] = rbd_0c[j] +
+ bdlcount_0c_div4;
+ if (rbd_0c[j] > 0x1F)
+ rbd_0c[j] = 0x1F;
+ regval = regval | (rbd_0c[j] << 8 * j);
+ }
+ mmio_write_32(DBSC_DBPDRGD0, regval);
+ }
+ }
+ mmio_write_32(DBSC_DBPDRGA0, 0x2);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7D81E37);
+ }
- WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010);
- WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ if (byp_ctl == 1)
+ mmio_write_32(DBSC_DBPDRGD0, 0x0380C720);
+ else
+ mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
- WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000);
- WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001);
- WriteReg_32(DBSC_E3_DBRFEN, 0x00000001);
- WriteReg_32(DBSC_E3_DBACEN, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ ;
-/* rev.0.08 */
- if (pdqsr_ctl == 1) {
- WriteReg_32(0xE67F0018, 0x00000001);
- RegVal = ReadReg_32(0x40000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
- /* PDR dynamic */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- }
+ mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
+ mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000);
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBRFCNF1,
+ (REFRESH_RATE * 99 / 125) + 0x00080000);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBRFCNF1,
+ (REFRESH_RATE * 116 / 125) + 0x00080000);
+ }
- /* rev.0.03 add Comment */
- /****************************************************************************
- * Initial_Step9( Initial End )
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000);
- WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
+ mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+ mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+ mmio_write_32(DBSC_DBRFEN, 0x00000001);
+ mmio_write_32(DBSC_DBACEN, 0x00000001);
-#ifdef ddr_qos_init_setting /* only for non qos_init */
- WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
- WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218);
- WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4);
- WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037);
- WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001);
- WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111);
- WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123);
- WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00);
- WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00);
- WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000);
- WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000);
- WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300);
- WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0);
- WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200);
- WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100);
- WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100);
- WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0);
- WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0);
- WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040);
- WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100);
- WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0);
- WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0);
- WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040);
- WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0);
- WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0);
- WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080);
- WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040);
- WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040);
- WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030);
- WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020);
- WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010);
+ if (pdqsr_ctl == 1) {
+ mmio_write_32(0xE67F0018, 0x00000001);
+ regval = mmio_read_32(0x40000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGD0, regval);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
-/* rev.0.08 */
- if (pdqsr_ctl == 1){} else {
- WriteReg_32(0xE67F0018, 0x00000001);
- }
+ /* PDR dynamic */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ }
- WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
-#endif
+ /*
+ * Initial_Step9( Initial End )
+ */
+ mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
- return 1; /* rev.0.04 Restore the return code */
+#ifdef ddr_qos_init_setting /* only for non qos_init */
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+ mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+ mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
+ mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+ mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+ mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+ mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+ mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+ mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
+ mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
+ mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
+ mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+ mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
+ mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS90, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0);
+ mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0);
+ mmio_write_32(DBSC_DBSCHQOS93, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+ mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+ mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+ mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+ mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
+ mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
+ mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
+ mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
-} /* init_ddr */
+ if (pdqsr_ctl == 0)
+ mmio_write_32(0xE67F0018, 0x00000001);
-/* rev.0.04 add function */
-uint32_t recovery_from_backup_mode(void)
-{
- /****************************************************************************
- * recovery_Step0(DBSC Setting 1) / same "init_ddr"
- ***************************************************************************/
- uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
- uint32_t ddr_md;
- uint32_t err;
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+#endif
-/* rev.0.08 */
- uint32_t RegVal, j;
- uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
- uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
- uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
- /* rev.0.10 */
- uint32_t pdr_ctl;
- /* rev.0.11 */
- uint32_t byp_ctl;
+ return 1;
+}
-/* rev.0.08 */
- if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
- pdqsr_ctl = 1;
- lcdl_ctl = 1;
- pdr_ctl = 1; /* rev.0.10 */
- byp_ctl = 1; /* rev.0.11 */
- } else {
- pdqsr_ctl = 0;
- lcdl_ctl = 0;
- pdr_ctl = 0; /* rev.0.10 */
- byp_ctl = 0; /* rev.0.11 */
- }
+static uint32_t recovery_from_backup_mode(uint32_t ddr_backup)
+{
+ /*
+ * recovery_Step0(DBSC Setting 1) / same "init_ddr"
+ */
+ uint32_t r2, r5, r6, r7, r12, i;
+ uint32_t ddr_md;
+ uint32_t err;
+ uint32_t regval, j;
+ uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4;
+ uint32_t bdlcount_0c_div8, bdlcount_0c_div16;
+ uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
+ uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
+ uint32_t pdr_ctl;
+ uint32_t byp_ctl;
- /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
- ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0;
+ if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
+ pdqsr_ctl = 1;
+ lcdl_ctl = 1;
+ pdr_ctl = 1;
+ byp_ctl = 1;
+ } else {
+ pdqsr_ctl = 0;
+ lcdl_ctl = 0;
+ pdr_ctl = 0;
+ byp_ctl = 0;
+ }
- /* 1584Mbps setting */
- if (ddr_md == 0) {
- /* CPG setting ===============================================*/
- WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF);
- WriteReg_32(CPG_CPGWPCR, 0xA5A50000);
+ /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
+ ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0);
- WriteReg_32(CPG_SRCR4, 0x20000000);
+ /* 1584Mbps setting */
+ if (ddr_md == 0) {
+ mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF);
+ mmio_write_32(CPG_CPGWPCR, 0xA5A50000);
- WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */
- while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0);
+ mmio_write_32(CPG_SRCR4, 0x20000000);
- WriteReg_32(CPG_SRSTCLR4, 0x20000000);
+ mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */
+ while (!(mmio_read_32(CPG_PLLECR) & BIT(11)))
+ ;
- WriteReg_32(CPG_CPGWPCR, 0xA5A50001);
+ mmio_write_32(CPG_SRSTCLR4, 0x20000000);
- /* CPG setting ===============================================*/
- } /* ddr_md */
+ mmio_write_32(CPG_CPGWPCR, 0xA5A50001);
+ }
- WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
- WriteReg_32(DBSC_E3_DBKIND, 0x00000007);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ mmio_write_32(DBSC_DBKIND, 0x00000007);
#if RCAR_DRAM_DDR3L_MEMCONF == 0
- WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02);
-#elif RCAR_DRAM_DDR3L_MEMCONF == 1
- WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
-#elif RCAR_DRAM_DDR3L_MEMCONF == 2
- WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02);
+ mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02);
#else
- WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
+ mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02);
#endif
-/* rev.0.08 */
#if RCAR_DRAM_DDR3L_MEMDUAL == 1
- RegVal_R2 = (ReadReg_32(0xE6790614));
- WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
+ r2 = mmio_read_32(0xE6790614);
+ mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */
#endif
- WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001);
+ mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBTR0, 0x0000000B);
- WriteReg_32(DBSC_E3_DBTR1, 0x00000008);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBTR0, 0x0000000D);
- WriteReg_32(DBSC_E3_DBTR1, 0x00000009);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBTR0, 0x0000000B);
+ mmio_write_32(DBSC_DBTR1, 0x00000008);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBTR0, 0x0000000D);
+ mmio_write_32(DBSC_DBTR1, 0x00000009);
+ }
- WriteReg_32(DBSC_E3_DBTR2, 0x00000000);
+ mmio_write_32(DBSC_DBTR2, 0x00000000);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBTR3, 0x0000000B);
- WriteReg_32(DBSC_E3_DBTR4, 0x000B000B);
- WriteReg_32(DBSC_E3_DBTR5, 0x00000027);
- WriteReg_32(DBSC_E3_DBTR6, 0x0000001C);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBTR3, 0x0000000D);
- WriteReg_32(DBSC_E3_DBTR4, 0x000D000D);
- WriteReg_32(DBSC_E3_DBTR5, 0x0000002D);
- WriteReg_32(DBSC_E3_DBTR6, 0x00000020);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBTR3, 0x0000000B);
+ mmio_write_32(DBSC_DBTR4, 0x000B000B);
+ mmio_write_32(DBSC_DBTR5, 0x00000027);
+ mmio_write_32(DBSC_DBTR6, 0x0000001C);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBTR3, 0x0000000D);
+ mmio_write_32(DBSC_DBTR4, 0x000D000D);
+ mmio_write_32(DBSC_DBTR5, 0x0000002D);
+ mmio_write_32(DBSC_DBTR6, 0x00000020);
+ }
- WriteReg_32(DBSC_E3_DBTR7, 0x00060006);
+ mmio_write_32(DBSC_DBTR7, 0x00060006);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBTR8, 0x00000020);
- WriteReg_32(DBSC_E3_DBTR9, 0x00000006);
- WriteReg_32(DBSC_E3_DBTR10, 0x0000000C);
- WriteReg_32(DBSC_E3_DBTR11, 0x0000000A);
- WriteReg_32(DBSC_E3_DBTR12, 0x00120012);
- WriteReg_32(DBSC_E3_DBTR13, 0x000000CE);
- WriteReg_32(DBSC_E3_DBTR14, 0x00140005);
- WriteReg_32(DBSC_E3_DBTR15, 0x00050004);
- WriteReg_32(DBSC_E3_DBTR16, 0x071F0305);
- WriteReg_32(DBSC_E3_DBTR17, 0x040C0000);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBTR8, 0x00000021);
- WriteReg_32(DBSC_E3_DBTR9, 0x00000007);
- WriteReg_32(DBSC_E3_DBTR10, 0x0000000E);
- WriteReg_32(DBSC_E3_DBTR11, 0x0000000C);
- WriteReg_32(DBSC_E3_DBTR12, 0x00140014);
- WriteReg_32(DBSC_E3_DBTR13, 0x000000F2);
- WriteReg_32(DBSC_E3_DBTR14, 0x00170006);
- WriteReg_32(DBSC_E3_DBTR15, 0x00060005);
- WriteReg_32(DBSC_E3_DBTR16, 0x09210507);
- WriteReg_32(DBSC_E3_DBTR17, 0x040E0000);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBTR8, 0x00000020);
+ mmio_write_32(DBSC_DBTR9, 0x00000006);
+ mmio_write_32(DBSC_DBTR10, 0x0000000C);
+ mmio_write_32(DBSC_DBTR11, 0x0000000A);
+ mmio_write_32(DBSC_DBTR12, 0x00120012);
+ mmio_write_32(DBSC_DBTR13, 0x000000CE);
+ mmio_write_32(DBSC_DBTR14, 0x00140005);
+ mmio_write_32(DBSC_DBTR15, 0x00050004);
+ mmio_write_32(DBSC_DBTR16, 0x071F0305);
+ mmio_write_32(DBSC_DBTR17, 0x040C0000);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBTR8, 0x00000021);
+ mmio_write_32(DBSC_DBTR9, 0x00000007);
+ mmio_write_32(DBSC_DBTR10, 0x0000000E);
+ mmio_write_32(DBSC_DBTR11, 0x0000000C);
+ mmio_write_32(DBSC_DBTR12, 0x00140014);
+ mmio_write_32(DBSC_DBTR13, 0x000000F2);
+ mmio_write_32(DBSC_DBTR14, 0x00170006);
+ mmio_write_32(DBSC_DBTR15, 0x00060005);
+ mmio_write_32(DBSC_DBTR16, 0x09210507);
+ mmio_write_32(DBSC_DBTR17, 0x040E0000);
+ }
- WriteReg_32(DBSC_E3_DBTR18, 0x00000200);
+ mmio_write_32(DBSC_DBTR18, 0x00000200);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBTR19, 0x01000040);
- WriteReg_32(DBSC_E3_DBTR20, 0x020000D6);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBTR19, 0x0129004B);
- WriteReg_32(DBSC_E3_DBTR20, 0x020000FB);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBTR19, 0x01000040);
+ mmio_write_32(DBSC_DBTR20, 0x020000D6);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBTR19, 0x0129004B);
+ mmio_write_32(DBSC_DBTR20, 0x020000FB);
+ }
- WriteReg_32(DBSC_E3_DBTR21, 0x00040004);
- WriteReg_32(DBSC_E3_DBBL, 0x00000000);
- WriteReg_32(DBSC_E3_DBODT0, 0x00000001);
- WriteReg_32(DBSC_E3_DBADJ0, 0x00000001);
- WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002);
- WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010);
- WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001);
- WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046);
+ mmio_write_32(DBSC_DBTR21, 0x00040004);
+ mmio_write_32(DBSC_DBBL, 0x00000000);
+ mmio_write_32(DBSC_DBODT0, 0x00000001);
+ mmio_write_32(DBSC_DBADJ0, 0x00000001);
+ mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+ mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+ mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03);
- WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03);
- WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_SCFCTST0, 0x0D050B03);
+ mmio_write_32(DBSC_SCFCTST1, 0x0306030C);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_SCFCTST0, 0x0C050B03);
+ mmio_write_32(DBSC_SCFCTST1, 0x0305030C);
+ }
- /****************************************************************************
- * recovery_Step1(PHY setting 1)
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A);
- WriteReg_32(DBSC_E3_DBCMD, 0x01840001);
- WriteReg_32(DBSC_E3_DBCMD, 0x0A840000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); /* DDR_PLLCR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */
- if (byp_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720);
- } else {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700);
- }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); /* DDR_DXCCR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
- while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /*
+ * recovery_Step1(PHY setting 1)
+ */
+ mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBCMD, 0x01840001);
+ mmio_write_32(DBSC_DBCMD, 0x0A840000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000008); /* DDR_PLLCR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */
+ if (byp_ctl == 1)
+ mmio_write_32(DBSC_DBPDRGD0, 0x0780C720);
+ else
+ mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000020); /* DDR_DXCCR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */
+ mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ ;
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023);
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) -
+ 400 + 0x08B00000);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) -
+ 400 + 0x0A300000);
+ }
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- if (REFRESH_RATE > 3900) {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */
- } else {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */
- }
- } else { /* 1856Mbps */
- if (REFRESH_RATE > 3900) {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */
- } else {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */
- } /* REFRESH_RATE */
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); /* DDR_DSGCR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ if (REFRESH_RATE > 3900)
+ mmio_write_32(DBSC_DBPDRGD0, 0x18); /* [7]SRT=0 */
+ else
+ mmio_write_32(DBSC_DBPDRGD0, 0x98); /* [7]SRT=1 */
+ } else { /* 1856Mbps */
+ if (REFRESH_RATE > 3900)
+ mmio_write_32(DBSC_DBPDRGD0, 0x20); /* [7]SRT=0 */
+ else
+ mmio_write_32(DBSC_DBPDRGD0, 0xA0); /* [7]SRT=1 */
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x40010000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021); /* DDR_DSGCR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x40010000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0xC4285FBF);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */
+ mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */
+ mmio_write_32(DBSC_DBPDRGD0, 0xC4285FBF);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */
+ mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00050001);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x00050001);
- /* ddr backupmode end */
- if (ddrBackup) {
- NOTICE("BL2: [WARM_BOOT]\n");
- } else {
- NOTICE("BL2: [COLD_BOOT]\n");
- } /* ddrBackup */
- err = rcar_dram_update_boot_status(ddrBackup);
- if (err) {
- NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
- return INITDRAM_ERR_I;
- } /* err */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04285FBF);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5);
+ /* ddr backupmode end */
+ if (ddr_backup)
+ NOTICE("BL2: [WARM_BOOT]\n");
+ else
+ NOTICE("BL2: [COLD_BOOT]\n");
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x08000000);
+ err = rcar_dram_update_boot_status(ddr_backup);
+ if (err) {
+ NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
+ return INITDRAM_ERR_I;
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04285FBF);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x08000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000003);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
- } /* ddr_md */
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
-/* rev0.08 */
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000000C);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x18000040);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */
- /****************************************************************************
- * recovery_Step2(PHY setting 2)
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /* Select setting value in bps */
+ if (ddr_md == 0) /* 1584Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ else /* 1856Mbps */
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000000C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x18000040);
- WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
- WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010);
+ /*
+ * recovery_Step2(PHY setting 2)
+ */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- /* Select setting value in bps */
- if (ddr_md == 0) { /* 1584Mbps */
- WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
- } else { /* 1856Mbps */
- WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
- WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000);
- WriteReg_32(DBSC_E3_DBRFEN, 0x00000001);
- WriteReg_32(DBSC_E3_DBCMD, 0x0A840001);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0);
+ mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000);
+ mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
- WriteReg_32(DBSC_E3_DBCMD, 0x00000000);
+ /* Select setting value in bps */
+ if (ddr_md == 0) { /* 1584Mbps */
+ mmio_write_32(DBSC_DBRFCNF1,
+ (REFRESH_RATE * 99 / 125) + 0x00080000);
+ } else { /* 1856Mbps */
+ mmio_write_32(DBSC_DBRFCNF1,
+ (REFRESH_RATE * 116 / 125) + 0x00080000);
+ }
- WriteReg_32(DBSC_E3_DBCMD, 0x04840010);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0);
+ mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+ mmio_write_32(DBSC_DBRFEN, 0x00000001);
+ mmio_write_32(DBSC_DBCMD, 0x0A840001);
+ while (mmio_read_32(DBSC_DBWAIT) & BIT(0))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBCMD, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010701);
+ mmio_write_32(DBSC_DBCMD, 0x04840010);
+ while (mmio_read_32(DBSC_DBWAIT) & BIT(0))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- for (i = 0; i < 4; i++)
- {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
- RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
- RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
- RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010701);
- if (RegVal_R6 > 0) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6);
- } else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
- } /* RegVal_R6 */
- } /* for i */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0);
+ for (i = 0; i < 4; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
- /* rev.0.08 */
- if (pdqsr_ctl == 1){} else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- }
+ if (r6 > 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0,
+ r2 | ((r6 + (r5 << 1)) & 0xFF));
+ }
+ }
- /* PDR always off */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ if (pdqsr_ctl == 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8);
+ /* PDR always off */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ }
- /* rev.0.08 */
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
-if (pdqsr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-}
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
- /* PDR dynamic */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00011001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ if (pdqsr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
-if (pdqsr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-}
+ /* PDR dynamic */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ }
- /* PDR always off */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00012001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ if (pdqsr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ }
-if (pdqsr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-}
+ /* PDR always off */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ }
- /* PDR dynamic */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00014001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ if (pdqsr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ /* PDR dynamic */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ }
- for (i = 0; i < 4; i++) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
- RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
- RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
- RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
- RegVal_R12 = (RegVal_R5 >> 0x2);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00018001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- if (RegVal_R12 < RegVal_R6) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
- } else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
- } /* RegVal_R12 < RegVal_R6 */
- } /* for i */
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
-/* rev.0.08 */
- if (pdqsr_ctl == 1){} else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- }
+ for (i = 0; i < 4; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ r12 = r5 >> 0x2;
- /* PDR always off */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
- }
+ if (r12 < r6) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0,
+ r2 |
+ ((r6 + r5 + (r5 >> 1) + r12) & 0xFF));
+ }
+ }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
- while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+ if (pdqsr_ctl == 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
-/* rev.0.08 */
- if (lcdl_ctl == 1) {
- for (i = 0; i < 4; i++) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
- bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
- bdlcount_0c_div2 = (bdlcount_0c >> 1);
- bdlcount_0c_div4 = (bdlcount_0c >> 2);
- bdlcount_0c_div8 = (bdlcount_0c >> 3);
- bdlcount_0c_div16 = (bdlcount_0c >> 4);
+ /* PDR always off */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
+ }
- if (ddr_md == 0) { /* 1584Mbps */
- lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8;
- lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16;
- } else { /* 1856Mbps */
- lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4;
- lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4;
- } /* ddr_md */
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- if (dqsgd_0c > lcdl_judge1) {
- if (dqsgd_0c <= lcdl_judge2) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
- } else {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
- rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
- rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
- WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
- rbd_0c[0] = (RegVal) &0x0000001f;
- rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
- rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
- rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
- for (j = 0; j < 4; j++) {
- rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
- if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
- RegVal = RegVal | (rbd_0c[j] << 8 * j);
- }
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
- rbd_0c[0] = (RegVal) &0x0000001f;
- rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
- rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
- rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
- RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
- for (j = 0; j < 4; j++) {
- rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
- if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
- RegVal = RegVal | (rbd_0c[j] << 8 * j);
+ if (lcdl_ctl == 1) {
+ for (i = 0; i < 4; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+ dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x000000FF;
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20);
+ bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) &
+ 0x0000FF00) >> 8;
+ bdlcount_0c_div2 = (bdlcount_0c >> 1);
+ bdlcount_0c_div4 = (bdlcount_0c >> 2);
+ bdlcount_0c_div8 = (bdlcount_0c >> 3);
+ bdlcount_0c_div16 = (bdlcount_0c >> 4);
+
+ if (ddr_md == 0) { /* 1584Mbps */
+ lcdl_judge1 = bdlcount_0c_div2 +
+ bdlcount_0c_div4 +
+ bdlcount_0c_div8;
+ lcdl_judge2 = bdlcount_0c +
+ bdlcount_0c_div4 +
+ bdlcount_0c_div16;
+ } else { /* 1856Mbps */
+ lcdl_judge1 = bdlcount_0c_div2 +
+ bdlcount_0c_div4;
+ lcdl_judge2 = bdlcount_0c +
+ bdlcount_0c_div4;
+ }
+
+ if (dqsgd_0c <= lcdl_judge1)
+ continue;
+
+ if (dqsgd_0c <= lcdl_judge2) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGD0,
+ (dqsgd_0c - bdlcount_0c_div8) |
+ regval);
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xFFFFFF00;
+ mmio_write_32(DBSC_DBPDRGD0, regval);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xFFFFFFF8;
+ mmio_write_32(DBSC_DBPDRGD0,
+ regval | (gatesl_0c + 1));
+ mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0);
+ rdqsd_0c = (regval & 0xFF00) >> 8;
+ rdqsnd_0c = (regval & 0xFF0000) >> 16;
+ mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0,
+ (regval & 0xFF0000FF) |
+ ((rdqsd_0c +
+ bdlcount_0c_div4) << 8) |
+ ((rdqsnd_0c +
+ bdlcount_0c_div4) << 16));
+ mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD0));
+ rbd_0c[0] = (regval) & 0x1f;
+ rbd_0c[1] = (regval >> 8) & 0x1f;
+ rbd_0c[2] = (regval >> 16) & 0x1f;
+ rbd_0c[3] = (regval >> 24) & 0x1f;
+ mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xE0E0E0E0;
+ for (j = 0; j < 4; j++) {
+ rbd_0c[j] = rbd_0c[j] +
+ bdlcount_0c_div4;
+ if (rbd_0c[j] > 0x1F)
+ rbd_0c[j] = 0x1F;
+ regval = regval | (rbd_0c[j] << 8 * j);
+ }
+ mmio_write_32(DBSC_DBPDRGD0, regval);
+ mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
+ regval = (mmio_read_32(DBSC_DBPDRGD0));
+ rbd_0c[0] = regval & 0x1f;
+ rbd_0c[1] = (regval >> 8) & 0x1f;
+ rbd_0c[2] = (regval >> 16) & 0x1f;
+ rbd_0c[3] = (regval >> 24) & 0x1f;
+ mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
+ regval = mmio_read_32(DBSC_DBPDRGD0) &
+ 0xE0E0E0E0;
+ for (j = 0; j < 4; j++) {
+ rbd_0c[j] = rbd_0c[j] +
+ bdlcount_0c_div4;
+ if (rbd_0c[j] > 0x1F)
+ rbd_0c[j] = 0x1F;
+ regval = regval | (rbd_0c[j] << 8 * j);
+ }
+ mmio_write_32(DBSC_DBPDRGD0, regval);
+ }
}
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
- }
- }
- }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37);
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000002);
+ mmio_write_32(DBSC_DBPDRGD0, 0x07D81E37);
+ }
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ if (byp_ctl == 1)
+ mmio_write_32(DBSC_DBPDRGD0, 0x0380C720);
+ else
+ mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
- if (byp_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720);
- } else {
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700);
- }
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
- while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ ;
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
- /****************************************************************************
- * recovery_Step3(DBSC Setting 2)
- ***************************************************************************/
- WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001);
- WriteReg_32(DBSC_E3_DBACEN, 0x00000001);
+ /*
+ * recovery_Step3(DBSC Setting 2)
+ */
+ mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+ mmio_write_32(DBSC_DBACEN, 0x00000001);
-/* rev.0.08 */
- if (pdqsr_ctl == 1) {
- WriteReg_32(0xE67F0018, 0x00000001);
- RegVal = ReadReg_32(0x40000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
- }
+ if (pdqsr_ctl == 1) {
+ mmio_write_32(0xE67F0018, 0x00000001);
+ regval = mmio_read_32(0x40000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGD0, regval);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ }
- /* PDR dynamic */ /* rev.0.10 */
- if (pdr_ctl == 1) {
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
- WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
- }
+ /* PDR dynamic */
+ if (pdr_ctl == 1) {
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
+ }
- WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000);
- WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
+ mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-#ifdef ddr_qos_init_setting /* only for non qos_init */
- WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
- WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218);
- WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4);
- WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037);
- WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001);
- WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111);
- WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123);
- WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00);
- WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00);
- WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000);
- WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000);
- WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300);
- WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0);
- WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200);
- WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100);
- WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100);
- WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0);
- WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0);
- WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040);
- WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100);
- WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0);
- WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0);
- WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040);
- WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0);
- WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0);
- WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080);
- WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040);
- WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040);
- WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030);
- WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020);
- WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010);
+#ifdef ddr_qos_init_setting /* only for non qos_init */
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+ mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+ mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
+ mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+ mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+ mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+ mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+ mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+ mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
+ mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
+ mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
+ mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+ mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
+ mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS90, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0);
+ mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0);
+ mmio_write_32(DBSC_DBSCHQOS93, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+ mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+ mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+ mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+ mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
+ mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
+ mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
+ mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
-/* rev.0.08 */
- if (pdqsr_ctl == 1){} else {
- WriteReg_32(0xE67F0018, 0x00000001);
- }
+ if (pdqsr_ctl == 0)
+ mmio_write_32(0xE67F0018, 0x00000001);
- WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
#endif
- return 1;
+ return 1;
-} /* recovery_from_backup_mode */
+} /* recovery_from_backup_mode */
-/*******************************************************************************
- * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps
- ******************************************************************************/
+/*
+ * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps
+ */
-/*******************************************************************************
- * DDR Initialize entry for IPL
- ******************************************************************************/
+/*
+ * DDR Initialize entry for IPL
+ */
int32_t rcar_dram_init(void)
{
- uint32_t dataL;
- uint32_t failcount;
- uint32_t md = 0;
- uint32_t ddr = 0;
+ uint32_t dataL;
+ uint32_t failcount;
+ uint32_t md = 0;
+ uint32_t ddr = 0;
+ uint32_t ddr_backup;
- md = *((volatile uint32_t*)RST_MODEMR);
- ddr = (md & 0x00080000) >> 19;
- if (ddr == 0x0) {
- NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION);
- } else if(ddr == 0x1){
- NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION);
- } /* ddr */
+ md = *((volatile uint32_t*)RST_MODEMR);
+ ddr = (md & 0x00080000) >> 19;
+ if (ddr == 0x0)
+ NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION);
+ else if (ddr == 0x1)
+ NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION);
- rcar_dram_get_boot_status(&ddrBackup);
+ rcar_dram_get_boot_status(&ddr_backup);
- if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
- dataL = recovery_from_backup_mode(); /* WARM boot */
- } else {
- dataL = init_ddr(); /* COLD boot */
- } /* ddrBackup */
+ if (ddr_backup == DRAM_BOOT_STATUS_WARM)
+ dataL = recovery_from_backup_mode(ddr_backup); /* WARM boot */
+ else
+ dataL = init_ddr(); /* COLD boot */
- if (dataL == 1) {
- failcount = 0;
- } else {
- failcount = 1;
- } /* dataL */
+ if (dataL == 1)
+ failcount = 0;
+ else
+ failcount = 1;
- if (failcount == 0) {
- return INITDRAM_OK;
- } else {
- return INITDRAM_NG;
- } /* failcount */
-} /* InitDram */
+ if (failcount == 0)
+ return INITDRAM_OK;
+ else
+ return INITDRAM_NG;
-/*******************************************************************************
- * END
- ******************************************************************************/
+}
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
deleted file mode 100644
index 2e9a5bf..0000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef DDR_INIT_E3_H
-#define DDR_INIT_E3_H
-
-#include <stdint.h>
-
-#define RCAR_E3_DDR_VERSION "rev.0.11"
-
-#ifdef ddr_qos_init_setting
- #define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */
-#else
- #if RCAR_REF_INT == 0
- #define REFRESH_RATE 3900
- #elif RCAR_REF_INT == 1
- #define REFRESH_RATE 7800
- #else
- #define REFRESH_RATE 3900
- #endif
-#endif
-
-extern int32_t rcar_dram_init(void);
-#define INITDRAM_OK (0)
-#define INITDRAM_NG (0xffffffff)
-#define INITDRAM_ERR_I (0xffffffff)
-#define INITDRAM_ERR_O (0xfffffffe)
-#define INITDRAM_ERR_T (0xfffffff0)
-
-#endif /* DDR_INIT_E3_H */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
index 7e93328..00e1903 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
@@ -1,339 +1,338 @@
/*
- * Copyright (c) 2015-2016, Renesas Electronics Corporation
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
#include <stdint.h>
#include "boot_init_dram.h"
-#include "boot_init_dram_regdef_v3m.h"
-
-static void WriteReg_32(uintptr_t a, uint32_t v)
-{
- *(volatile uint32_t*)a = v;
-}
-
-static uint32_t ReadReg_32(uintptr_t a)
-{
- uint32_t w = *(volatile uint32_t*)a;
- return w;
-}
+#include "boot_init_dram_regdef.h"
static uint32_t init_ddr_v3m_1600(void)
{
- // last modified 2016.12.16
+ uint32_t i, r2, r5, r6, r7, r12;
- uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
-
- WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
- WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ mmio_write_32(DBSC_DBKIND, 0x00000007);
#if RCAR_DRAM_DDR3L_MEMCONF == 0
- WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02); // 1GB: Eagle
+ mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); // 1GB: Eagle
#else
- WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02); // 2GB: V3MSK
+ mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); // 2GB: V3MSK
#endif
- WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
- WriteReg_32(DBSC_V3M_DBTR0,0x0000000B);
- WriteReg_32(DBSC_V3M_DBTR1,0x00000008);
- WriteReg_32(DBSC_V3M_DBTR3,0x0000000B);
- WriteReg_32(DBSC_V3M_DBTR4,0x000B000B);
- WriteReg_32(DBSC_V3M_DBTR5,0x00000027);
- WriteReg_32(DBSC_V3M_DBTR6,0x0000001C);
- WriteReg_32(DBSC_V3M_DBTR7,0x00060006);
- WriteReg_32(DBSC_V3M_DBTR8,0x00000020);
- WriteReg_32(DBSC_V3M_DBTR9,0x00000006);
- WriteReg_32(DBSC_V3M_DBTR10,0x0000000C);
- WriteReg_32(DBSC_V3M_DBTR11,0x0000000B);
- WriteReg_32(DBSC_V3M_DBTR12,0x00120012);
- WriteReg_32(DBSC_V3M_DBTR13,0x01180118);
- WriteReg_32(DBSC_V3M_DBTR14,0x00140005);
- WriteReg_32(DBSC_V3M_DBTR15,0x00050004);
- WriteReg_32(DBSC_V3M_DBTR16,0x071D0305);
- WriteReg_32(DBSC_V3M_DBTR17,0x040C0010);
- WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
- WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
- WriteReg_32(DBSC_V3M_DBTR20,0x02000120);
- WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
- WriteReg_32(DBSC_V3M_DBBL,0x00000000);
- WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
- WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
- WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00082010);
- WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x00002000);
- WriteReg_32(DBSC_V3M_DBSCHCNT0,0x080f003f);
- WriteReg_32(DBSC_V3M_DBSCHCNT1,0x00001010);
- WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
- WriteReg_32(DBSC_V3M_DBSCHRW0,0x00000200);
- WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000040);
- WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000600);
- WriteReg_32(DBSC_V3M_DBSCHQOS41,0x00000480);
- WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000300);
- WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000180);
- WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000400);
- WriteReg_32(DBSC_V3M_DBSCHQOS91,0x00000300);
- WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
- WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
- WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000300);
- WriteReg_32(DBSC_V3M_DBSCHQOS131,0x00000240);
- WriteReg_32(DBSC_V3M_DBSCHQOS132,0x00000180);
- WriteReg_32(DBSC_V3M_DBSCHQOS133,0x000000c0);
- WriteReg_32(DBSC_V3M_DBSCHQOS140,0x00000200);
- WriteReg_32(DBSC_V3M_DBSCHQOS141,0x00000180);
- WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000100);
- WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000080);
- WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000100);
- WriteReg_32(DBSC_V3M_DBSCHQOS151,0x000000c0);
- WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000080);
- WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000040);
- WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
- WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00040C04);
- WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000001c4);
- WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000003);
- WriteReg_32(DBSC_V3M_DBSCHRW1,0x001a0080);
- WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
+ mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
+ mmio_write_32(DBSC_DBTR0, 0x0000000B);
+ mmio_write_32(DBSC_DBTR1, 0x00000008);
+ mmio_write_32(DBSC_DBTR3, 0x0000000B);
+ mmio_write_32(DBSC_DBTR4, 0x000B000B);
+ mmio_write_32(DBSC_DBTR5, 0x00000027);
+ mmio_write_32(DBSC_DBTR6, 0x0000001C);
+ mmio_write_32(DBSC_DBTR7, 0x00060006);
+ mmio_write_32(DBSC_DBTR8, 0x00000020);
+ mmio_write_32(DBSC_DBTR9, 0x00000006);
+ mmio_write_32(DBSC_DBTR10, 0x0000000C);
+ mmio_write_32(DBSC_DBTR11, 0x0000000B);
+ mmio_write_32(DBSC_DBTR12, 0x00120012);
+ mmio_write_32(DBSC_DBTR13, 0x01180118);
+ mmio_write_32(DBSC_DBTR14, 0x00140005);
+ mmio_write_32(DBSC_DBTR15, 0x00050004);
+ mmio_write_32(DBSC_DBTR16, 0x071D0305);
+ mmio_write_32(DBSC_DBTR17, 0x040C0010);
+ mmio_write_32(DBSC_DBTR18, 0x00000200);
+ mmio_write_32(DBSC_DBTR19, 0x01000040);
+ mmio_write_32(DBSC_DBTR20, 0x02000120);
+ mmio_write_32(DBSC_DBTR21, 0x00040004);
+ mmio_write_32(DBSC_DBBL, 0x00000000);
+ mmio_write_32(DBSC_DBODT0, 0x00000001);
+ mmio_write_32(DBSC_DBADJ0, 0x00000001);
+ mmio_write_32(DBSC_DBCAM0CNF1, 0x00082010);
+ mmio_write_32(DBSC_DBCAM0CNF2, 0x00002000);
+ mmio_write_32(DBSC_DBSCHCNT0, 0x080f003f);
+ mmio_write_32(DBSC_DBSCHCNT1, 0x00001010);
+ mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+ mmio_write_32(DBSC_DBSCHRW0, 0x00000200);
+ mmio_write_32(DBSC_DBSCHRW1, 0x00000040);
+ mmio_write_32(DBSC_DBSCHQOS40, 0x00000600);
+ mmio_write_32(DBSC_DBSCHQOS41, 0x00000480);
+ mmio_write_32(DBSC_DBSCHQOS42, 0x00000300);
+ mmio_write_32(DBSC_DBSCHQOS43, 0x00000180);
+ mmio_write_32(DBSC_DBSCHQOS90, 0x00000400);
+ mmio_write_32(DBSC_DBSCHQOS91, 0x00000300);
+ mmio_write_32(DBSC_DBSCHQOS92, 0x00000200);
+ mmio_write_32(DBSC_DBSCHQOS93, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS130, 0x00000300);
+ mmio_write_32(DBSC_DBSCHQOS131, 0x00000240);
+ mmio_write_32(DBSC_DBSCHQOS132, 0x00000180);
+ mmio_write_32(DBSC_DBSCHQOS133, 0x000000c0);
+ mmio_write_32(DBSC_DBSCHQOS140, 0x00000200);
+ mmio_write_32(DBSC_DBSCHQOS141, 0x00000180);
+ mmio_write_32(DBSC_DBSCHQOS142, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS143, 0x00000080);
+ mmio_write_32(DBSC_DBSCHQOS150, 0x00000100);
+ mmio_write_32(DBSC_DBSCHQOS151, 0x000000c0);
+ mmio_write_32(DBSC_DBSCHQOS152, 0x00000080);
+ mmio_write_32(DBSC_DBSCHQOS153, 0x00000040);
+ mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+ mmio_write_32(DBSC_DBCAM0CNF1, 0x00040C04);
+ mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4);
+ mmio_write_32(DBSC_DBSCHSZ0, 0x00000003);
+ mmio_write_32(DBSC_DBSCHRW1, 0x001a0080);
+ mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
- WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
- WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
- WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
+ mmio_write_32(DBSC_DBCMD, 0x01000001);
+ mmio_write_32(DBSC_DBCMD, 0x08000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
+ mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C700);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
- while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
+ ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X13C03C10);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGD0, 0x08C0C170);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
+ mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
+ mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
+ mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
+ mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000004);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00000018);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
+ mmio_write_32(DBSC_DBPDRGD0, 0x13C03C10);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
- WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
+ mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
+ mmio_write_32(DBSC_DBCMD, 0x08000001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- for (uint32_t i = 0; i<4; i++)
- {
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
- RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
- RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
- RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
- if ( RegVal_R6 > 0 )
- {
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
+ for (i = 0; i < 4; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
- WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
- WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
- } else {
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
- WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);
+ if (r6 > 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
- RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
- WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
- }
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 |
+ (((r5 << 1) + r6) & 0xFF));
+ }
+ }
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00A0);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
+ mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00B8);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- for (uint32_t i = 0; i < 4; i++)
- {
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20);
- RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8;
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20);
- RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
+ mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
+ mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20);
- RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
- RegVal_R12 = (RegVal_R5 >> 2);
- if (RegVal_R6 - RegVal_R12 > 0)
- {
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
+ for (i = 0; i < 4; i++) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
+ r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
+ mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
+ r6 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF);
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
- WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2);
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
+ r7 = (mmio_read_32(DBSC_DBPDRGD0) & 0x7);
+ r12 = (r5 >> 2);
+ if (r6 - r12 > 0) {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
- WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
- }
- else
- {
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
- WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2);
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
- RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
- WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
- WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2);
- }
- }
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
- while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, ((r6 - r12) & 0xFF) | r2);
+ } else {
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, (r7 & 0x7) | r2);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+ mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
+ mmio_write_32(DBSC_DBPDRGD0, r2 |
+ ((r6 + r5 +
+ (r5 >> 1) + r12) & 0xFF));
+ }
+ }
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C700);
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
- while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );
- WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
- WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
+ mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
+ mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
+ while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
+ ;
- WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
- WriteReg_32(DBSC_V3M_DBBUS0CNF0,0x00010001);
- WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200E);
- WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860);
- WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);
- WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
- WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
- WriteReg_32(DBSC_V3M_DBACEN,0x00000001);
- WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
- WriteReg_32(0xE67F0024, 0x00000001);
- WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
+ while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
+ ;
+ mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
+ mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
- return 1;
+ mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000);
+ mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001);
+ mmio_write_32(DBSC_DBCALCNF, 0x0100200E);
+ mmio_write_32(DBSC_DBRFCNF1, 0x00081860);
+ mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+ mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+ mmio_write_32(DBSC_DBRFEN, 0x00000001);
+ mmio_write_32(DBSC_DBACEN, 0x00000001);
+ mmio_write_32(DBSC_DBPDLK0, 0x00000000);
+ mmio_write_32(0xE67F0024, 0x00000001);
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+
+ return INITDRAM_OK;
}
int32_t rcar_dram_init(void)
{
- return init_ddr_v3m_1600() ? INITDRAM_OK : INITDRAM_NG;
+ return init_ddr_v3m_1600();
}
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
index 16581bd..89d666c 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -79,18 +79,18 @@
char *pRCAR_DDR_VERSION;
uint32_t _cnf_BOARDTYPE;
-static uint32_t *pDDR_REGDEF_TBL;
+static const uint32_t *pDDR_REGDEF_TBL;
static uint32_t brd_clk;
static uint32_t brd_clkdiv;
static uint32_t brd_clkdiva;
static uint32_t ddr_mbps;
static uint32_t ddr_mbpsdiv;
static uint32_t ddr_tccd;
-static struct _boardcnf *Boardcnf;
-static uint32_t ddr_phyvalid;
static uint32_t ddr_phycaslice;
-static volatile uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
-static uint32_t ch_have_this_cs[CS_CNT];
+static const struct _boardcnf *Boardcnf;
+static uint32_t ddr_phyvalid;
+static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
+static uint32_t ch_have_this_cs[CS_CNT] __attribute__ ((aligned(64)));
static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t max_density;
static uint32_t ddr0800_mul;
@@ -228,7 +228,7 @@
/*******************************************************************************
* Prototypes
******************************************************************************/
-static inline int32_t vch_nxt(int32_t pos);
+static inline uint32_t vch_nxt(uint32_t pos);
static void cpg_write_32(uint32_t a, uint32_t v);
static void pll3_control(uint32_t high);
static inline void dsb_sev(void);
@@ -328,9 +328,9 @@
/*******************************************************************************
* macro for channel selection loop
******************************************************************************/
-static inline int32_t vch_nxt(int32_t pos)
+static inline uint32_t vch_nxt(uint32_t pos)
{
- int32_t posn;
+ uint32_t posn;
for (posn = pos; posn < DRAM_CH_CNT; posn++) {
if (ddr_phyvalid & (1U << posn))
@@ -364,26 +364,34 @@
uint32_t dataL, dataDIV, dataMUL, tmpDIV;
if (high) {
- tmpDIV =
- (1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
- (ddr_mul * brd_clk * ddr_mbpsdiv + 1);
- dataMUL =
- (ddr_mul * (tmpDIV + 1) - 1) << 24;
+ tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+ (brd_clk * ddr_mul) / 2;
+ dataMUL = (((ddr_mul * tmpDIV) - 1) << 24) |
+ (brd_clkdiva << 7);
Pll3Mode = 1;
loop_max = 2;
} else {
- tmpDIV =
- (1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
- (ddr0800_mul * brd_clk * ddr_mbpsdiv + 1);
- dataMUL =
- (ddr0800_mul * (tmpDIV + 1) - 1) << 24;
+ tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+ (brd_clk * ddr0800_mul) / 2;
+ dataMUL = (((ddr0800_mul * tmpDIV) - 1) << 24) |
+ (brd_clkdiva << 7);
Pll3Mode = 0;
loop_max = 8;
}
- if (tmpDIV) {
- dataDIV = tmpDIV + 1;
- } else {
+
+ switch (tmpDIV) {
+ case 1:
dataDIV = 0;
+ break;
+ case 2:
+ case 3:
+ case 4:
+ dataDIV = tmpDIV;
+ break;
+ default:
+ dataDIV = 6;
+ dataMUL = (dataMUL * tmpDIV) / 3;
+ break;
}
dataMUL = dataMUL | (brd_clkdiva << 7);
@@ -478,8 +486,6 @@
} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
}
-
- return;
}
/*******************************************************************************
@@ -891,17 +897,14 @@
#define JS1_MR1(f) (0x04 | ((f)<<4))
#define JS1_MR2(f) (0x00 | ((f)<<3) | (f))
const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
-/*A { 800, 6, 6, 4, 6 , 8, JS1_MR1(0), JS1_MR2(0) }, 533.333Mbps*/
-/*A { 1600, 10, 12, 6, 10 , 8, JS1_MR1(1), JS1_MR2(1) }, 1066.666Mbps*/
-/*A { 2400, 14, 16, 8, 16 , 8, JS1_MR1(2), JS1_MR2(2) }, 1600.000Mbps*/
- /*B*/ {800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40}, /* 533.333Mbps */
- /*B*/ {1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40}, /* 1066.666Mbps */
- /*B*/ {2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40}, /* 1600.000Mbps */
- /*A*/ {3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3)}, /* 2133.333Mbps */
- /*A*/ {4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4)}, /* 2666.666Mbps */
- /*A*/ {4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5)}, /* 3200.000Mbps */
- /*A*/ {5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6)}, /* 3733.333Mbps */
- /*A*/ {6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7)} /* 4266.666Mbps */
+ { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0)|0x40 }, /* 533.333Mbps */
+ { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1)|0x40 }, /* 1066.666Mbps */
+ { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2)|0x40 }, /* 1600.000Mbps */
+ { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, /* 2133.333Mbps */
+ { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, /* 2666.666Mbps */
+ { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, /* 3200.000Mbps */
+ { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) }, /* 3733.333Mbps */
+ { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) } /* 4266.666Mbps */
};
struct _jedec_spec2 {
@@ -1225,7 +1228,7 @@
******************************************************************************/
static void ddrtbl_load(void)
{
- int i;
+ uint32_t i;
uint32_t slice;
uint32_t csab;
uint32_t adr;
@@ -1238,7 +1241,7 @@
***********************************************************************/
/* search jedec_spec1 index */
for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) {
- if (js1[i].fx3 * 2 * ddr_mbpsdiv >= ddr_mbps * 3)
+ if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U)
break;
}
if (JS1_USABLEC_SPEC_HI < i)
@@ -1441,12 +1444,12 @@
#endif /* _def_LPDDR4_VREFCA */
if ((Prr_Product == PRR_PRODUCT_M3N)
|| (Prr_Product == PRR_PRODUCT_V3H)) {
- js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7;
+ js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
if (js2[JS2_tIEdly] > (RL))
js2[JS2_tIEdly] = RL;
} else if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut > PRR_PRODUCT_11)) {
- js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4;
+ js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
} else if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut <= PRR_PRODUCT_11)) {
js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
@@ -1528,7 +1531,8 @@
/***********************************************************************
FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety)
***********************************************************************/
- ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01);
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01);
/***********************************************************************
@@ -1613,11 +1617,12 @@
******************************************************************************/
static void ddr_config_sub(void)
{
- int32_t i;
+ uint32_t i;
uint32_t ch, slice;
uint32_t dataL;
uint32_t tmp;
uint8_t high_byte[SLICE_CNT];
+ const uint32_t _par_CALVL_DEVICE_MAP = 1;
foreach_vch(ch) {
/***********************************************************************
BOARD SETTINGS (DQ,DM,VREF_DRIVING)
@@ -1645,8 +1650,6 @@
/***********************************************************************
BOARD SETTINGS (CA,ADDR_SEL)
***********************************************************************/
- const uint32_t _par_CALVL_DEVICE_MAP = 1;
-
dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) |
0x00888888;
@@ -1771,11 +1774,20 @@
uint32_t dataL;
uint32_t tmp;
uint8_t high_byte[SLICE_CNT];
+ uint32_t ca_swizzle;
+ uint32_t ca;
+ uint32_t csmap;
+ uint32_t o_inv;
+ uint32_t inv;
+ uint32_t bit_soc;
+ uint32_t bit_mem;
+ uint32_t j;
+
+ const uint8_t o_mr15 = 0x55;
+ const uint8_t o_mr20 = 0x55;
+ const uint16_t o_mr32_mr40 = 0x5a3c;
foreach_vch(ch) {
- uint32_t ca_swizzle;
- uint32_t ca;
- uint32_t csmap;
/***********************************************************************
BOARD SETTINGS (DQ,DM,VREF_DRIVING)
***********************************************************************/
@@ -1817,15 +1829,6 @@
ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01);
for (slice = 0; slice < SLICE_CNT; slice++) {
- const uint8_t o_mr15 = 0x55;
- const uint8_t o_mr20 = 0x55;
- const uint16_t o_mr32_mr40 = 0x5a3c;
- uint32_t o_inv;
- uint32_t inv;
- uint32_t bit_soc;
- uint32_t bit_mem;
- uint32_t j;
-
ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM,
0x01);
ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START,
@@ -1862,6 +1865,14 @@
uint32_t ch, slice;
uint32_t dataL;
uint32_t tmp;
+ int8_t _adj;
+ int16_t adj;
+ uint32_t dq;
+ union {
+ uint32_t ui32[4];
+ uint8_t ui8[16];
+ } patt;
+ uint16_t patm;
/***********************************************************************
configure ddrphy registers
@@ -1876,11 +1887,6 @@
WDQ_USER_PATT
***********************************************************************/
foreach_vch(ch) {
- union {
- uint32_t ui32[4];
- uint8_t ui8[16];
- } patt;
- uint16_t patm;
for (slice = 0; slice < SLICE_CNT; slice++) {
patm = 0;
for (i = 0; i < 16; i++) {
@@ -1905,48 +1911,65 @@
CACS DLY
***********************************************************************/
dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
-
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
- set_dfifrequency(0x1f);
- } else {
- ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00);
- ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x01);
- }
-
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U);
foreach_vch(ch) {
- int16_t adj;
- for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
+ for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) {
adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
- ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- dataL + adj);
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+ dataL + adj);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
+ _cnf_DDR_PHY_ADR_V_REGSET[
+ ddr_regdef_adr(
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+ DDR_PHY_ADR_V_REGSET_OFS]);
+ }
+
+ for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4);
+ i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
+ adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+ dataL + adj);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
+ _cnf_DDR_PHY_ADR_G_REGSET[
+ ddr_regdef_adr(
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+ DDR_PHY_ADR_G_REGSET_OFS]);
}
+
if (ddr_phycaslice == 1) {
for (i = 0; i < 6; i++) {
- adj =
- _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i +
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
- ddr_setval_s(ch, 2,
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- dataL + adj);
+ adj = _f_scale_adj(
+ Boardcnf->ch[ch].cacs_adj[
+ i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+ dataL + adj);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
+ 0x0100,
+ _cnf_DDR_PHY_ADR_V_REGSET[
+ ddr_regdef_adr(
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+ DDR_PHY_ADR_V_REGSET_OFS]);
}
}
}
- if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
- set_dfifrequency(0x00);
- } else {
- ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01);
- ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x00);
- }
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
/***********************************************************************
WDQDM DLY
***********************************************************************/
dataL = Boardcnf->dqdm_dly_w;
foreach_vch(ch) {
- int8_t _adj;
- int16_t adj;
- uint32_t dq;
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
dq = slice * 8 + i;
@@ -1967,9 +1990,6 @@
***********************************************************************/
dataL = Boardcnf->dqdm_dly_r;
foreach_vch(ch) {
- int8_t _adj;
- int16_t adj;
- uint32_t dq;
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
dq = slice * 8 + i;
@@ -2041,6 +2061,7 @@
int32_t i;
uint32_t ch;
uint32_t dataL;
+ uint32_t dataL2;
uint32_t tmp[4];
/* RFC */
@@ -2193,7 +2214,6 @@
#define _par_DBRNK_VAL (0x7007)
for (i = 0; i < 4; i++) {
- uint32_t dataL2;
dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) {
@@ -2559,7 +2579,7 @@
retry = 0;
while (retry++ < RETRY_MAX) {
foreach_vch(ch) {
- dataL = mmio_read_32(DBSC_INITCOMP(ch));
+ dataL = mmio_read_32(DBSC_DBDFISTAT(ch));
if (dataL & 0x00000001)
phytrainingok |= (1U << ch);
}
@@ -2627,6 +2647,9 @@
uint32_t chip_id[2];
uint32_t term_code;
uint32_t override;
+ uint32_t pvtr;
+ uint32_t pvtp;
+ uint32_t pvtn;
term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_DATA_TERM);
override = 0;
@@ -2652,7 +2675,7 @@
dataL =
ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_TERM_X[index]);
- dataL = (dataL & ~0x0001ffff) | term_code;
+ dataL = (dataL & 0xfffe0000) | term_code;
ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL);
}
} else if ((Prr_Product == PRR_PRODUCT_M3)
@@ -2674,9 +2697,6 @@
if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut <= PRR_PRODUCT_11)) {
foreach_vch(ch) {
- uint32_t pvtr;
- uint32_t pvtp;
- uint32_t pvtn;
dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
pvtr = (dataL >> 12) & 0x1f;
pvtr += 8;
@@ -2693,7 +2713,7 @@
ddrtbl_getval
(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_TERM_X[index]);
- dataL = (dataL & ~0x0001ffff)
+ dataL = (dataL & 0xfffe0000)
| (pvtr << 12)
| (pvtn << 6)
| (pvtp);
@@ -2969,6 +2989,7 @@
uint32_t phytrainingok;
uint32_t ch, slice;
uint32_t err;
+ int16_t adj;
MSG_LF("init_ddr:0\n");
@@ -3130,7 +3151,8 @@
/***********************************************************************
exec pi_training
***********************************************************************/
- ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00);
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
@@ -3159,7 +3181,6 @@
***********************************************************************/
dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
foreach_vch(ch) {
- int16_t adj;
for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
@@ -3563,6 +3584,7 @@
{
uint32_t err, retry_cnt;
const uint32_t retry_max = 0x10;
+ uint32_t ch, ddr_csn, mr14_bkup[4][4];
ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12);
if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
@@ -3577,13 +3599,12 @@
ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF));
retry_cnt = 0;
+ err = 0;
do {
if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut <= PRR_PRODUCT_11)) {
err = wdqdm_man1();
} else {
- uint32_t ch, ddr_csn, mr14_bkup[4][4];
-
ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
0x01);
@@ -3720,15 +3741,15 @@
int8_t _adj;
int16_t adj;
uint32_t dq;
+ int32_t min_win;
+ int32_t win;
+ uint32_t rdq_status_obs_select;
/***********************************************************************
analysis of training results
***********************************************************************/
err = 0;
for (slice = 0; slice < SLICE_CNT; slice++) {
- int32_t min_win;
- int32_t win;
- uint32_t rdq_status_obs_select;
k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
continue;
@@ -3828,6 +3849,7 @@
uint32_t ddr_csn;
#ifdef DDR_FAST_INIT
uint32_t slice;
+ uint32_t i, adj, dataL;
#endif/* DDR_FAST_INIT */
uint32_t err;
@@ -3836,7 +3858,7 @@
***********************************************************************/
err = 0;
- for (ddr_csn = 0; ddr_csn < CS_CNT; ddr_csn++) {
+ for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
/* KICK RDQLVL */
err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
if (err)
@@ -3870,8 +3892,6 @@
&& (Prr_Cut <= PRR_PRODUCT_11))
|| ((Prr_Product == PRR_PRODUCT_M3)
&& (Prr_Cut <= PRR_PRODUCT_10))) {
- uint32_t i, adj, dataL;
-
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
if (i == 8)
@@ -3948,7 +3968,7 @@
int32_t i;
uint32_t startval;
uint32_t curval;
- const uint32_t VAL_END = 0x3f;
+ const int32_t VAL_END = 0x3f;
if (dir == 0) {
startval = (val & 0x01);
@@ -4004,6 +4024,8 @@
uint32_t tmp;
uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
+ uint64_t tmpval;
+ int32_t lsb, msb;
ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
foreach_vch(ch) {
@@ -4041,8 +4063,6 @@
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
- uint64_t tmpval;
- int32_t lsb, msb;
tmpval = val[ch][slice][index];
lsb = _find_change(tmpval, 0);
msb =
@@ -4201,10 +4221,10 @@
Thermal sensor setting
***********************************************************************/
dataL = mmio_read_32(CPG_MSTPSR5);
- if (dataL & BIT22) { /* case THS/TSC Standby */
- dataL &= ~(BIT22);
+ if (dataL & BIT(22)) { /* case THS/TSC Standby */
+ dataL &= ~(BIT(22));
cpg_write_32(CPG_SMSTPCR5, dataL);
- while ((BIT22) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */
+ while ((BIT(22)) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */
}
/* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
@@ -4230,15 +4250,15 @@
if (Prr_Product == PRR_PRODUCT_H3) {
if (Prr_Cut <= PRR_PRODUCT_11) {
- pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[0][0];
+ pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[0][0];
} else {
- pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[2][0];
+ pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[2][0];
}
} else if (Prr_Product == PRR_PRODUCT_M3) {
- pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[1][0];
+ pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[1][0];
} else if ((Prr_Product == PRR_PRODUCT_M3N)
|| (Prr_Product == PRR_PRODUCT_V3H)) {
- pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[3][0];
+ pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[3][0];
} else {
FATAL_MSG("BL2: DDR:Unknown Product\n");
return 0xff;
@@ -4259,7 +4279,7 @@
FATAL_MSG("BL2: DDR:Unknown Board\n");
return 0xff;
}
- Boardcnf = (struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
+ Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
/* RCAR_DRAM_SPLIT_2CH (2U) */
#if RCAR_DRAM_SPLIT == 2
@@ -4327,6 +4347,8 @@
Adjust tccd
***********************************************************************/
dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
+ bus_mbps = 0;
+ bus_mbpsdiv = 0;
switch (dataL) {
case 0:
bus_mbps = brd_clk * 0x60 * 2;
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
index 513bb03..5d1b078 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -1,10 +1,10 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#define BOARDNUM 20
+#define BOARDNUM 22
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
@@ -1425,6 +1425,108 @@
}
}
},
+/* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0x04},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0x04},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0xff},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0xff},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ }
};
void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
@@ -1521,12 +1623,7 @@
#define PFC_PUD6 0xE6060458U
#define GPIO_INDT5 0xE605500CU
#define GPIO_INDT6 0xE605540CU
-
-#define BIT25 (1<<25)
-#define BIT22 (1<<22)
-#define BIT15 (1<<15)
-#define BIT0 (1)
-#define GPIO_GPSR6 (0xE6060118U)
+#define GPIO_GPSR6 0xE6060118U
#if (RCAR_GEN3_ULCB == 0)
static void pfc_write_and_poll(uint32_t a, uint32_t v)
@@ -1557,17 +1654,17 @@
pud5_bak = mmio_read_32(PFC_PUD5);
dsb_sev();
- dataL = (gpsr6_bak & ~BIT15);
+ dataL = (gpsr6_bak & ~BIT(15));
pfc_write_and_poll(GPIO_GPSR6, dataL);
/* Pull-Up/Down Enable (PUEN5[22]=1) */
dataL = puen5_bak;
- dataL |= (BIT22);
+ dataL |= (BIT(22));
pfc_write_and_poll(PFC_PUEN5, dataL);
/* Pull-Down-Enable (PUD5[22]=0, PUEN5[22]=1) */
dataL = pud5_bak;
- dataL &= ~(BIT22);
+ dataL &= ~(BIT(22));
pfc_write_and_poll(PFC_PUD5, dataL);
/* GPSR6[15]=SSI_WS6 */
rcar_micro_delay(10);
@@ -1576,7 +1673,7 @@
/* Pull-Up-Enable (PUD5[22]=1, PUEN5[22]=1) */
dataL = pud5_bak;
- dataL |= (BIT22);
+ dataL |= (BIT(22));
pfc_write_and_poll(PFC_PUD5, dataL);
/* GPSR6[15]=SSI_WS6 */
@@ -1673,7 +1770,7 @@
/* RENESAS SALVATOR-X (M3-W/SIP) */
brd = 0;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
- /* RENESAS SALVATOR-X (M3-W Ver.1.3/SIP) */
+ /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */
brd = 19;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
index 24ff833..a1cbfbf 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#define RCAR_DDR_VERSION "rev.0.35"
+#define RCAR_DDR_VERSION "rev.0.36"
#define DRAM_CH_CNT (0x04)
#define SLICE_CNT (0x04)
#define CS_CNT (0x02)
@@ -144,11 +144,11 @@
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
#define DBSC_DBDFICUPDCNF 0xE679052CU
-#define DBSC_INITCOMP(ch) (0xE6790600U + 0x40U * (ch))
-#define DBSC_INITCOMP_0 0xE6790600U
-#define DBSC_INITCOMP_1 0xE6790640U
-#define DBSC_INITCOMP_2 0xE6790680U
-#define DBSC_INITCOMP_3 0xE67906C0U
+#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
+#define DBSC_DBDFISTAT_0 0xE6790600U
+#define DBSC_DBDFISTAT_1 0xE6790640U
+#define DBSC_DBDFISTAT_2 0xE6790680U
+#define DBSC_DBDFISTAT_3 0xE67906C0U
#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
#define DBSC_DBDFICNT_0 0xE6790604U
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
index b29c773..bad1de9 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -1182,7 +1182,7 @@
#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
-const static uint32_t DDR_REGDEF_TBL[4][1173] = {
+static const uint32_t DDR_REGDEF_TBL[4][1173] = {
{
/*0000*/ 0xffffffffU,
/*0001*/ 0xffffffffU,
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
index 39fc8a6..6fa9ab9 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/drivers/synopsys/emmc/dw_mmc.c b/drivers/synopsys/emmc/dw_mmc.c
index b0dcaa7..04f4673 100644
--- a/drivers/synopsys/emmc/dw_mmc.c
+++ b/drivers/synopsys/emmc/dw_mmc.c
@@ -14,6 +14,7 @@
#include <drivers/delay_timer.h>
#include <drivers/mmc.h>
#include <drivers/synopsys/dw_mmc.h>
+#include <lib/utils_def.h>
#include <lib/mmio.h>
#define DWMMC_CTRL (0x00)
@@ -55,7 +56,7 @@
#define DWMMC_CMDARG (0x28)
#define DWMMC_CMD (0x2c)
-#define CMD_START (1 << 31)
+#define CMD_START (U(1) << 31)
#define CMD_USE_HOLD_REG (1 << 29) /* 0 if SDR50/100 */
#define CMD_UPDATE_CLK_ONLY (1 << 21)
#define CMD_SEND_INIT (1 << 15)
@@ -100,7 +101,7 @@
#define IDMAC_DES0_CH (1 << 4)
#define IDMAC_DES0_ER (1 << 5)
#define IDMAC_DES0_CES (1 << 30)
-#define IDMAC_DES0_OWN (1 << 31)
+#define IDMAC_DES0_OWN (U(1) << 31)
#define IDMAC_DES1_BS1(x) ((x) & 0x1fff)
#define IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13)
@@ -425,7 +426,6 @@
(params->bus_width == MMC_BUS_WIDTH_8)));
memcpy(&dw_params, params, sizeof(dw_mmc_params_t));
- mmio_write_32(dw_params.reg_base + DWMMC_FIFOTH, 0x103ff);
dw_params.mmc_dev_type = info->mmc_dev_type;
mmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width,
params->flags, info);
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts
new file mode 100644
index 0000000..8bc4adf
--- /dev/null
+++ b/fdts/a5ds.dts
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+ model = "A5DS";
+ compatible = "arm,A5DS";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <0>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x7F000000>;
+ };
+
+ refclk100mhz: refclk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ smbclk: refclk24mhzx2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ clock-output-names = "smclk";
+ };
+
+
+ rtc@1a220000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x1a220000 0x1000>;
+ clocks = <&refclk100mhz>;
+ interrupts = <0 6 0xf04>;
+ clock-names = "apb_pclk";
+ };
+
+ gic: interrupt-controller@1c001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1c001000 0x1000>,
+ <0x1c000100 0x100>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ serial0: uart@1a200000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a200000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 8 0xf04>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ serial1: uart@1a210000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a210000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 9 0xf04>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ timer0: timer@1a040000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0x1a040000 0x1000>;
+ clock-frequency = <50000000>;
+
+ frame@1a050000 {
+ frame-number = <0>;
+ interrupts = <0 2 0xf04>;
+ reg = <0x1a050000 0x1000>;
+ };
+ };
+};
diff --git a/include/arch/aarch32/console_macros.S b/include/arch/aarch32/console_macros.S
index 070be84..996cb32 100644
--- a/include/arch/aarch32/console_macros.S
+++ b/include/arch/aarch32/console_macros.S
@@ -15,7 +15,7 @@
* default consoles are enabled for the "boot" and "crash" states, this can be
* changed after registration with the console_set_scope() function). It ends
* with a tail call that will include return to the caller.
- * REQUIRES console_t pointer in x0 and a valid return address in x30.
+ * REQUIRES console_t pointer in r0 and a valid return address in lr.
*/
.macro finish_console_register _driver, putc=0, getc=0, flush=0
/*
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 502b868..913b62c 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -250,7 +250,7 @@
#define SCTLR_SED_BIT (ULL(1) << 8)
#define SCTLR_UMA_BIT (ULL(1) << 9)
#define SCTLR_I_BIT (ULL(1) << 12)
-#define SCTLR_V_BIT (ULL(1) << 13)
+#define SCTLR_EnDB_BIT (ULL(1) << 13)
#define SCTLR_DZE_BIT (ULL(1) << 14)
#define SCTLR_UCT_BIT (ULL(1) << 15)
#define SCTLR_NTWI_BIT (ULL(1) << 16)
@@ -261,6 +261,8 @@
#define SCTLR_E0E_BIT (ULL(1) << 24)
#define SCTLR_EE_BIT (ULL(1) << 25)
#define SCTLR_UCI_BIT (ULL(1) << 26)
+#define SCTLR_EnDA_BIT (ULL(1) << 27)
+#define SCTLR_EnIB_BIT (ULL(1) << 30)
#define SCTLR_EnIA_BIT (ULL(1) << 31)
#define SCTLR_BT0_BIT (ULL(1) << 35)
#define SCTLR_BT1_BIT (ULL(1) << 36)
diff --git a/include/drivers/ufs.h b/include/drivers/ufs.h
index a10cd80..574c4ea 100644
--- a/include/drivers/ufs.h
+++ b/include/drivers/ufs.h
@@ -82,7 +82,7 @@
#define UECDME 0x48
/* UTP Transfer Request Interrupt Aggregation Control Register */
#define UTRIACR 0x4C
-#define UTRIACR_IAEN (1 << 31)
+#define UTRIACR_IAEN (1U << 31)
#define UTRIACR_IAPWEN (1 << 24)
#define UTRIACR_IASB (1 << 20)
#define UTRIACR_CTR (1 << 16)
diff --git a/include/lib/cpus/aarch64/cortex_deimos.h b/include/lib/cpus/aarch64/cortex_a77.h
similarity index 66%
rename from include/lib/cpus/aarch64/cortex_deimos.h
rename to include/lib/cpus/aarch64/cortex_a77.h
index 9d024b6..0467ef3 100644
--- a/include/lib/cpus/aarch64/cortex_deimos.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -4,22 +4,23 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef CORTEX_DEIMOS_H
-#define CORTEX_DEIMOS_H
+#ifndef CORTEX_A77_H
+#define CORTEX_A77_H
#include <lib/utils_def.h>
-#define CORTEX_DEIMOS_MIDR U(0x410FD0D0)
+/* Cortex-A77 MIDR */
+#define CORTEX_A77_MIDR U(0x410FD0D0)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_DEIMOS_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions.
******************************************************************************/
-#define CORTEX_DEIMOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
+#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
-#endif /* CORTEX_DEIMOS_H */
+#endif /* CORTEX_A77_H */
diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h
index b99be30..b17a435 100644
--- a/include/lib/libc/aarch64/stdint_.h
+++ b/include/lib/libc/aarch64/stdint_.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -116,3 +116,6 @@
typedef long register_t;
typedef unsigned long u_register_t;
+
+typedef __int128 int128_t;
+typedef unsigned __int128 uint128_t;
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
new file mode 100644
index 0000000..f3fd5e1
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a77.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ---------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ---------------------------------------------
+ */
+func cortex_a77_core_pwr_dwn
+ /* ---------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------
+ */
+ mrs x0, CORTEX_A77_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_A77_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_a77_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex-A77. Must follow AAPCS.
+ */
+func cortex_a77_errata_report
+ ret
+endfunc cortex_a77_errata_report
+#endif
+
+
+ /* ---------------------------------------------
+ * This function provides Cortex-A77 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a77_regs, "aS"
+cortex_a77_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a77_cpu_reg_dump
+ adr x6, cortex_a77_regs
+ mrs x8, CORTEX_A77_CPUECTLR_EL1
+ ret
+endfunc cortex_a77_cpu_reg_dump
+
+declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \
+ CPU_NO_RESET_FUNC, \
+ cortex_a77_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_deimos.S
deleted file mode 100644
index df4c128..0000000
--- a/lib/cpus/aarch64/cortex_deimos.S
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_deimos.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex-Deimos supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
- /* ---------------------------------------------
- * HW will do the cache maintenance while powering down
- * ---------------------------------------------
- */
-func cortex_deimos_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_DEIMOS_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_DEIMOS_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_deimos_core_pwr_dwn
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex Deimos. Must follow AAPCS.
- */
-func cortex_deimos_errata_report
- ret
-endfunc cortex_deimos_errata_report
-#endif
-
-
- /* ---------------------------------------------
- * This function provides Cortex-Deimos specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_deimos_regs, "aS"
-cortex_deimos_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_deimos_cpu_reg_dump
- adr x6, cortex_deimos_regs
- mrs x8, CORTEX_DEIMOS_CPUECTLR_EL1
- ret
-endfunc cortex_deimos_cpu_reg_dump
-
-declare_cpu_ops cortex_deimos, CORTEX_DEIMOS_MIDR, \
- CPU_NO_RESET_FUNC, \
- cortex_deimos_core_pwr_dwn
diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c
index eca3be3..e31f9d8 100644
--- a/lib/xlat_tables/aarch32/nonlpae_tables.c
+++ b/lib/xlat_tables/aarch32/nonlpae_tables.c
@@ -122,8 +122,8 @@
#define DACR_DOMAIN_PERM_CLIENT 0x1
#define DACR_DOMAIN_PERM_MANAGER 0x3
-#define NUM_1MB_IN_4GB (1 << 12)
-#define NUM_4K_IN_1MB (1 << 8)
+#define NUM_1MB_IN_4GB (1U << 12)
+#define NUM_4K_IN_1MB (1U << 8)
#define ONE_MB_SHIFT 20
diff --git a/plat/arm/board/a5ds/a5ds_bl1_setup.c b/plat/arm/board/a5ds/a5ds_bl1_setup.c
new file mode 100644
index 0000000..629c928
--- /dev/null
+++ b/plat/arm/board/a5ds/a5ds_bl1_setup.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*******************************************************************************
+ * Perform any BL1 specific platform actions.
+ ******************************************************************************/
+void bl1_early_platform_setup(void)
+{
+ arm_bl1_early_platform_setup();
+}
+
+void bl1_platform_setup(void)
+{
+ arm_bl1_platform_setup();
+}
diff --git a/plat/arm/board/a5ds/a5ds_bl2_setup.c b/plat/arm/board/a5ds/a5ds_bl2_setup.c
new file mode 100644
index 0000000..1979c50
--- /dev/null
+++ b/plat/arm/board/a5ds/a5ds_bl2_setup.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+}
+
+void bl2_platform_setup(void)
+{
+ arm_bl2_platform_setup();
+}
diff --git a/plat/arm/board/a5ds/a5ds_common.c b/plat/arm/board/a5ds/a5ds_common.c
new file mode 100644
index 0000000..e462fa1
--- /dev/null
+++ b/plat/arm/board/a5ds/a5ds_common.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <plat/arm/common/arm_config.h>
+#include <plat/arm/common/plat_arm.h>
+
+#define MAP_PERIPHBASE MAP_REGION_FLAT(PERIPHBASE,\
+ PERIPH_SIZE,\
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_A5_PERIPHERALS MAP_REGION_FLAT(A5_PERIPHERALS_BASE,\
+ A5_PERIPHERALS_SIZE,\
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#ifdef IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ MAP_FLASH1_RW,
+ MAP_PERIPHBASE,
+ MAP_A5_PERIPHERALS,
+ {0}
+};
+#endif
+#ifdef IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ MAP_FLASH1_RW,
+ MAP_PERIPHBASE,
+ MAP_A5_PERIPHERALS,
+ ARM_MAP_NS_DRAM1,
+ {0}
+};
+#endif
+#ifdef IMAGE_BL32
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ MAP_PERIPHBASE,
+ MAP_A5_PERIPHERALS,
+ {0}
+};
+#endif
+
+ARM_CASSERT_MMAP
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return A5DS_TIMER_BASE_FREQUENCY;
+}
diff --git a/plat/arm/board/a5ds/a5ds_pm.c b/plat/arm/board/a5ds/a5ds_pm.c
new file mode 100644
index 0000000..5fd443b
--- /dev/null
+++ b/plat/arm/board/a5ds/a5ds_pm.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+
+/*******************************************************************************
+ * Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard
+ * platform layer will take care of registering the handlers with PSCI.
+ ******************************************************************************/
+plat_psci_ops_t a5ds_psci_pm_ops = {
+ /* dummy struct */
+ .validate_ns_entrypoint = NULL,
+};
+
+int __init plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ *psci_ops = &a5ds_psci_pm_ops;
+
+ return 0;
+}
diff --git a/plat/arm/board/a5ds/a5ds_private.h b/plat/arm/board/a5ds/a5ds_private.h
new file mode 100644
index 0000000..f577249
--- /dev/null
+++ b/plat/arm/board/a5ds/a5ds_private.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef A5DS_PRIVATE_H
+#define A5DS_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void a5ds_config_setup(void);
+
+#endif /* A5DS_PRIVATE_H */
diff --git a/plat/arm/board/a5ds/a5ds_security.c b/plat/arm/board/a5ds/a5ds_security.c
new file mode 100644
index 0000000..5593ae0
--- /dev/null
+++ b/plat/arm/board/a5ds/a5ds_security.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * We assume that all security programming is done by the primary core.
+ */
+void plat_arm_security_setup(void)
+{
+ /*
+ * The platform currently does not have any security setup.
+ */
+}
diff --git a/plat/arm/board/a5ds/a5ds_topology.c b/plat/arm/board/a5ds/a5ds_topology.c
new file mode 100644
index 0000000..94fa71f
--- /dev/null
+++ b/plat/arm/board/a5ds/a5ds_topology.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+/* The A5DS power domain tree descriptor */
+static const unsigned char a5ds_power_domain_tree_desc[] = {
+ 1,
+ /* No of children for the root node */
+ A5DS_CLUSTER_COUNT,
+ /* No of children for the first cluster node */
+ A5DS_CORE_COUNT,
+};
+
+/*******************************************************************************
+ * This function returns the topology according to A5DS_CLUSTER_COUNT.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return a5ds_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * Get core position using mpidr
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id;
+
+ mpidr &= MPIDR_AFFINITY_MASK;
+
+ if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
+ return -1;
+
+ cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+ if (cluster_id >= A5DS_CLUSTER_COUNT)
+ return -1;
+
+ /*
+ * Validate cpu_id by checking whether it represents a CPU in
+ * one of the two clusters present on the platform.
+ */
+ if (cpu_id >= A5DS_MAX_CPUS_PER_CLUSTER)
+ return -1;
+
+ return (cpu_id + (cluster_id * 4));
+
+}
diff --git a/plat/arm/board/a5ds/aarch32/a5ds_helpers.S b/plat/arm/board/a5ds/aarch32/a5ds_helpers.S
new file mode 100644
index 0000000..23a22d9
--- /dev/null
+++ b/plat/arm/board/a5ds/aarch32/a5ds_helpers.S
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .globl plat_secondary_cold_boot_setup
+ .globl plat_get_my_entrypoint
+ .globl plat_is_my_cpu_primary
+
+ /* --------------------------------------------------------------------
+ * void plat_secondary_cold_boot_setup (void);
+ *
+ * For AArch32, cold-booting secondary CPUs is not yet
+ * implemented and they panic.
+ * --------------------------------------------------------------------
+ */
+func plat_secondary_cold_boot_setup
+cb_panic:
+ wfi
+ b cb_panic
+endfunc plat_secondary_cold_boot_setup
+
+ /* ---------------------------------------------------------------------
+ * unsigned long plat_get_my_entrypoint (void);
+ *
+ * Main job of this routine is to distinguish between a cold and warm
+ * boot.
+ * ---------------------------------------------------------------------
+ */
+func plat_get_my_entrypoint
+ /* TODO support warm boot */
+ /* Cold reset */
+ mov r0, #0
+ bx lr
+
+endfunc plat_get_my_entrypoint
+
+ /* -----------------------------------------------------
+ * unsigned int plat_is_my_cpu_primary (void);
+ *
+ * Find out whether the current cpu is the primary
+ * cpu.
+ * -----------------------------------------------------
+ */
+func plat_is_my_cpu_primary
+ ldcopr r0, MPIDR
+ ldr r1, =MPIDR_AFFINITY_MASK
+ and r0, r1
+ cmp r0, #0
+ moveq r0, #1
+ movne r0, #0
+ bx lr
+endfunc plat_is_my_cpu_primary
diff --git a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
new file mode 100644
index 0000000..9ab2d96
--- /dev/null
+++ b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+ /* Platform Config */
+ plat_arm_bl2 {
+ compatible = "arm,tb_fw";
+ hw_config_addr = <0x0 0x82000000>;
+ hw_config_max_size = <0x01000000>;
+ /* Disable authentication for development */
+ disable_auth = <0x0>;
+ };
+};
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h
new file mode 100644
index 0000000..db65c37
--- /dev/null
+++ b/plat/arm/board/a5ds/include/platform_def.h
@@ -0,0 +1,350 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <common/tbbr/tbbr_img_def.h>
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/v2m_def.h>
+#include <plat/common/common_def.h>
+
+/* Memory location options for TSP */
+#define ARM_DRAM_ID 2
+
+#define ARM_DRAM1_BASE UL(0x80000000)
+#define ARM_DRAM1_SIZE UL(0x80000000)
+#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - 1)
+
+#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
+/*
+ * The last 2MB is meant to be NOLOAD and will not be zero
+ * initialized.
+ */
+#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ 0x00200000)
+
+#define SRAM_BASE 0x2000000
+#define SRAM_SIZE 0x200000
+
+/* The first 4KB of NS DRAM1 are used as shared memory */
+#define A5DS_SHARED_RAM_BASE SRAM_BASE
+#define A5DS_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
+
+/* The next 252 kB of NS DRAM is used to load the BL images */
+#define ARM_BL_RAM_BASE (A5DS_SHARED_RAM_BASE + \
+ A5DS_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE (PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE - \
+ A5DS_SHARED_RAM_SIZE)
+
+#define PERIPHBASE 0x1a000000
+#define PERIPH_SIZE 0x00240000
+#define A5_PERIPHERALS_BASE 0x1c000000
+#define A5_PERIPHERALS_SIZE 0x10000
+
+#define ARM_CACHE_WRITEBACK_SHIFT 6
+
+#define ARM_IRQ_SEC_PHY_TIMER 29
+
+#define ARM_IRQ_SEC_SGI_0 8
+#define ARM_IRQ_SEC_SGI_1 9
+#define ARM_IRQ_SEC_SGI_2 10
+#define ARM_IRQ_SEC_SGI_3 11
+#define ARM_IRQ_SEC_SGI_4 12
+#define ARM_IRQ_SEC_SGI_5 13
+#define ARM_IRQ_SEC_SGI_6 14
+#define ARM_IRQ_SEC_SGI_7 15
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE)
+
+#define A5DS_IRQ_TZ_WDOG 56
+#define A5DS_IRQ_SEC_SYS_TIMER 57
+
+/* Default cluster count for A5DS */
+#define A5DS_CLUSTER_COUNT 1
+
+/* Default number of CPUs per cluster on A5DS */
+#define A5DS_MAX_CPUS_PER_CLUSTER 4
+
+/* Default number of threads per CPU on A5DS */
+#define A5DS_MAX_PE_PER_CPU 1
+
+#define A5DS_CORE_COUNT 1
+
+#define A5DS_PRIMARY_CPU 0x0
+
+#define FLASH1_BASE UL(0x8000000)
+#define FLASH1_SIZE UL(0x2800000)
+
+#define MAP_FLASH1_RW MAP_REGION_FLAT(FLASH1_BASE,\
+ FLASH1_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_FLASH1_RO MAP_REGION_FLAT(FLASH1_BASE,\
+ FLASH1_SIZE, \
+ MT_RO_DATA | MT_SECURE)
+
+#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
+ A5DS_SHARED_RAM_BASE, \
+ A5DS_SHARED_RAM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
+ ARM_NS_DRAM1_BASE, \
+ ARM_NS_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_SRAM MAP_REGION_FLAT( \
+ SRAM_BASE, \
+ SRAM_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+/*
+ * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to
+ * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides
+ * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order
+ * to be able to access the heap.
+ */
+
+#define ARM_MAP_BL_RO MAP_REGION_FLAT(\
+ BL_CODE_BASE,\
+ BL_CODE_END - BL_CODE_BASE,\
+ MT_CODE | MT_SECURE),\
+ MAP_REGION_FLAT(\
+ BL_RO_DATA_BASE,\
+ BL_RO_DATA_END\
+ - BL_RO_DATA_BASE, \
+ MT_RO_DATA | MT_SECURE)
+
+#if USE_COHERENT_MEM
+#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT(\
+ BL_COHERENT_RAM_BASE,\
+ BL_COHERENT_RAM_END \
+ - BL_COHERENT_RAM_BASE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+#endif
+
+/*
+ * The max number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#define ARM_BL_REGIONS 5
+
+#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
+ ARM_BL_REGIONS)
+
+/* Memory mapped Generic timer interfaces */
+#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
+
+#define ARM_CONSOLE_BAUDRATE 115200
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * id will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE 1
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE 2
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+
+/*
+ * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
+ * and limit. Leave enough space of BL2 meminfo.
+ */
+#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
+#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
+
+/*******************************************************************************
+ * BL1 specific defines.
+ * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
+ * addresses.
+ ******************************************************************************/
+#define BL1_RO_BASE 0x00000000
+#define BL1_RO_LIMIT PLAT_ARM_TRUSTED_ROM_SIZE
+/*
+ * Put BL1 RW at the top of the memory allocated for BL images in NS DRAM.
+ */
+#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE - \
+ (PLAT_ARM_MAX_BL1_RW_SIZE))
+#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
+ (ARM_BL_RAM_SIZE))
+/*******************************************************************************
+ * BL2 specific defines.
+ ******************************************************************************/
+
+/*
+ * Put BL2 just below BL1.
+ */
+#define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE)
+#define BL2_LIMIT BL1_RW_BASE
+
+/* Put BL32 below BL2 in NS DRAM.*/
+#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT
+
+#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
+ - PLAT_ARM_MAX_BL32_SIZE)
+#define BL32_PROGBITS_LIMIT BL2_BASE
+#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+
+/* Required platform porting definitions */
+#define PLATFORM_CORE_COUNT 1
+#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT) + 1
+
+#define PLAT_MAX_PWR_LVL 2
+
+/*
+ * Other platform porting definitions are provided by included headers
+ */
+
+/*
+ * Required ARM standard platform porting definitions
+ */
+
+#define PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE 0x00040000 /* 256 KB */
+
+#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
+#define PLAT_ARM_TRUSTED_ROM_SIZE 0x10000 /* 64KB */
+
+#define PLAT_ARM_DRAM2_SIZE ULL(0x80000000)
+
+/*
+ * Load address of BL33 for this platform port
+ */
+#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000))
+
+/*
+ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
+ * plat_arm_mmap array defined for each BL stage.
+ */
+#if defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES 8
+# define MAX_XLAT_TABLES 6
+#else
+# define PLAT_ARM_MMAP_ENTRIES 12
+# define MAX_XLAT_TABLES 6
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
+
+/*
+ * A5DS_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth.
+ */
+#define A5DS_MAX_BL2_SIZE 0x11000
+
+/*
+ * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
+ * calculated using the current SP_MIN PROGBITS debug size plus the sizes of
+ * BL2 and BL1-RW
+ */
+#define PLAT_ARM_MAX_BL32_SIZE 0x3B000
+/*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# define PLATFORM_STACK_SIZE 0x440
+#elif defined(IMAGE_BL2)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+#define MAX_IO_DEVICES 3
+#define MAX_IO_HANDLES 4
+
+/* Reserve the last block of flash for PSCI MEM PROTECT flag */
+#define PLAT_ARM_FIP_BASE FLASH1_BASE
+#define PLAT_ARM_FIP_MAX_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_NVM_BASE FLASH1_BASE
+#define PLAT_ARM_NVM_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/*
+ * PL011 related constants
+ */
+#define PLAT_ARM_BOOT_UART_BASE 0x1A200000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 24000000
+
+#define PLAT_ARM_RUN_UART_BASE 0x1A210000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000
+
+#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
+
+#define A5DS_TIMER_BASE_FREQUENCY UL(24000000)
+
+/* System timer related constants */
+#define PLAT_ARM_NSTIMER_FRAME_ID 1
+
+/* Mailbox base address */
+#define A5DS_TRUSTED_MAILBOX_BASE A5DS_SHARED_RAM_BASE
+
+/*
+ * GIC related constants to cater for GICv2
+ */
+#define PLAT_ARM_GICD_BASE 0x1C001000
+#define PLAT_ARM_GICC_BASE 0x1C000100
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
+ ARM_G1S_IRQ_PROPS(grp), \
+ INTR_PROP_DESC(A5DS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(A5DS_IRQ_SEC_SYS_TIMER,\
+ GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_LEVEL)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
new file mode 100644
index 0000000..4fd357b
--- /dev/null
+++ b/plat/arm/board/a5ds/platform.mk
@@ -0,0 +1,94 @@
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Add `libfdt` and Arm common helpers required for Dynamic Config
+include lib/libfdt/libfdt.mk
+
+DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \
+ plat/arm/common/arm_dyn_cfg_helpers.c \
+ common/fdt_wrappers.c
+
+A5DS_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
+ drivers/arm/gic/v2/gicv2_main.c \
+ drivers/arm/gic/v2/gicv2_helpers.c \
+ plat/common/plat_gicv2.c \
+ plat/arm/common/arm_gicv2.c
+
+A5DS_SECURITY_SOURCES := plat/arm/board/a5ds/a5ds_security.c
+
+PLAT_INCLUDES := -Iplat/arm/board/a5ds/include
+
+PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/${ARCH}/pl011_console.S \
+ plat/arm/board/a5ds/a5ds_common.c \
+ plat/arm/common/${ARCH}/arm_helpers.S \
+ plat/arm/common/arm_common.c \
+ plat/arm/common/arm_console.c \
+ plat/arm/board/common/${ARCH}/board_arm_helpers.S
+
+A5DS_CPU_LIBS := lib/cpus/aarch32/cortex_a5.S
+
+BL1_SOURCES += drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ drivers/cfi/v2m/v2m_flash.c \
+ plat/arm/common/arm_bl1_setup.c \
+ plat/arm/common/arm_err.c \
+ plat/arm/common/arm_io_storage.c \
+ plat/arm/board/a5ds/${ARCH}/a5ds_helpers.S \
+ plat/arm/board/a5ds/a5ds_bl1_setup.c \
+ lib/aarch32/arm32_aeabi_divmod.c \
+ lib/aarch32/arm32_aeabi_divmod_a32.S \
+ ${A5DS_CPU_LIBS} \
+ ${DYN_CFG_SOURCES}
+
+BL2_SOURCES += lib/aarch32/arm32_aeabi_divmod.c \
+ lib/aarch32/arm32_aeabi_divmod_a32.S \
+ drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/cfi/v2m/v2m_flash.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ plat/arm/board/a5ds/a5ds_bl2_setup.c \
+ plat/arm/common/arm_bl2_setup.c \
+ plat/arm/common/arm_err.c \
+ plat/arm/common/arm_io_storage.c \
+ plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c \
+ plat/arm/common/arm_image_load.c \
+ common/desc_image_load.c \
+ ${DYN_CFG_SOURCES} \
+ ${A5DS_SECURITY_SOURCES}
+
+# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
+ifdef UNIX_MK
+
+FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/a5ds_tb_fw_config.dtb
+
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config))
+
+$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb, \
+ fdts/$(notdir ${FVP_HW_CONFIG_DTS})))
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config))
+
+FDT_SOURCES += plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts \
+ ${FVP_HW_CONFIG_DTS}
+endif
+
+NEED_BL32 := yes
+
+MULTI_CONSOLE_API := 1
+
+PLAT_BL_COMMON_SOURCES += lib/xlat_tables/aarch32/nonlpae_tables.c
+
+# Use translation tables library v1 when using Cortex-A5
+ARM_XLAT_TABLES_LIB_V1 := 1
+$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
+$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
+
+$(eval $(call assert_boolean,ARM_DISABLE_TRUSTED_WDOG))
+$(eval $(call add_define,ARM_DISABLE_TRUSTED_WDOG))
diff --git a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
new file mode 100644
index 0000000..8b45af8
--- /dev/null
+++ b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+}
+
+/*
+ * A5DS will only have one always-on power domain and there
+ * is no power control present.
+ */
+void plat_arm_pwrc_setup(void)
+{
+}
+
diff --git a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
new file mode 100644
index 0000000..da1d785
--- /dev/null
+++ b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2019, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# SP_MIN source files specific to A5DS platform
+BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \
+ lib/utils/mem_region.c \
+ lib/aarch32/arm32_aeabi_divmod.c \
+ lib/aarch32/arm32_aeabi_divmod_a32.S \
+ plat/arm/board/a5ds/aarch32/a5ds_helpers.S \
+ plat/arm/board/a5ds/a5ds_pm.c \
+ plat/arm/board/a5ds/a5ds_topology.c \
+ plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c \
+ plat/arm/common/sp_min/arm_sp_min_setup.c \
+ plat/common/aarch32/platform_mp_stack.S \
+ plat/common/plat_psci_common.c \
+ ${A5DS_CPU_LIBS} \
+ ${A5DS_GIC_SOURCES} \
+ ${A5DS_SECURITY_SOURCES}
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 3cbdfbc..bd6812b 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -109,9 +109,9 @@
ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_a76ae.S \
+ lib/cpus/aarch64/cortex_a77.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \
- lib/cpus/aarch64/cortex_deimos.S \
lib/cpus/aarch64/neoverse_zeus.S
# AArch64/AArch32
else
diff --git a/plat/hisilicon/hikey/hikey_ddr.c b/plat/hisilicon/hikey/hikey_ddr.c
index e688c15..cd9e9a2 100644
--- a/plat/hisilicon/hikey/hikey_ddr.c
+++ b/plat/hisilicon/hikey/hikey_ddr.c
@@ -138,7 +138,7 @@
mmio_write_32((0xf6504000 + 0x06c), data);
data = mmio_read_32((0xf6504000 + 0x06c));
- data &= ~(0xffffff << 8);
+ data &= ~(0xffffffu << 8);
data |= 0xc7a << 8;
mmio_write_32((0xf6504000 + 0x06c), data);
diff --git a/plat/hisilicon/hikey/include/hi6220_regs_ao.h b/plat/hisilicon/hikey/include/hi6220_regs_ao.h
index 132f33c..614eba2 100644
--- a/plat/hisilicon/hikey/include/hi6220_regs_ao.h
+++ b/plat/hisilicon/hikey/include/hi6220_regs_ao.h
@@ -222,14 +222,14 @@
#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27)
#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28)
#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29)
-#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31)
+#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1U << 31)
#define AO_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26)
#define AO_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27)
#define AO_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28)
#define AO_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29)
#define AO_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30)
-#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31)
+#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1U << 31)
#define AO_SC_SYS_STAT0_MCU_RST_STAT (1 << 25)
#define AO_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26)
@@ -237,7 +237,7 @@
#define AO_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28)
#define AO_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29)
#define AO_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30)
-#define AO_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31)
+#define AO_SC_SYS_STAT0_GLB_SRST_STAT (1U << 31)
#define AO_SC_SYS_STAT1_MODE_STATUS (1 << 0)
#define AO_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16)
@@ -308,7 +308,7 @@
#define AO_SC_PERIPH_CLKEN4_CLK_JTAG_AUTH (1 << 28)
#define AO_SC_PERIPH_CLKEN4_CLK_CS_DAPB_ON (1 << 29)
#define AO_SC_PERIPH_CLKEN4_CLK_PDM (1 << 30)
-#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD (1 << 31)
+#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD (1U << 31)
#define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU (1 << 0)
#define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_CCPU (1 << 1)
diff --git a/plat/hisilicon/hikey/include/hi6220_regs_peri.h b/plat/hisilicon/hikey/include/hi6220_regs_peri.h
index 8711ae4..77236e8 100644
--- a/plat/hisilicon/hikey/include/hi6220_regs_peri.h
+++ b/plat/hisilicon/hikey/include/hi6220_regs_peri.h
@@ -134,7 +134,7 @@
#define PERI_CTRL4_OTG_SESSEND (1 << 28)
#define PERI_CTRL4_OTG_BVALID (1 << 29)
#define PERI_CTRL4_OTG_AVALID (1 << 30)
-#define PERI_CTRL4_OTG_VBUSVALID (1 << 31)
+#define PERI_CTRL4_OTG_VBUSVALID (1U << 31)
/* PERI_SC_PERIPH_CTRL5 */
#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3)
diff --git a/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c b/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c
index bcf6865..91d8033 100644
--- a/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c
+++ b/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c
@@ -23,7 +23,7 @@
#define RES2_LOCK_BASE (SOC_PCTRL_RESOURCE2_LOCK_ADDR(PCTRL_BASE))
#define LOCK_BIT (0x1 << 28)
-#define LOCK_ID_MASK (0x7 << 29)
+#define LOCK_ID_MASK (0x7u << 29)
#define CPUIDLE_LOCK_ID(core) (0x6 - (core))
#define LOCK_UNLOCK_OFFSET 0x4
#define LOCK_STAT_OFFSET 0x8
diff --git a/plat/hisilicon/hikey960/include/hi3660.h b/plat/hisilicon/hikey960/include/hi3660.h
index 5b9305a..7cc1ee0 100644
--- a/plat/hisilicon/hikey960/include/hi3660.h
+++ b/plat/hisilicon/hikey960/include/hi3660.h
@@ -67,7 +67,7 @@
#define SCTRL_SCPERDIS1_REG (SCTRL_REG_BASE + 0x174)
#define SCTRL_SCPEREN1_REG (SCTRL_REG_BASE + 0x170)
#define SCTRL_SCPERDIS1_REG (SCTRL_REG_BASE + 0x174)
-#define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS (1 << 31)
+#define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS (1u << 31)
#define SCPEREN_GT_PCLK_MMBUFCFG (1 << 25)
#define SCPEREN_GT_PCLK_MMBUF (1 << 23)
#define SCPEREN_GT_ACLK_MMBUF (1 << 22)
diff --git a/plat/hisilicon/hikey960/include/hi3660_crg.h b/plat/hisilicon/hikey960/include/hi3660_crg.h
index ec587aa..eb5a6c5 100644
--- a/plat/hisilicon/hikey960/include/hi3660_crg.h
+++ b/plat/hisilicon/hikey960/include/hi3660_crg.h
@@ -11,7 +11,7 @@
#define CRG_PEREN0_REG (CRG_REG_BASE + 0x000)
#define CRG_PERDIS0_REG (CRG_REG_BASE + 0x004)
#define CRG_PERSTAT0_REG (CRG_REG_BASE + 0x008)
-#define PEREN0_GT_CLK_AOMM (1 << 31)
+#define PEREN0_GT_CLK_AOMM (1U << 31)
#define CRG_PEREN1_REG (CRG_REG_BASE + 0x010)
#define CRG_PERDIS1_REG (CRG_REG_BASE + 0x014)
@@ -62,7 +62,7 @@
#define CRG_PERRSTSTAT5_REG (CRG_REG_BASE + 0x0A4)
/* bit fields in CRG_PERI */
-#define PERI_PCLK_PCTRL_BIT (1 << 31)
+#define PERI_PCLK_PCTRL_BIT (1U << 31)
#define PERI_TIMER12_BIT (1 << 25)
#define PERI_TIMER11_BIT (1 << 24)
#define PERI_TIMER10_BIT (1 << 23)
diff --git a/plat/hisilicon/hikey960/include/hi3660_hkadc.h b/plat/hisilicon/hikey960/include/hi3660_hkadc.h
index 4d2de4a..dc9e813 100644
--- a/plat/hisilicon/hikey960/include/hi3660_hkadc.h
+++ b/plat/hisilicon/hikey960/include/hi3660_hkadc.h
@@ -13,7 +13,7 @@
#define HKADC_DSP_START_CLR_REG (HKADC_SSI_REG_BASE + 0x01C)
#define HKADC_WR01_DATA_REG (HKADC_SSI_REG_BASE + 0x020)
-#define WR1_WRITE_MODE (1 << 31)
+#define WR1_WRITE_MODE (1U << 31)
#define WR1_READ_MODE (0 << 31)
#define WR1_ADDR(x) (((x) & 0x7F) << 24)
#define WR1_DATA(x) (((x) & 0xFF) << 16)
@@ -47,7 +47,7 @@
#define HKADC_WR01_VALUE ((HKADC_START_ADDR << 24) | \
(0x1 << 16))
-#define HKADC_WR23_VALUE ((0x1 << 31) | \
+#define HKADC_WR23_VALUE ((0x1u << 31) | \
(HKADC_DATA0_ADDR << 24) | \
(1 << 15) | \
(HKADC_DATA1_ADDR << 8))
diff --git a/plat/imx/common/sci/imx8_mu.h b/plat/imx/common/sci/imx8_mu.h
index edcac7b..7885219 100644
--- a/plat/imx/common/sci/imx8_mu.h
+++ b/plat/imx/common/sci/imx8_mu.h
@@ -13,7 +13,7 @@
#define MU_TR_COUNT1 4
#define MU_RR_COUNT1 4
-#define MU_CR_GIEn_MASK1 (0xF << 28)
+#define MU_CR_GIEn_MASK1 (0xFu << 28)
#define MU_CR_RIEn_MASK1 (0xF << 24)
#define MU_CR_TIEn_MASK1 (0xF << 20)
#define MU_CR_GIRn_MASK1 (0xF << 16)
@@ -23,7 +23,7 @@
#define MU_SR_TE0_MASK1 (1 << 23)
#define MU_SR_RF0_MASK1 (1 << 27)
#define MU_CR_RIE0_MASK1 (1 << 27)
-#define MU_CR_GIE0_MASK1 (1 << 31)
+#define MU_CR_GIE0_MASK1 (1U << 31)
#define MU_TR_COUNT 4
#define MU_RR_COUNT 4
diff --git a/plat/imx/imx8m/imx8m_caam.c b/plat/imx/imx8m/imx8m_caam.c
new file mode 100644
index 0000000..478005e
--- /dev/null
+++ b/plat/imx/imx8m/imx8m_caam.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019, NXP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+
+#include <imx8m_caam.h>
+
+void imx8m_caam_init(void)
+{
+ uint32_t sm_cmd;
+
+ /* Dealloc part 0 and 2 with current DID */
+ sm_cmd = (0 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
+ mmio_write_32(SM_CMD, sm_cmd);
+
+ sm_cmd = (2 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
+ mmio_write_32(SM_CMD, sm_cmd);
+
+ /* config CAAM JRaMID set MID to Cortex A */
+ mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
+ mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
+ mmio_write_32(CAAM_JR2MID, CAAM_NS_MID);
+
+ /* Alloc partition 0 writing SMPO and SMAGs */
+ mmio_write_32(SM_P0_PERM, 0xff);
+ mmio_write_32(SM_P0_SMAG2, 0xffffffff);
+ mmio_write_32(SM_P0_SMAG1, 0xffffffff);
+
+ /* Allocate page 0 and 1 to partition 0 with DID set */
+ sm_cmd = (0 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT |
+ SMC_CMD_ALLOC_PAGE);
+ mmio_write_32(SM_CMD, sm_cmd);
+
+ sm_cmd = (1 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT |
+ SMC_CMD_ALLOC_PAGE);
+ mmio_write_32(SM_CMD, sm_cmd);
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index 8bfb545..63d9223 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -24,6 +24,7 @@
#include <gpc.h>
#include <imx_aipstz.h>
#include <imx_uart.h>
+#include <imx8m_caam.h>
#include <plat_imx8.h>
static const mmap_region_t imx_mmap[] = {
@@ -93,6 +94,8 @@
imx_aipstz_init(aipstz);
+ imx8m_caam_init();
+
console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
/* This console is only used for boot stage */
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index a95ab83..de9e3b5 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -77,6 +77,7 @@
#define IMX_NOC_BASE U(0x32700000)
#define IMX_TZASC_BASE U(0x32F80000)
#define IMX_IOMUX_GPR_BASE U(0x30340000)
+#define IMX_CAAM_BASE U(0x30900000)
#define IMX_DDRC_BASE U(0x3d400000)
#define IMX_DDRPHY_BASE U(0x3c000000)
#define IMX_DDR_IPS_BASE U(0x3d000000)
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index a3d249a..c28463b 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -20,6 +20,7 @@
BL31_SOURCES += plat/imx/common/imx8_helpers.S \
plat/imx/imx8m/gpc_common.c \
plat/imx/imx8m/imx_aipstz.c \
+ plat/imx/imx8m/imx8m_caam.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c \
plat/imx/imx8m/imx8mm/imx8mm_psci.c \
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index ce55d7f..26a3b36 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -24,6 +24,7 @@
#include <gpc.h>
#include <imx_aipstz.h>
#include <imx_uart.h>
+#include <imx8m_caam.h>
#include <plat_imx8.h>
static const mmap_region_t imx_mmap[] = {
@@ -129,10 +130,7 @@
imx_aipstz_init(aipstz);
- /* config CAAM JRaMID set MID to Cortex A */
- mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
- mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
- mmio_write_32(CAAM_JR2MID, CAAM_NS_MID);
+ imx8m_caam_init();
#if DEBUG_CONSOLE
static console_uart_t console;
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 959b820..3c212e3 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -70,6 +70,7 @@
#define IMX_SNVS_BASE U(0x30370000)
#define IMX_NOC_BASE U(0x32700000)
#define IMX_TZASC_BASE U(0x32F80000)
+#define IMX_CAAM_BASE U(0x30900000)
#define IMX_IOMUX_GPR_BASE U(0x30340000)
#define IMX_DDRC_BASE U(0x3d400000)
#define IMX_DDRPHY_BASE U(0x3c000000)
@@ -122,8 +123,3 @@
#define DEBUG_CONSOLE 0
#define IMX_WDOG_B_RESET
-
-#define CAAM_JR0MID U(0x30900010)
-#define CAAM_JR1MID U(0x30900018)
-#define CAAM_JR2MID U(0x30900020)
-#define CAAM_NS_MID U(0x1)
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index d6879bf..44ce555 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -22,6 +22,7 @@
plat/imx/imx8m/imx8mq/imx8mq_psci.c \
plat/imx/imx8m/gpc_common.c \
plat/imx/imx8m/imx_aipstz.c \
+ plat/imx/imx8m/imx8m_caam.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mq/gpc.c \
plat/imx/common/imx8_topology.c \
diff --git a/plat/imx/imx8m/include/imx8m_caam.h b/plat/imx/imx8m/include/imx8m_caam.h
new file mode 100644
index 0000000..84725b1
--- /dev/null
+++ b/plat/imx/imx8m/include/imx8m_caam.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019, NXP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX8M_CAAM_H
+#define IMX8M_CAAM_H
+
+#include <lib/utils_def.h>
+
+#include <platform_def.h>
+
+#define CAAM_JR0MID (IMX_CAAM_BASE + 0x10)
+#define CAAM_JR1MID (IMX_CAAM_BASE + 0x18)
+#define CAAM_JR2MID (IMX_CAAM_BASE + 0x20)
+#define CAAM_NS_MID (0x1)
+
+#define JR0_BASE (IMX_CAAM_BASE + 0x1000)
+
+#define SM_P0_PERM (JR0_BASE + 0xa04)
+#define SM_P0_SMAG2 (JR0_BASE + 0xa08)
+#define SM_P0_SMAG1 (JR0_BASE + 0xa0c)
+#define SM_CMD (JR0_BASE + 0xbe4)
+
+/* secure memory command */
+#define SMC_PAGE_SHIFT 16
+#define SMC_PART_SHIFT 8
+
+#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */
+#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */
+
+void imx8m_caam_init(void);
+
+#endif /* IMX8M_CAAM_H */
diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.h b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h
index 4fb2922..cfef585 100644
--- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.h
+++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h
@@ -34,7 +34,7 @@
#define CAD_QSPI_CFG_CS(x) (((x) << 11))
#define CAD_QSPI_CFG_ENABLE (1 << 0)
#define CAD_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
-#define CAD_QSPI_CFG_IDLE (1 << 31)
+#define CAD_QSPI_CFG_IDLE (1U << 31)
#define CAD_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
#define CAD_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
diff --git a/plat/intel/soc/stratix10/include/s10_mailbox.h b/plat/intel/soc/stratix10/include/s10_mailbox.h
index 78db520..554c265 100644
--- a/plat/intel/soc/stratix10/include/s10_mailbox.h
+++ b/plat/intel/soc/stratix10/include/s10_mailbox.h
@@ -76,7 +76,7 @@
#define RECONFIG_STATUS_STATE 0
#define RECONFIG_STATUS_PIN_STATUS 2
#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
-#define PIN_STATUS_NSTATUS (1 << 31)
+#define PIN_STATUS_NSTATUS (1U << 31)
#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
index 802386c..4500c6f 100644
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@@ -59,6 +59,11 @@
#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
+#define S10_SYSMGR_CORE(x) (0xffd12000 + (x))
+#define SYSMGR_MMC 0x28
+#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0)
+
+
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
void enable_nonsecure_access(void);
diff --git a/plat/intel/soc/stratix10/soc/s10_system_manager.c b/plat/intel/soc/stratix10/soc/s10_system_manager.c
index 48f37d7..a2ed5a3 100644
--- a/plat/intel/soc/stratix10/soc/s10_system_manager.c
+++ b/plat/intel/soc/stratix10/soc/s10_system_manager.c
@@ -86,5 +86,8 @@
mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
+
+ mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3));
+
}
diff --git a/plat/layerscape/board/ls1043/ls1043_psci.c b/plat/layerscape/board/ls1043/ls1043_psci.c
index d6429c3..8e282cb 100644
--- a/plat/layerscape/board/ls1043/ls1043_psci.c
+++ b/plat/layerscape/board/ls1043/ls1043_psci.c
@@ -66,12 +66,12 @@
dsb();
/* enable core soft reset */
mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORESRENCR_OFFSET,
- htobe32(1 << 31));
+ htobe32(1U << 31));
dsb();
isb();
/* reset core */
mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORE0_SFT_RST_OFFSET +
- core_pos * 4, htobe32(1 << 31));
+ core_pos * 4, htobe32(1U << 31));
mdelay(10);
}
diff --git a/plat/layerscape/board/ls1043/ls_gic.c b/plat/layerscape/board/ls1043/ls_gic.c
index 3d8b262..cba55ca 100644
--- a/plat/layerscape/board/ls1043/ls_gic.c
+++ b/plat/layerscape/board/ls1043/ls_gic.c
@@ -35,7 +35,7 @@
soc_dev_id == (SVR_LS1043AE << 8)) &&
((val & 0xff) == REV1_1)) {
val = be32toh(mmio_read_32((uintptr_t)gic_align));
- if (val & (1 << GIC_ADDR_BIT)) {
+ if (val & (1U << GIC_ADDR_BIT)) {
*gicc_base = GICC_BASE;
*gicd_base = GICD_BASE;
} else {
diff --git a/plat/layerscape/common/include/soc.h b/plat/layerscape/common/include/soc.h
index 76c3418..a5dc855 100644
--- a/plat/layerscape/common/include/soc.h
+++ b/plat/layerscape/common/include/soc.h
@@ -9,9 +9,9 @@
#include <stdint.h>
-#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1043A 0x879204
-#define SVR_LS1043AE 0x879200
+#define SVR_WO_E 0xFFFFFEu
+#define SVR_LS1043A 0x879204u
+#define SVR_LS1043AE 0x879200u
void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h
index 8b7cd64..de80315 100644
--- a/plat/marvell/a8k/common/include/a8k_plat_def.h
+++ b/plat/marvell/a8k/common/include/a8k_plat_def.h
@@ -18,7 +18,7 @@
#define GWD_IIDR2_REV_ID_OFFSET 12
#define GWD_IIDR2_REV_ID_MASK 0xF
#define GWD_IIDR2_CHIP_ID_OFFSET 20
-#define GWD_IIDR2_CHIP_ID_MASK (0xFFF << GWD_IIDR2_CHIP_ID_OFFSET)
+#define GWD_IIDR2_CHIP_ID_MASK (0xFFFu << GWD_IIDR2_CHIP_ID_OFFSET)
#define CHIP_ID_AP806 0x806
#define CHIP_ID_AP807 0x807
diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c
index 0590cc0..7f9e242 100644
--- a/plat/marvell/a8k/common/plat_ble_setup.c
+++ b/plat/marvell/a8k/common/plat_ble_setup.c
@@ -77,13 +77,13 @@
/* VDD limit is 0.82V for all A3900 devices
* AVS offsets are not the same as in A70x0
*/
-#define AVS_A3900_CLK_VALUE ((0x80 << 24) | \
+#define AVS_A3900_CLK_VALUE ((0x80u << 24) | \
(0x2c2 << 13) | \
(0x2c2 << 3) | \
(0x1 << AVS_SOFT_RESET_OFFSET) | \
(0x1 << AVS_ENABLE_OFFSET))
/* VDD is 0.88V for 2GHz clock */
-#define AVS_A3900_HIGH_CLK_VALUE ((0x80 << 24) | \
+#define AVS_A3900_HIGH_CLK_VALUE ((0x80u << 24) | \
(0x2f5 << 13) | \
(0x2f5 << 3) | \
(0x1 << AVS_SOFT_RESET_OFFSET) | \
diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c
index e2575b1..d07601a 100644
--- a/plat/marvell/a8k/common/plat_pm.c
+++ b/plat/marvell/a8k/common/plat_pm.c
@@ -93,7 +93,7 @@
#define PWRC_CPUN_CR_ISO_ENABLE_MASK \
(0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)
#define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK \
- (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)
+ (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)
#define CCU_B_PRCRN_REG(cpu_id) \
(MVEBU_REGS_BASE + 0x1A50 + \
@@ -253,7 +253,7 @@
/* 3. Assert power ready */
reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
- reg_val |= 0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET;
+ reg_val |= 0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET;
mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);
/* 4. Read & Validate power ready
@@ -262,7 +262,7 @@
do {
reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
exit_loop--;
- } while (!(reg_val & (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) &&
+ } while (!(reg_val & (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) &&
exit_loop > 0);
if (exit_loop <= 0)
diff --git a/plat/mediatek/mt8183/drivers/mcsi/mcsi.h b/plat/mediatek/mt8183/drivers/mcsi/mcsi.h
index c13e22a..8a588bf 100644
--- a/plat/mediatek/mt8183/drivers/mcsi/mcsi.h
+++ b/plat/mediatek/mt8183/drivers/mcsi/mcsi.h
@@ -41,7 +41,7 @@
#define BD_CTRL_REG 0x40
/* Snoop Control register bit definitions */
-#define DVM_SUPPORT (1 << 31)
+#define DVM_SUPPORT (1U << 31)
#define SNP_SUPPORT (1 << 30)
#define SHAREABLE_OVWRT (1 << 2)
#define DVM_EN_BIT (1 << 1)
diff --git a/plat/mediatek/mt8183/include/mcucfg.h b/plat/mediatek/mt8183/include/mcucfg.h
index c84f2a7..83ee88f 100644
--- a/plat/mediatek/mt8183/include/mcucfg.h
+++ b/plat/mediatek/mt8183/include/mcucfg.h
@@ -197,7 +197,7 @@
MP0_CPUCFG_64BIT_SHIFT = 12,
MP1_CPUCFG_64BIT_SHIFT = 28,
MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
- MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
+ MP1_CPUCFG_64BIT = 0xfu << MP1_CPUCFG_64BIT_SHIFT
};
/* scu related */
diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h
index 7820988..bc9022b 100644
--- a/plat/mediatek/mt8183/include/platform_def.h
+++ b/plat/mediatek/mt8183/include/platform_def.h
@@ -180,7 +180,7 @@
#define MTK_WDT_STATUS_SECURITY_RST (1 << 28)
#define MTK_WDT_STATUS_IRQ_ASSERT (1 << 29)
#define MTK_WDT_STATUS_SW_WDT_RST (1 << 30)
-#define MTK_WDT_STATUS_HW_WDT_RST (1 << 31)
+#define MTK_WDT_STATUS_HW_WDT_RST (1U << 31)
/* RGU other related */
#define MTK_WDT_MODE_DUAL_MODE 0x0040
diff --git a/plat/renesas/rcar/include/rcar_version.h b/plat/renesas/rcar/include/rcar_version.h
index ff56f92..2d400e0 100644
--- a/plat/renesas/rcar/include/rcar_version.h
+++ b/plat/renesas/rcar/include/rcar_version.h
@@ -9,7 +9,7 @@
#include <arch_helpers.h>
-#define VERSION_OF_RENESAS "2.0.3"
+#define VERSION_OF_RENESAS "2.0.4"
#define VERSION_OF_RENESAS_MAXLEN (128)
extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
diff --git a/plat/renesas/rcar/rcar_common.c b/plat/renesas/rcar/rcar_common.c
index d24d71a..4ea753f 100644
--- a/plat/renesas/rcar/rcar_common.c
+++ b/plat/renesas/rcar/rcar_common.c
@@ -18,10 +18,10 @@
#define MSTP318 (1 << 18)
#define MSTP319 (1 << 19)
#define PMSR 0x5c
-#define PMSR_L1FAEG (1 << 31)
+#define PMSR_L1FAEG (1U << 31)
#define PMSR_PMEL1RX (1 << 23)
#define PMCTLR 0x60
-#define PMSR_L1IATN (1 << 31)
+#define PMSR_L1IATN (1U << 31)
static int rcar_pcie_fixup(unsigned int controller)
{
diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c
index c215ee2..a17fef9 100644
--- a/plat/rockchip/rk3328/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c
@@ -284,7 +284,7 @@
static inline void pll_pwr_dwn(uint32_t pll_id, uint32_t pd)
{
mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1),
- BITS_WITH_WMASK(1, 1, 15));
+ BITS_WITH_WMASK(1U, 1U, 15));
if (pd)
mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1),
BITS_WITH_WMASK(1, 1, 14));
@@ -305,7 +305,7 @@
sram_data.dpll_con_save[i] =
mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, i));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
- BITS_WITH_WMASK(1, 1, 15));
+ BITS_WITH_WMASK(1U, 1U, 15));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(1, 1, 14));
}
@@ -315,7 +315,7 @@
uint32_t delay = PLL_LOCKED_TIMEOUT;
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
- BITS_WITH_WMASK(1, 1, 15));
+ BITS_WITH_WMASK(1U, 1U, 15));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(0, 1, 14));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
@@ -402,7 +402,7 @@
/* clk_rtc32k */
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38),
BITS_WITH_WMASK(767, 0x3fff, 0) |
- BITS_WITH_WMASK(2, 0x3, 14));
+ BITS_WITH_WMASK(2U, 0x3u, 14));
}
static void pm_plls_resume(void)
@@ -411,7 +411,7 @@
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38),
ddr_data.clk_sel38 |
BITS_WMSK(0x3fff, 0) |
- BITS_WMSK(0x3, 14));
+ BITS_WMSK(0x3u, 14));
/* uart2 */
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(18),
@@ -483,7 +483,7 @@
mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]);
mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]);
mmio_write_32(GRF_BASE + PMIC_SLEEP_REG,
- sram_data.pmic_sleep_save | BITS_WMSK(0xffff, 0));
+ sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0));
/* Resuming volt need a lot of time */
sram_udelay(100);
}
diff --git a/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c b/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c
index 84d2654..fa98eb3 100644
--- a/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c
+++ b/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c
@@ -400,7 +400,7 @@
p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 0))
& 0xffff) |
- (0xFFFF << 16);
+ (0xFFFFu << 16);
p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 1))
& 0xffff);
@@ -410,7 +410,7 @@
p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 3))
& 0xffff) |
- (0xFFFF << 16);
+ (0xFFFFu << 16);
} else {
ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]);
}
diff --git a/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h b/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h
index 15912b5..6663bcb 100644
--- a/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h
+++ b/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h
@@ -222,7 +222,7 @@
#define DDRPHY0_SRSTN_REQ(n) (((0x1 << 0) << 16) | (n << 0))
/* CRU_DPLL_CON2 */
-#define DPLL_STATUS_LOCK (1 << 31)
+#define DPLL_STATUS_LOCK (1U << 31)
/* CRU_DPLL_CON3 */
#define DPLL_POWER_DOWN ((0x1 << (1 + 16)) | (0 << 1))
@@ -237,7 +237,7 @@
#define DDR_PLL_SRC_MASK 0x13
/* DDR_PCTL_TREFI */
-#define DDR_UPD_REF_ENABLE (0X1 << 31)
+#define DDR_UPD_REF_ENABLE (0X1u << 31)
uint32_t ddr_get_resume_code_size(void);
uint32_t ddr_get_resume_data_size(void);
diff --git a/plat/rockchip/rk3368/drivers/soc/soc.h b/plat/rockchip/rk3368/drivers/soc/soc.h
index 5f24e93..6c7a01b 100644
--- a/plat/rockchip/rk3368/drivers/soc/soc.h
+++ b/plat/rockchip/rk3368/drivers/soc/soc.h
@@ -50,7 +50,7 @@
#define PMUSRAM_S 1
#define STIMER_S_SHIFT 6
#define STIMER_S 1
-#define SGRF_SOC_CON7_BITS ((0xffff << 16) | \
+#define SGRF_SOC_CON7_BITS ((0xffffu << 16) | \
(PMUSRAM_S << PMUSRAM_S_SHIFT) | \
(STIMER_S << STIMER_S_SHIFT))
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index 45fd924..3b627d2 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -504,7 +504,7 @@
(pdram_timing->tmod << 8) |
pdram_timing->tmrd);
- mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
(pdram_timing->txsr -
pdram_timing->trcd) << 16);
} else if (timing_config->dram_type == LPDDR4) {
@@ -513,7 +513,7 @@
mmio_write_32(CTL_REG(i, 32),
(pdram_timing->tmrd << 8) |
pdram_timing->tmrd);
- mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
pdram_timing->txsr << 16);
} else {
mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1);
@@ -521,7 +521,7 @@
mmio_write_32(CTL_REG(i, 32),
(pdram_timing->tmrd << 8) |
pdram_timing->tmrd);
- mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
pdram_timing->txsr << 16);
}
mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3);
@@ -531,7 +531,7 @@
mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24),
(pdram_timing->cwl << 24));
mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al);
- mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16,
(pdram_timing->trc << 24) |
(pdram_timing->trrd << 16));
mmio_write_32(CTL_REG(i, 27),
@@ -540,7 +540,7 @@
(pdram_timing->twtr << 8) |
pdram_timing->tras_min);
- mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24,
+ mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24,
max(4, pdram_timing->trtp) << 24);
mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) |
pdram_timing->tras_max);
@@ -560,7 +560,7 @@
((pdram_timing->trefi - 8) << 16) |
pdram_timing->trfc);
mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp);
- mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 53), 0xffffu << 16,
pdram_timing->txpdll << 16);
mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24,
pdram_timing->tcscke << 24);
@@ -571,7 +571,7 @@
(pdram_timing->tckehcs << 8) |
pdram_timing->tckelcs);
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr);
- mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 62), 0xffffu << 16,
(pdram_timing->tckehcmd << 24) |
(pdram_timing->tckelcmd << 16));
mmio_write_32(CTL_REG(i, 63),
@@ -601,7 +601,7 @@
pdram_timing->mr[2]);
mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff,
pdram_timing->mr[3]);
- mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24,
+ mmio_clrsetbits_32(CTL_REG(i, 139), 0xffu << 24,
pdram_timing->mr11 << 24);
mmio_write_32(CTL_REG(i, 147),
(pdram_timing->mr[1] << 16) |
@@ -610,20 +610,20 @@
pdram_timing->mr[2]);
mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff,
pdram_timing->mr[3]);
- mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24,
+ mmio_clrsetbits_32(CTL_REG(i, 153), 0xffu << 24,
pdram_timing->mr11 << 24);
if (timing_config->dram_type == LPDDR4) {
- mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 140), 0xffffu << 16,
pdram_timing->mr12 << 16);
- mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 142), 0xffffu << 16,
pdram_timing->mr14 << 16);
- mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 145), 0xffffu << 16,
pdram_timing->mr22 << 16);
- mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 154), 0xffffu << 16,
pdram_timing->mr12 << 16);
- mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 156), 0xffffu << 16,
pdram_timing->mr14 << 16);
- mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 159), 0xffffu << 16,
pdram_timing->mr22 << 16);
}
mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8,
@@ -655,7 +655,7 @@
<< 8) | get_rdlat_adj(timing_config->dram_type,
pdram_timing->cl);
mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp);
- mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 82), 0xffffu << 16,
(4 * pdram_timing->trefi) << 16);
mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff,
@@ -748,13 +748,13 @@
tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
pdram_timing->tmod + pdram_timing->tzqinit;
mmio_write_32(CTL_REG(i, 9), tmp);
- mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 22), 0xffffu << 16,
pdram_timing->tdllk << 16);
mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00,
(pdram_timing->tmod << 24) |
(pdram_timing->tmrd << 16) |
(pdram_timing->trtp << 8));
- mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
(pdram_timing->txsr -
pdram_timing->trcd) << 16);
} else if (timing_config->dram_type == LPDDR4) {
@@ -764,7 +764,7 @@
(pdram_timing->tmrd << 24) |
(pdram_timing->tmrd << 16) |
(pdram_timing->trtp << 8));
- mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
pdram_timing->txsr << 16);
} else {
mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1);
@@ -773,7 +773,7 @@
(pdram_timing->tmrd << 24) |
(pdram_timing->tmrd << 16) |
(pdram_timing->trtp << 8));
- mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
pdram_timing->txsr << 16);
}
mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3);
@@ -796,7 +796,7 @@
pdram_timing->tras_max);
mmio_clrsetbits_32(CTL_REG(i, 36), 0xff,
max(1, pdram_timing->tckesr));
- mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24),
+ mmio_clrsetbits_32(CTL_REG(i, 39), (0xffu << 24),
(pdram_timing->trcd << 24));
mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr);
mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24,
@@ -809,7 +809,7 @@
mmio_write_32(CTL_REG(i, 49),
((pdram_timing->trefi - 8) << 16) |
pdram_timing->trfc);
- mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 52), 0xffffu << 16,
pdram_timing->txp << 16);
mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff,
pdram_timing->txpdll);
@@ -821,7 +821,7 @@
pdram_timing->tcscke);
mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke);
mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr);
- mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 64), 0xffffu << 16,
(pdram_timing->tckehcmd << 24) |
(pdram_timing->tckelcmd << 16));
mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) |
@@ -831,7 +831,7 @@
mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff,
(pdram_timing->tcmdcke << 8) |
pdram_timing->tcsckeh);
- mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24),
+ mmio_clrsetbits_32(CTL_REG(i, 92), (0xffu << 24),
(pdram_timing->tcksre << 24));
mmio_clrsetbits_32(CTL_REG(i, 93), 0xff,
pdram_timing->tcksrx);
@@ -845,18 +845,18 @@
pdram_timing->tfc_long);
mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff,
pdram_timing->tvref_long);
- mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 134), 0xffffu << 16,
pdram_timing->mr[0] << 16);
mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) |
pdram_timing->mr[1]);
- mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 138), 0xffffu << 16,
pdram_timing->mr[3] << 16);
mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11);
- mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 148), 0xffffu << 16,
pdram_timing->mr[0] << 16);
mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) |
pdram_timing->mr[1]);
- mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 152), 0xffffu << 16,
pdram_timing->mr[3] << 16);
mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11);
if (timing_config->dram_type == LPDDR4) {
@@ -907,7 +907,7 @@
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff,
(4 * pdram_timing->trefi) & 0xffff);
- mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 84), 0xffffu << 16,
((2 * pdram_timing->trefi) & 0xffff) << 16);
if ((timing_config->dram_type == LPDDR3) ||
@@ -936,12 +936,12 @@
mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16,
(tmp & 0x3f) << 16);
- mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24,
+ mmio_clrsetbits_32(CTL_REG(i, 275), 0xffu << 24,
(get_pi_tdfi_phy_rdlat(pdram_timing,
timing_config) &
0xff) << 24);
- mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16,
+ mmio_clrsetbits_32(CTL_REG(i, 284), 0xffffu << 16,
((2 * pdram_timing->trefi) & 0xffff) << 16);
mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff,
@@ -973,7 +973,7 @@
tmp = tmp1 - 2;
}
- mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24);
+ mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24);
/* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */
if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) &&
@@ -1036,7 +1036,7 @@
tmp = 2 * pdram_timing->trefi;
mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp);
/* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */
- mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16);
+ mmio_clrsetbits_32(PI_REG(i, 7), 0xffffu << 16, tmp << 16);
/* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */
if (timing_config->dram_type == LPDDR4)
@@ -1060,14 +1060,14 @@
mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16,
(pdram_timing->cl * 2) << 16);
/* PI_46 PI_TREF_F0:RW:16:16 */
- mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16,
+ mmio_clrsetbits_32(PI_REG(i, 46), 0xffffu << 16,
pdram_timing->trefi << 16);
/* PI_46 PI_TRFC_F0:RW:0:10 */
mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc);
/* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */
if (timing_config->dram_type == LPDDR3) {
tmp = get_pi_todtoff_max(pdram_timing, timing_config);
- mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24,
+ mmio_clrsetbits_32(PI_REG(i, 66), 0xffu << 24,
tmp << 24);
}
/* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */
@@ -1148,19 +1148,19 @@
/* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]);
/* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */
- mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16,
+ mmio_clrsetbits_32(PI_REG(i, 140), 0xffffu << 16,
pdram_timing->mr[1] << 16);
/* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]);
/* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]);
/* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */
- mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16,
+ mmio_clrsetbits_32(PI_REG(i, 133), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]);
/* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */
- mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16,
+ mmio_clrsetbits_32(PI_REG(i, 148), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_156 PI_TFC_F0:RW:0:10 */
mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff,
@@ -1177,10 +1177,10 @@
/* PI_158 PI_TRP_F0:RW:0:8 */
mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp);
/* PI_157 PI_TRTP_F0:RW:24:8 */
- mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24,
+ mmio_clrsetbits_32(PI_REG(i, 157), 0xffu << 24,
pdram_timing->trtp << 24);
/* PI_159 PI_TRAS_MIN_F0:RW:24:8 */
- mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24,
+ mmio_clrsetbits_32(PI_REG(i, 159), 0xffu << 24,
pdram_timing->tras_min << 24);
/* PI_159 PI_TRAS_MAX_F0:RW:0:17 */
tmp = pdram_timing->tras_max * 99 / 100;
@@ -1237,7 +1237,7 @@
mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8,
(pdram_timing->cl * 2) << 8);
/* PI_47 PI_TREF_F1:RW:16:16 */
- mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16,
+ mmio_clrsetbits_32(PI_REG(i, 47), 0xffffu << 16,
pdram_timing->trefi << 16);
/* PI_47 PI_TRFC_F1:RW:0:10 */
mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc);
@@ -1278,10 +1278,10 @@
mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16);
/*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */
tmp = get_pi_rdlat_adj(pdram_timing);
- mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24);
+ mmio_clrsetbits_32(PI_REG(i, 89), 0xffu << 24, tmp << 24);
/* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */
tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
- mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24);
+ mmio_clrsetbits_32(PI_REG(i, 90), 0xffu << 24, tmp << 24);
/* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */
tmp1 = tmp;
if (tmp1 == 0)
@@ -1290,7 +1290,7 @@
tmp = tmp1 - 1;
else
tmp = tmp1 - 5;
- mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24);
+ mmio_clrsetbits_32(PI_REG(i, 91), 0xffu << 24, tmp << 24);
/*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */
/* tadr=20ns */
tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
@@ -1333,12 +1333,12 @@
mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8,
pdram_timing->mr[1] << 8);
/* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */
- mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16,
+ mmio_clrsetbits_32(PI_REG(i, 128), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]);
/* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */
- mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16,
+ mmio_clrsetbits_32(PI_REG(i, 143), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]);
@@ -1351,7 +1351,7 @@
/* PI_162 PI_TWTR_F1:RW:0:6 */
mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr);
/* PI_161 PI_TRCD_F1:RW:24:8 */
- mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24,
+ mmio_clrsetbits_32(PI_REG(i, 161), 0xffu << 24,
pdram_timing->trcd << 24);
/* PI_161 PI_TRP_F1:RW:16:8 */
mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16,
@@ -1360,7 +1360,7 @@
mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8,
pdram_timing->trtp << 8);
/* PI_163 PI_TRAS_MIN_F1:RW:24:8 */
- mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24,
+ mmio_clrsetbits_32(PI_REG(i, 163), 0xffu << 24,
pdram_timing->tras_min << 24);
/* PI_163 PI_TRAS_MAX_F1:RW:0:17 */
mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff,
@@ -1765,7 +1765,7 @@
0x40) {
while (mmio_read_32(CTL_REG(i, 200)) & 0x1)
;
- mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24,
+ mmio_clrsetbits_32(CTL_REG(i, 93), 0xffu << 24,
0x69 << 24);
while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) !=
0x40)
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c
index 8bc66e1..7f9fad1 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.c
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.c
@@ -172,7 +172,7 @@
mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16,
1 << 16);
mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)),
- 0xffff << 16,
+ 0xffffu << 16,
0x200 << 16);
}
@@ -656,7 +656,7 @@
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
- (1 << 31)) == 0x0)
+ (1U << 31)) == 0x0)
;
}
diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
index d919fa1..cad76ac 100644
--- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
+++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
@@ -45,10 +45,10 @@
/* set the execute address for M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
BITS_WITH_WMASK((addr >> 12) & 0xffff,
- 0xffff, 0));
+ 0xffffu, 0));
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
BITS_WITH_WMASK((addr >> 28) & 0xf,
- 0xf, 0));
+ 0xfu, 0));
}
void m0_start(void)
diff --git a/plat/socionext/synquacer/include/plat.ld.S b/plat/socionext/synquacer/include/plat.ld.S
index 1b7f699..a06fe2a 100644
--- a/plat/socionext/synquacer/include/plat.ld.S
+++ b/plat/socionext/synquacer/include/plat.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#ifndef SYNQUACER_PLAT_LD_S__
#define SYNQUACER_PLAT_LD_S__
-#include <xlat_tables_defs.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
#define SPM_SHIM_EXCEPTIONS_VMA SP_DRAM
diff --git a/readme.rst b/readme.rst
index 84c8020..6c93a4c 100644
--- a/readme.rst
+++ b/readme.rst
@@ -198,8 +198,8 @@
- ``FVP_Base_Cortex-A76x4``
- ``FVP_Base_Cortex-A76AEx4``
- ``FVP_Base_Cortex-A76AEx8``
+- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
- ``FVP_Base_Neoverse-N1x4``
-- ``FVP_Base_Deimos``
- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
diff --git a/services/spd/opteed/teesmc_opteed.h b/services/spd/opteed/teesmc_opteed.h
index ec821ba..c82b58a 100644
--- a/services/spd/opteed/teesmc_opteed.h
+++ b/services/spd/opteed/teesmc_opteed.h
@@ -17,7 +17,7 @@
* full 64 bit values in the argument registers if invoked from Aarch64
* mode. This violates the SMC Calling Convention, but since this
* convention only coveres API towards Normal World it's something that
- * only concerns the OP-TEE Dispatcher in ARM Trusted Firmware and OP-TEE
+ * only concerns the OP-TEE Dispatcher in Trusted Firmware-A and OP-TEE
* OS at Secure EL1.
*/
