rcar_gen3: plat: Disable IPMMU PV0 cache on E3
Disable the IPMMU PV0 cache on E3 rev. 1.x .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index 99f98f3..52dfb40 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -264,6 +264,7 @@
} else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) ||
(product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
+ mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
}
diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h
index 3dbd3f5..1829e59 100644
--- a/plat/renesas/rcar/include/rcar_def.h
+++ b/plat/renesas/rcar/include/rcar_def.h
@@ -231,6 +231,8 @@
#define IPMMUMM_IMSCTLR_ENABLE (0xC0000000U)
#define IPMMUMM_IMAUXCTLR_NMERGE40_BIT (0x01000000U)
#define IMSCTLR_DISCACHE (0xE0000000U)
+#define IPMMU_VP0_BASE (0xFE990000U)
+#define IPMMUVP0_IMSCTLR (IPMMU_VP0_BASE + 0x0500U)
#define IPMMU_VI0_BASE (0xFEBD0000U)
#define IPMMUVI0_IMSCTLR (IPMMU_VI0_BASE + 0x0500U)
#define IPMMU_VI1_BASE (0xFEBE0000U)