Merge changes I8d334231,Icd1ce8ec,Ic963c21c into integration
* changes:
feat(tc0): add cpu capacity to provide scheduling information
fix(tc0): remove "arm,psci" from psci node
feat(tc0): update mhuv2 dts node to align with upstream driver
diff --git a/Makefile b/Makefile
index 017fc65..c290c8c 100644
--- a/Makefile
+++ b/Makefile
@@ -334,7 +334,7 @@
# General warnings
WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
- -Wdisabled-optimization -Wvla -Wshadow \
+ -Wdisabled-optimization -Wvla -Wshadow \
-Wno-unused-parameter -Wredundant-decls
# Additional warnings
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 58b0572..fc853f3 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -275,6 +275,9 @@
CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
issue but there is no workaround for that revision.
+- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
+ CPU. This needs to be enabled for revisions r0p0 and r1p0.
+
For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
diff --git a/drivers/arm/css/scmi/scmi_common.c b/drivers/arm/css/scmi/scmi_common.c
index 5b3724a..ec749fb 100644
--- a/drivers/arm/css/scmi/scmi_common.c
+++ b/drivers/arm/css/scmi/scmi_common.c
@@ -173,12 +173,12 @@
ret = scmi_proto_version(ch, SCMI_PWR_DMN_PROTO_ID, &version);
if (ret != SCMI_E_SUCCESS) {
- WARN("SCMI power domain protocol version message failed");
+ WARN("SCMI power domain protocol version message failed\n");
goto error;
}
if (!is_scmi_version_compatible(SCMI_PWR_DMN_PROTO_VER, version)) {
- WARN("SCMI power domain protocol version 0x%x incompatible with driver version 0x%x",
+ WARN("SCMI power domain protocol version 0x%x incompatible with driver version 0x%x\n",
version, SCMI_PWR_DMN_PROTO_VER);
goto error;
}
@@ -187,12 +187,12 @@
ret = scmi_proto_version(ch, SCMI_SYS_PWR_PROTO_ID, &version);
if ((ret != SCMI_E_SUCCESS)) {
- WARN("SCMI system power protocol version message failed");
+ WARN("SCMI system power protocol version message failed\n");
goto error;
}
if (!is_scmi_version_compatible(SCMI_SYS_PWR_PROTO_VER, version)) {
- WARN("SCMI system power management protocol version 0x%x incompatible with driver version 0x%x",
+ WARN("SCMI system power management protocol version 0x%x incompatible with driver version 0x%x\n",
version, SCMI_SYS_PWR_PROTO_VER);
goto error;
}
diff --git a/drivers/mtd/nor/spi_nor.c b/drivers/mtd/nor/spi_nor.c
index 108f893..8111efd 100644
--- a/drivers/mtd/nor/spi_nor.c
+++ b/drivers/mtd/nor/spi_nor.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -103,7 +103,7 @@
0 : 1;
}
- return (((sr & SR_WIP) != 0U) ? 1 : 0);
+ return (((sr & SR_WIP) == 0U) ? 0 : 1);
}
static int spi_nor_wait_ready(void)
@@ -141,7 +141,7 @@
}
sr |= SR_QUAD_EN_MX;
- ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1, SPI_MEM_DATA_OUT);
+ ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1U, SPI_MEM_DATA_OUT);
if (ret != 0) {
return ret;
}
@@ -168,7 +168,7 @@
return ret;
}
- ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2, SPI_MEM_DATA_OUT);
+ ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2U, SPI_MEM_DATA_OUT);
if (ret != 0) {
return -EINVAL;
}
@@ -230,7 +230,7 @@
}
return spi_nor_reg(nor_dev.bank_write_cmd, &nor_dev.selected_bank,
- 1, SPI_MEM_DATA_OUT);
+ 1U, SPI_MEM_DATA_OUT);
}
static int spi_nor_write_bar(uint32_t offset)
@@ -248,7 +248,7 @@
}
ret = spi_nor_reg(nor_dev.bank_write_cmd, &selected_bank,
- 1, SPI_MEM_DATA_OUT);
+ 1U, SPI_MEM_DATA_OUT);
if (ret != 0) {
return ret;
}
@@ -260,11 +260,11 @@
static int spi_nor_read_bar(void)
{
- uint8_t selected_bank = 0;
+ uint8_t selected_bank = 0U;
int ret;
ret = spi_nor_reg(nor_dev.bank_read_cmd, &selected_bank,
- 1, SPI_MEM_DATA_IN);
+ 1U, SPI_MEM_DATA_IN);
if (ret != 0) {
return ret;
}
@@ -280,7 +280,7 @@
size_t remain_len;
int ret;
- *length_read = 0;
+ *length_read = 0U;
nor_dev.read_op.addr.val = offset;
nor_dev.read_op.data.buf = (void *)buffer;
@@ -324,7 +324,7 @@
int spi_nor_init(unsigned long long *size, unsigned int *erase_size)
{
- int ret = 0;
+ int ret;
uint8_t id;
/* Default read command used */
@@ -339,7 +339,7 @@
return -EINVAL;
}
- assert(nor_dev.size != 0);
+ assert(nor_dev.size != 0U);
if (nor_dev.size > BANK_SIZE) {
nor_dev.flags |= SPI_NOR_USE_BANK;
diff --git a/fdts/tc0.dts b/fdts/tc0.dts
index 92afb76..24e2496 100644
--- a/fdts/tc0.dts
+++ b/fdts/tc0.dts
@@ -17,6 +17,7 @@
};
chosen {
+ bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
stdout-path = "serial0:115200n8";
};
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index caa5120..4bc49f3 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -30,6 +30,7 @@
#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
+#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index f61726b..8c5a45a 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -44,13 +44,13 @@
b cpu_rev_var_ls
endfunc check_errata_1688305
- /* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata #1941498.
- * This applies to revisions r0p0, r1p0, and r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
+/* --------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata #1941498.
+ * This applies to revisions r0p0, r1p0, and r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
func errata_a78_1941498_wa
/* Compare x0 against revision <= r1p1 */
mov x17, x30
@@ -72,16 +72,16 @@
b cpu_rev_var_ls
endfunc check_errata_1941498
- /* --------------------------------------------------
- * Errata Workaround for A78 Erratum 1951500.
- * This applies to revisions r1p0 and r1p1 of A78.
- * The issue also exists in r0p0 but there is no fix
- * in that revision.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
+/* --------------------------------------------------
+ * Errata Workaround for A78 Erratum 1951500.
+ * This applies to revisions r1p0 and r1p1 of A78.
+ * The issue also exists in r0p0 but there is no fix
+ * in that revision.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
func errata_a78_1951500_wa
/* Compare x0 against revisions r1p0 - r1p1 */
mov x17, x30
@@ -126,6 +126,34 @@
b cpu_rev_var_range
endfunc check_errata_1951500
+/* --------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata #1821534.
+ * This applies to revisions r0p0 and r1p0.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78_1821534_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_1821534
+ cbz x0, 1f
+
+ /* Set bit 2 in ACTLR2_EL1 */
+ mrs x1, CORTEX_A78_ACTLR2_EL1
+ orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
+ msr CORTEX_A78_ACTLR2_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_a78_1821534_wa
+
+func check_errata_1821534
+ /* Applies to r0p0 and r1p0 */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_1821534
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A78
* -------------------------------------------------
@@ -150,6 +178,11 @@
bl errata_a78_1951500_wa
#endif
+#if ERRATA_A78_1821534
+ mov x0, x18
+ bl errata_a78_1821534_wa
+#endif
+
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@@ -207,6 +240,7 @@
report_errata ERRATA_A78_1688305, cortex_a78, 1688305
report_errata ERRATA_A78_1941498, cortex_a78, 1941498
report_errata ERRATA_A78_1951500, cortex_a78, 1951500
+ report_errata ERRATA_A78_1821534, cortex_a78, 1821534
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index fb33346..541a2a2 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -307,6 +307,10 @@
# well but there is no workaround for that revision.
ERRATA_A78_1951500 ?=0
+# Flag to apply erratum 1821534 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the A78 cpu.
+ERRATA_A78_1821534 ?=0
+
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_N1_1043202 ?=0
@@ -605,6 +609,10 @@
$(eval $(call assert_boolean,ERRATA_A78_1951500))
$(eval $(call add_define,ERRATA_A78_1951500))
+# Process ERRATA_A78_1821534 flag
+$(eval $(call assert_boolean,ERRATA_A78_1821534))
+$(eval $(call add_define,ERRATA_A78_1821534))
+
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_N1_1043202))