refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants
The register at offset 0x1C1 is called Reset and Clock Control in
functional specification, but we use constant name GLOB_PHY_CTRL0.
Rename it to RST_CLK_CTRL instead.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I5dac8913bd0686d4f5bd74b91cb7d07ba06df72b
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 19a10ac..c8ac8d5 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -162,8 +162,8 @@
#define LANE_CFG4_ADDR(unit) (COMPHY_LANE_CFG4 * PHY_SHFT(unit))
#define SPREAD_SPECTRUM_CLK_EN BIT(7)
-#define COMPHY_GLOB_PHY_CTRL0 0x1C1
-#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_GLOB_PHY_CTRL0 * PHY_SHFT(unit))
+#define COMPHY_RST_CLK_CTRL 0x1C1
+#define RST_CLK_CTRL_ADDR(unit) (COMPHY_RST_CLK_CTRL * PHY_SHFT(unit))
#define SOFT_RESET BIT(0)
#define MODE_CORE_CLK_FREQ_SEL BIT(9)
#define MODE_PIPE_WIDTH_32 BIT(3)