Tegra194: toggle SE clock during context save/restore
This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called during System Suspend/Resume.
Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7
Signed-off-by: steven kao <skao@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index a98aa2d..da8056b 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -152,6 +152,14 @@
#define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
/*******************************************************************************
+ * Tegra HSP doorbell #0 constants
+ ******************************************************************************/
+#define TEGRA_HSP_DBELL_BASE U(0x03C90000)
+#define HSP_DBELL_1_ENABLE U(0x104)
+#define HSP_DBELL_3_TRIGGER U(0x300)
+#define HSP_DBELL_3_ENABLE U(0x304)
+
+/*******************************************************************************
* Tegra hardware synchronization primitives for the SPE engine
******************************************************************************/
#define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000)
@@ -207,6 +215,13 @@
#define TEGRA_TZRAM_SIZE U(0x40000)
/*******************************************************************************
+ * Tegra CCPLEX-BPMP IPC constants
+ ******************************************************************************/
+#define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000)
+#define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000)
+#define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */
+
+/*******************************************************************************
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x20000000)
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
index a9f4610..3a2e959 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#include <stdbool.h>
#include <arch_helpers.h>
+#include <bpmp_ipc.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
@@ -181,6 +182,12 @@
{
int32_t ret = 0;
+ /* initialise communication channel with BPMP */
+ assert(tegra_bpmp_ipc_init() == 0);
+
+ /* Enable SE clock before SE context save */
+ tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+
/* save SE registers */
se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL);
@@ -193,6 +200,9 @@
ERROR("%s: context save failed (%d)\n", __func__, ret);
}
+ /* Disable SE clock after SE context save */
+ tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+
return ret;
}
@@ -201,6 +211,12 @@
*/
void tegra_se_resume(void)
{
+ /* initialise communication channel with BPMP */
+ assert(tegra_bpmp_ipc_init() == 0);
+
+ /* Enable SE clock before SE context restore */
+ tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+
/*
* When TZ takes over after System Resume, TZ should first reconfigure
* SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT,
@@ -211,4 +227,7 @@
mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]);
mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]);
mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
+
+ /* Disable SE clock after SE context restore */
+ tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
}
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index 3b58244..38c737d 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -86,6 +86,8 @@
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
@@ -94,6 +96,8 @@
MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
#endif
+ MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */
+ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index f114b7e..1389f8f 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -38,6 +38,8 @@
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
+ ${COMMON_DIR}/drivers/bpmp_ipc/intf.c \
+ ${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \
${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
${COMMON_DIR}/drivers/smmu/smmu.c \
${SOC_DIR}/drivers/mce/mce.c \