commit e55c27bbd718ad6abb72aab9919d9b94210cfd65
author Varun Wadekar <vwadekar@nvidia.com> Thu Sep 13 08:47:43 2018 -0700
committer Varun Wadekar <vwadekar@nvidia.com> Wed Mar 11 13:37:26 2020 -0700
tree 309e10d36f01fa8e6d7fd6ae5fce38012f98cf40
parent aa4e3f22bed672f7fd1901a8e413b94940c9067e

Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.

Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

plat/nvidia/tegra/soc/t186/plat_psci_handlers.c

diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index a0879cc..f034bdb 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -294,7 +294,7 @@
 		assert(tegra_bpmp_ipc_init() == 0);
 
 		/* Enable SE clock */
-		ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+		ret = tegra_bpmp_ipc_enable_clock(TEGRA186_CLK_SE);
 		if (ret != 0) {
 			ERROR("Failed to enable clock\n");
 			return ret;
@@ -319,7 +319,7 @@
 		memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
 			 (uintptr_t)BL31_END - (uintptr_t)BL31_BASE);
 
-		ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+		ret = tegra_bpmp_ipc_disable_clock(TEGRA186_CLK_SE);
 		if (ret != 0) {
 			ERROR("Failed to disable clock\n");
 			return ret;

plat/nvidia/tegra/soc/t194/drivers/se/se.c

diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
index 0069e3f..ccdc94d 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
@@ -459,7 +459,7 @@
 	assert(tegra_bpmp_ipc_init() == 0);
 
 	/* Enable SE clock before SE context save */
-	ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+	ret = tegra_bpmp_ipc_enable_clock(TEGRA194_CLK_SE);
 	assert(ret == 0);
 
 	/* save SE registers */
@@ -475,7 +475,7 @@
 	}
 
 	/* Disable SE clock after SE context save */
-	ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+	ret = tegra_bpmp_ipc_disable_clock(TEGRA194_CLK_SE);
 	assert(ret == 0);
 
 	return ret;
@@ -492,7 +492,7 @@
 	assert(tegra_bpmp_ipc_init() == 0);
 
 	/* Enable SE clock before SE context restore */
-	ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+	ret = tegra_bpmp_ipc_enable_clock(TEGRA194_CLK_SE);
 	assert(ret == 0);
 
 	/*
@@ -507,6 +507,6 @@
 	mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
 
 	/* Disable SE clock after SE context restore */
-	ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+	ret = tegra_bpmp_ipc_disable_clock(TEGRA194_CLK_SE);
 	assert(ret == 0);
 }

plat/nvidia/tegra/soc/t194/plat_psci_handlers.c

diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 7af3b32..3c91af4 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -304,7 +304,7 @@
 		assert(ret == 0);
 
 		/* Enable SE clock before SE context save */
-		ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+		ret = tegra_bpmp_ipc_enable_clock(TEGRA194_CLK_SE);
 		assert(ret == 0);
 
 		/*
@@ -330,7 +330,7 @@
 		       src_len_in_bytes);
 
 		/* Disable SE clock after SE context save */
-		ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+		ret = tegra_bpmp_ipc_disable_clock(TEGRA194_CLK_SE);
 		assert(ret == 0);
 	}