Merge "feat(mt8196): add SMMU driver for PM" into integration
diff --git a/.github/dependabot.yml b/.github/dependabot.yml
index b565bcb..4c610ad 100644
--- a/.github/dependabot.yml
+++ b/.github/dependabot.yml
@@ -5,33 +5,57 @@
directories: ["/"]
schedule:
interval: "daily"
+ groups:
+ dev-deps:
+ patterns: ["*"]
+ update-types: ["major", "minor", "patch"]
- target-branch: "lts-v2.10"
package-ecosystem: "npm"
directories: ["/"]
schedule:
interval: "daily"
+ groups:
+ dev-deps:
+ patterns: ["*"]
+ update-types: ["patch"]
- target-branch: "lts-v2.8"
package-ecosystem: "npm"
directories: ["/"]
schedule:
interval: "daily"
+ groups:
+ dev-deps:
+ patterns: ["*"]
+ update-types: ["patch"]
- target-branch: "main"
package-ecosystem: "pip"
directories: ["/", "/tools/cot_dt2c", "/tools/tlc"]
schedule:
interval: "daily"
+ groups:
+ dev-deps:
+ patterns: ["*"]
+ update-types: ["major", "minor", "patch"]
- target-branch: "lts-v2.10"
package-ecosystem: "pip"
directories: ["/"]
schedule:
interval: "daily"
+ groups:
+ dev-deps:
+ patterns: ["*"]
+ update-types: ["patch"]
- target-branch: "lts-v2.8"
package-ecosystem: "pip"
directories: ["/"]
schedule:
interval: "daily"
+ groups:
+ dev-deps:
+ patterns: ["*"]
+ update-types: ["patch"]
diff --git a/Makefile b/Makefile
index 58c98a1..fae34c5 100644
--- a/Makefile
+++ b/Makefile
@@ -115,6 +115,9 @@
SP_MK_GEN ?= ${SPTOOLPATH}/sp_mk_generator.py
SP_DTS_LIST_FRAGMENT ?= ${BUILD_PLAT}/sp_list_fragment.dts
+# Variables for use with sptool
+TLCTOOL ?= poetry run tlc
+
# Variables for use with ROMLIB
ROMLIBPATH ?= lib/romlib
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index a26910c..a85b355 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -213,6 +213,7 @@
sp_min_plat_runtime_setup();
console_flush();
+ console_switch_state(CONSOLE_FLAG_RUNTIME);
}
/******************************************************************************
diff --git a/changelog.yaml b/changelog.yaml
index 90f7425..422b9da 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2021-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -1418,6 +1418,9 @@
scope: tools
subsections:
+ - title: Dependabot
+ scope: dependabot
+
- title: STM32 Image
scope: stm32image
@@ -1477,6 +1480,9 @@
- title: Compiler runtime libraries
scope: compiler-rt
+ - title: Development dependencies
+ scope: dev-deps
+
- title: libfdt
scope: libfdt
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 17b2954..4637908 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -578,6 +578,12 @@
CPU, this affects all configurations. This needs to be enabled for revisions
r0p0 and r0p1. It has been fixed in r0p2.
+For Neoverse V3, the following errata build flags are defined :
+
+- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3
+ CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and
+ is still open.
+
For Cortex-A710, the following errata build flags are defined :
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
@@ -653,6 +659,10 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
CPU and is still open.
+- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the
+ CPU and is still open.
+
For Neoverse N2, the following errata build flags are defined :
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
@@ -724,6 +734,15 @@
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
in r0p3.
+- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is
+ still open.
+
+For Neoverse N3, the following errata build flags are defined :
+
+- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3
+ CPU. This needs to be enabled for revisions r0p0 and is still open.
+
For Cortex-X2, the following errata build flags are defined :
- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
@@ -778,6 +797,10 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
CPU and it is still open.
+- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
+ CPU and it is still open.
+
For Cortex-X3, the following errata build flags are defined :
- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3
@@ -825,6 +848,10 @@
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU. It is fixed in r1p2.
+- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3
+ CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2
+ of the CPU and it is still open.
+
For Cortex-X4, the following errata build flags are defined :
- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4
@@ -858,6 +885,15 @@
- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4
+ CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3.
+ It is still open.
+
+For Cortex-X925, the following errata build flags are defined :
+
+- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925
+ CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open.
+
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
@@ -956,6 +992,10 @@
Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0
and r1p1. It is fixed in r1p2.
+- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to
+ Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0,
+ r1p2, r1p3. It is still open.
+
For Cortex-A720, the following errata build flags are defined :
- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to
@@ -974,6 +1014,22 @@
Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
It is fixed in r0p2.
+- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to
+ Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1
+ and r0p2. It is still open.
+
+For Cortex-A720_AE, the following errata build flags are defined :
+
+- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround
+ to Cortex-A715_AE CPU. This needs to be enabled for revisions r0p0.
+ It is still open.
+
+For Cortex-A725, the following errata build flags are defined :
+
+- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to
+ Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1.
+ It is fixed in r0p2.
+
DSU Errata Workarounds
----------------------
diff --git a/docs/design_documents/rse.rst b/docs/design_documents/rse.rst
index dd110ca..21e5fd4 100644
--- a/docs/design_documents/rse.rst
+++ b/docs/design_documents/rse.rst
@@ -781,6 +781,21 @@
- ``ROTPK for secure firmware.``
- ``ROTPK for non-secure firmware.``
+Get entropy API
+^^^^^^^^^^^^^^^
+
+AP/RSE interface for reading the entropy is as follows.
+
+Defined here:
+
+- ``include/lib/psa/rse_platform_api.h``
+
+.. code-block:: c
+
+ psa_status_t rse_platform_get_entropy(uint8_t *data, size_t data_size)
+
+Through this service, we can read an entropy generated from RSE.
+
References
----------
diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index 691a3b8..fc0b3b6 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -46,21 +46,6 @@
serial0 = &os_uart;
};
- chosen {
- /*
- * Add some dummy entropy for Linux so it
- * doesn't delay the boot waiting for it.
- */
- rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
- 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
- 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
- 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
- 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
- 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
- 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
- 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -615,9 +600,9 @@
* L3 cache in the DSU is the Memory System Component (MSC)
* The MPAM registers are accessed through utility bus in the DSU
*/
- msc0 {
+ dsu-msc0 {
compatible = "arm,mpam-msc";
- reg = <MPAM_ADDR 0x0 0x2000>;
+ reg = <DSU_MPAM_ADDR 0x0 0x2000>;
};
ete0 {
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
index 003efdc..8aa77ce 100644
--- a/fdts/tc2.dts
+++ b/fdts/tc2.dts
@@ -35,7 +35,7 @@
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
-#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
+#define DSU_MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi
index 049a4c6..ef8713a 100644
--- a/fdts/tc3-4-base.dtsi
+++ b/fdts/tc3-4-base.dtsi
@@ -17,7 +17,7 @@
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined"
-#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
+#define DSU_MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
diff --git a/fdts/tc4.dts b/fdts/tc4.dts
index 98cfea1..df9a7e9 100644
--- a/fdts/tc4.dts
+++ b/fdts/tc4.dts
@@ -13,9 +13,9 @@
#define MHU_TX_ADDR 46240000 /* hex */
#define MHU_RX_ADDR 46250000 /* hex */
-#define LIT_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
-#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
-#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
+#define LIT_CPU_PMU_COMPATIBLE "arm,nevis-pmu"
+#define MID_CPU_PMU_COMPATIBLE "arm,gelas-pmu"
+#define BIG_CPU_PMU_COMPATIBLE "arm,travis-pmu"
#define RSE_MHU_TX_ADDR 49020000 /* hex */
#define RSE_MHU_RX_ADDR 49030000 /* hex */
@@ -104,4 +104,46 @@
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>;
};
+
+#if defined(TARGET_FLAVOUR_FPGA)
+ slc-msc@0 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(0) 0x0 0x4000>;
+ };
+
+ slc-msc@1 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(1) 0x0 0x4000>;
+ };
+
+ slc-msc@2 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(2) 0x0 0x4000>;
+ };
+
+ slc-msc@3 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(3) 0x0 0x4000>;
+ };
+
+ slc-msc@4 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(4) 0x0 0x4000>;
+ };
+
+ slc-msc@5 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(5) 0x0 0x4000>;
+ };
+
+ slc-msc@6 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(6) 0x0 0x4000>;
+ };
+
+ slc-msc@7 {
+ compatible = "arm,mpam-msc";
+ reg = <0x0 MCN_MPAM_NS_BASE_ADDR(7) 0x0 0x4000>;
+ };
+#endif /* TARGET_FLAVOUR_FPGA */
};
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
index 9df8d47..650193c 100644
--- a/include/lib/cpus/aarch64/cortex_a710.h
+++ b/include/lib/cpus/aarch64/cortex_a710.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,4 +67,8 @@
#define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2
#define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_a710_3701772(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* CORTEX_A710_H */
diff --git a/include/lib/cpus/aarch64/cortex_a715.h b/include/lib/cpus/aarch64/cortex_a715.h
index c7f50db..e9bd886 100644
--- a/include/lib/cpus/aarch64/cortex_a715.h
+++ b/include/lib/cpus/aarch64/cortex_a715.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -38,4 +38,8 @@
#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_a715_3699560(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* CORTEX_A715_H */
diff --git a/include/lib/cpus/aarch64/cortex_a720.h b/include/lib/cpus/aarch64/cortex_a720.h
index 129c1ee..670438f 100644
--- a/include/lib/cpus/aarch64/cortex_a720.h
+++ b/include/lib/cpus/aarch64/cortex_a720.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -38,4 +38,8 @@
#define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_a720_3699561(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* CORTEX_A720_H */
diff --git a/include/lib/cpus/aarch64/cortex_a720_ae.h b/include/lib/cpus/aarch64/cortex_a720_ae.h
index c88b1f9..cc9c3b0 100644
--- a/include/lib/cpus/aarch64/cortex_a720_ae.h
+++ b/include/lib/cpus/aarch64/cortex_a720_ae.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,4 +20,8 @@
#define CORTEX_A720_AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_a720_ae_3699562(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* CORTEX_A720_AE_H */
diff --git a/include/lib/cpus/aarch64/cortex_a725.h b/include/lib/cpus/aarch64/cortex_a725.h
index cb1c099..20488dd 100644
--- a/include/lib/cpus/aarch64/cortex_a725.h
+++ b/include/lib/cpus/aarch64/cortex_a725.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,4 +21,8 @@
#define CORTEX_A725_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A725_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_a725_3699564(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* CORTEX_A725_H */
diff --git a/include/lib/cpus/aarch64/cortex_gelas.h b/include/lib/cpus/aarch64/cortex_gelas.h
index 90bb78f..486b868 100644
--- a/include/lib/cpus/aarch64/cortex_gelas.h
+++ b/include/lib/cpus/aarch64/cortex_gelas.h
@@ -15,6 +15,7 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5
+#define CPUECTLR2_EL1_EXTLLC_BIT 10
/*******************************************************************************
* CPU Power Control register specific definitions
diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h
index 0f97b1e..9ec5177 100644
--- a/include/lib/cpus/aarch64/cortex_x2.h
+++ b/include/lib/cpus/aarch64/cortex_x2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -64,4 +64,8 @@
#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2
#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_x2_3701772(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* CORTEX_X2_H */
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index c5f820c..8834db1 100644
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -63,4 +63,8 @@
#define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2
#define CORTEX_X3_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_x3_3701769(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* CORTEX_X3_H */
diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h
index 116f9a0..8ef830a 100644
--- a/include/lib/cpus/aarch64/cortex_x4.h
+++ b/include/lib/cpus/aarch64/cortex_x4.h
@@ -50,6 +50,8 @@
return 0;
}
#endif /* ERRATA_X4_2726228 */
+
+long check_erratum_cortex_x4_3701758(long cpu_rev);
#endif /* __ASSEMBLER__ */
#endif /* CORTEX_X4_H */
diff --git a/include/lib/cpus/aarch64/cortex_x925.h b/include/lib/cpus/aarch64/cortex_x925.h
index ecbbb59..170afbf 100644
--- a/include/lib/cpus/aarch64/cortex_x925.h
+++ b/include/lib/cpus/aarch64/cortex_x925.h
@@ -26,4 +26,8 @@
******************************************************************************/
#define CORTEX_X925_CPUACTLR6_EL1 S3_0_C15_C8_1
+#ifndef __ASSEMBLER__
+long check_erratum_cortex_x925_3701747(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* CORTEX_X925_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
index b379fab..f5837d4 100644
--- a/include/lib/cpus/aarch64/neoverse_n2.h
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,4 +69,8 @@
#define CPUECTLR2_EL1_TXREQ_LSB U(0)
#define CPUECTLR2_EL1_TXREQ_WIDTH U(3)
+#ifndef __ASSEMBLER__
+long check_erratum_neoverse_n2_3701773(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* NEOVERSE_N2_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n3.h b/include/lib/cpus/aarch64/neoverse_n3.h
index 9196330..24988aa 100644
--- a/include/lib/cpus/aarch64/neoverse_n3.h
+++ b/include/lib/cpus/aarch64/neoverse_n3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,4 +21,8 @@
#define NEOVERSE_N3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+#ifndef __ASSEMBLER__
+long check_erratum_neoverse_n3_3699563(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* NEOVERSE_N3_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v3.h b/include/lib/cpus/aarch64/neoverse_v3.h
index a31bdd3..5a828c0 100644
--- a/include/lib/cpus/aarch64/neoverse_v3.h
+++ b/include/lib/cpus/aarch64/neoverse_v3.h
@@ -30,4 +30,8 @@
******************************************************************************/
#define NEOVERSE_V3_CPUACTLR6_EL1 S3_0_C15_C8_1
+#ifndef __ASSEMBLER__
+long check_erratum_neoverse_v3_3701767(long cpu_rev);
+#endif /* __ASSEMBLER__ */
+
#endif /* NEOVERSE_V3_H */
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index a2f2fc6..b9166f7 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -4,12 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef ERRATA_REPORT_H
-#define ERRATA_REPORT_H
+#ifndef ERRATA_H
+#define ERRATA_H
#include <lib/cpus/cpu_ops.h>
-
#define ERRATUM_WA_FUNC_SIZE CPU_WORD_SIZE
#define ERRATUM_CHECK_FUNC_SIZE CPU_WORD_SIZE
#define ERRATUM_ID_SIZE 4
@@ -35,21 +34,6 @@
void print_errata_status(void);
-#if ERRATA_A75_764081
-bool errata_a75_764081_applies(void);
-#else
-static inline bool errata_a75_764081_applies(void)
-{
- return false;
-}
-#endif
-
-#if ERRATA_A520_2938996 || ERRATA_X4_2726228
-unsigned int check_if_affected_core(void);
-#endif
-
-int check_wa_cve_2024_7881(void);
-
/*
* NOTE that this structure will be different on AArch32 and AArch64. The
* uintptr_t will reflect the change and the alignment will be correct in both.
@@ -68,6 +52,26 @@
CASSERT(sizeof(struct erratum_entry) == ERRATUM_ENTRY_SIZE,
assert_erratum_entry_asm_c_different_sizes);
+
+/*
+ * Runtime errata helpers.
+ */
+#if ERRATA_A75_764081
+bool errata_a75_764081_applies(void);
+#else
+static inline bool errata_a75_764081_applies(void)
+{
+ return false;
+}
+#endif
+
+#if ERRATA_A520_2938996 || ERRATA_X4_2726228
+unsigned int check_if_affected_core(void);
+#endif
+
+int check_wa_cve_2024_7881(void);
+bool errata_ich_vmcr_el2_applies(void);
+
#else
/*
@@ -96,4 +100,4 @@
/* Macro to get CPU revision code for checking errata version compatibility. */
#define CPU_REV(r, p) ((r << 4) | p)
-#endif /* ERRATA_REPORT_H */
+#endif /* ERRATA_H */
diff --git a/include/lib/psa/rse_crypto_defs.h b/include/lib/psa/rse_crypto_defs.h
index b94664f..ea1342f 100644
--- a/include/lib/psa/rse_crypto_defs.h
+++ b/include/lib/psa/rse_crypto_defs.h
@@ -11,6 +11,9 @@
/* Declares types that encode errors, algorithms, key types, policies, etc. */
#include "psa/crypto_types.h"
+/* Value identifying random number generating API */
+#define RSE_CRYPTO_GENERATE_RANDOM_SID (uint16_t)(0x100)
+
/*
* Value identifying export public key function API, used to dispatch the request
* to the corresponding API implementation in the Crypto service backend.
diff --git a/include/lib/psa/rse_platform_api.h b/include/lib/psa/rse_platform_api.h
index 535001b..fcfeb50 100644
--- a/include/lib/psa/rse_platform_api.h
+++ b/include/lib/psa/rse_platform_api.h
@@ -11,7 +11,9 @@
#include <stdint.h>
#include "psa/error.h"
+#if CRYPTO_SUPPORT
#include <rse_crypto_defs.h>
+#endif
#define RSE_PLATFORM_API_ID_NV_READ (1010)
#define RSE_PLATFORM_API_ID_NV_INCREMENT (1011)
@@ -42,6 +44,7 @@
rse_platform_nv_counter_read(uint32_t counter_id,
uint32_t size, uint8_t *val);
+#if CRYPTO_SUPPORT
/*
* Reads the public key or the public part of a key pair in binary format.
*
@@ -57,4 +60,17 @@
rse_platform_key_read(enum rse_key_id_builtin_t key, uint8_t *data,
size_t data_size, size_t *data_length);
+/*
+ * Gets the entropy.
+ *
+ * data Buffer where the entropy data is to be written.
+ * data_size Size of the data buffer in bytes.
+ *
+ * PSA_SUCCESS if the entropy is generated successfully. Otherwise,
+ * it returns a PSA_ERROR.
+ */
+psa_status_t
+rse_platform_get_entropy(uint8_t *data, size_t data_size);
+#endif
+
#endif /* RSE_PLATFORM_API_H */
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index dce9c73..71ed6db 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,8 @@
#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_a710_3701772
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710
#endif /* WORKAROUND_CVE_2022_23960 */
@@ -218,6 +220,10 @@
check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
+
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index 8c9988d..fbc73ed 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,8 @@
#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_a715_3699560
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
#endif /* WORKAROUND_CVE_2022_23960 */
@@ -127,6 +129,10 @@
check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+add_erratum_entry cortex_a715, ERRATUM(3699560), ERRATA_A715_3699560, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_a715, ERRATUM(3699560), CPU_REV(1, 3)
+
cpu_reset_func_start cortex_a715
/* Disable speculative loads */
msr SSBS, xzr
diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index 9befb36..ab2c12f 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,8 @@
#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_a720_3699561
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */
@@ -72,6 +74,10 @@
check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2)
+
cpu_reset_func_start cortex_a720
/* Disable speculative loads */
msr SSBS, xzr
diff --git a/lib/cpus/aarch64/cortex_a720_ae.S b/lib/cpus/aarch64/cortex_a720_ae.S
index 42d49c3..57a5030 100644
--- a/lib/cpus/aarch64/cortex_a720_ae.S
+++ b/lib/cpus/aarch64/cortex_a720_ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,12 @@
#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_a720_ae_3699562
+
+add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0)
+
cpu_reset_func_start cortex_a720_ae
/* Disable speculative loads */
msr SSBS, xzr
diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S
index af98d14..c4d6034 100644
--- a/lib/cpus/aarch64/cortex_a725.S
+++ b/lib/cpus/aarch64/cortex_a725.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,12 @@
#error "Cortex-A725 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_a725_3699564
+
+add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1)
+
cpu_reset_func_start cortex_a725
/* Disable speculative loads */
msr SSBS, xzr
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index 2fc357a..c18ce3c 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,12 @@
#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_x2_3701772
+
+add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
#endif /* WORKAROUND_CVE_2022_23960 */
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 4a0212e..24dbf9d 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -22,6 +22,12 @@
#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_x3_3701769
+
+add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2)
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
#endif /* WORKAROUND_CVE_2022_23960 */
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 5765828..fded73f 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -23,6 +23,7 @@
#endif
.global check_erratum_cortex_x4_2726228
+.global check_erratum_cortex_x4_3701758
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
@@ -119,6 +120,10 @@
check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
+add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
+
cpu_reset_func_start cortex_x4
/* Disable speculative loads */
msr SSBS, xzr
diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 5b6632a..e2e70dd 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S
@@ -21,6 +21,12 @@
#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_x925_3701747
+
+add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)
+
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46)
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 69aa8ab..3df3839 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,6 +20,12 @@
#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_neoverse_n2_3701773
+
+add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773, NO_APPLY_AT_RESET
+
+check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
#endif /* WORKAROUND_CVE_2022_23960 */
diff --git a/lib/cpus/aarch64/neoverse_n3.S b/lib/cpus/aarch64/neoverse_n3.S
index d96c9d4..8abcafe 100644
--- a/lib/cpus/aarch64/neoverse_n3.S
+++ b/lib/cpus/aarch64/neoverse_n3.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,12 @@
#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_neoverse_n3_3699563
+
+add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563, NO_APPLY_AT_RESET
+
+check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0)
+
cpu_reset_func_start neoverse_n3
/* Disable speculative loads */
msr SSBS, xzr
diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S
index 69b6627..7fe2d7f 100644
--- a/lib/cpus/aarch64/neoverse_v3.S
+++ b/lib/cpus/aarch64/neoverse_v3.S
@@ -22,6 +22,12 @@
#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_neoverse_v3_3701767
+
+add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767, NO_APPLY_AT_RESET
+
+check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2)
+
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
#endif /* WORKAROUND_CVE_2022_23960 */
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 1984689..fb904e2 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -564,6 +564,11 @@
# still open.
CPU_FLAG_LIST += ERRATA_V1_2779461
+# Flag to apply erratum 3701767 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 and r0p2 of
+# the Neoverse V3 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_V3_3701767
+
# Flag to apply erratum 1987031 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
CPU_FLAG_LIST += ERRATA_A710_1987031
@@ -642,6 +647,11 @@
# open.
CPU_FLAG_LIST += ERRATA_A710_2778471
+# Flag to apply erratum 3701772 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r2p0, r2p1
+# of the Cortex-A710 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_A710_3701772
+
# Flag to apply erratum 2002655 workaround during reset. This erratum applies
# to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2002655
@@ -723,6 +733,16 @@
# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
CPU_FLAG_LIST += ERRATA_N2_2779511
+# Flag to apply erratum 3701773 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1, r0p2 and r0p3
+# of the Neoverse N2 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_N2_3701773
+
+# Flag to apply erratum 3699563 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revision r0p0 of the Neoverse N3
+# cpu and is still open.
+CPU_FLAG_LIST += ERRATA_N3_3699563
+
# Flag to apply erratum 2002765 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_2002765
@@ -781,6 +801,11 @@
# to revisions r0p0, r1p0, r2p0, r2p1 of the Cortex-X2 cpu and it is still open.
CPU_FLAG_LIST += ERRATA_X2_2778471
+# Flag to apply erratum 3701772 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r2p0 and r2p1
+# of the Cortex-X2 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_X2_3701772
+
# Flag to apply erratum 2070301 workaround on reset. This erratum applies
# to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu and is
# still open.
@@ -822,6 +847,11 @@
# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2743088
+# Flag to apply erratum 3701769 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r1p1 and r1p2
+# of the Cortex-X3 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_X3_3701769
+
# Flag to apply erratum 2779509 workaround on reset. This erratum applies
# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2779509
@@ -859,6 +889,16 @@
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_3076789
+# Flag to apply erratum 3701758 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1, r0p2 and r0p3
+# of the Cortex-X4 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_X4_3701758
+
+# Flag to apply erratum 3701747 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 of the
+# Cortex-X925 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_X925_3701747
+
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240
@@ -984,6 +1024,11 @@
# only to revision r0p0, r1p0 and r1p1. It is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_A715_2728106
+# Flag to apply erratum 3699560 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r1p0, r1p2, r1p3
+# of the Cortex-A715 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_A715_3699560
+
# Flag to apply erratum 2792132 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_A720_2792132
@@ -1000,12 +1045,27 @@
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_A720_2940794
+# Flag to apply erratum 3699561 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1, r0p2 of
+# the Cortex-A720 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_A720_3699561
+
+# Flag to apply erratum 3699562 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revision r0p0 the Cortex-A720-AE
+# cpu and is still open.
+CPU_FLAG_LIST += ERRATA_A720_AE_3699562
+
+# Flag to apply erratum 3699564 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 of
+# the Cortex-A725 cpu and is fixed in r0p2
+CPU_FLAG_LIST += ERRATA_A725_3699564
+
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_798953
# Flag to apply DSU erratum 936184. This erratum applies to DSUs containing
-# the ACP interface and revision < r2p0. Applying the workaround results in
+# the ACP interface and revision < r0p0. Applying the workaround results in
# higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_936184
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index a4515a9..a391430 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,11 +8,22 @@
#include <arch.h>
#include <arch_helpers.h>
+#include <cortex_a75.h>
#include <cortex_a520.h>
+#include <cortex_a710.h>
+#include <cortex_a715.h>
+#include <cortex_a720.h>
+#include <cortex_a720_ae.h>
+#include <cortex_a725.h>
+#include <cortex_x2.h>
+#include <cortex_x3.h>
#include <cortex_x4.h>
-#include <cortex_a75.h>
+#include <cortex_x925.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
+#include <neoverse_n2.h>
+#include <neoverse_n3.h>
+#include <neoverse_v3.h>
#if ERRATA_A520_2938996 || ERRATA_X4_2726228
unsigned int check_if_affected_core(void)
@@ -40,3 +51,97 @@
return false;
}
#endif /* ERRATA_A75_764081 */
+
+bool errata_ich_vmcr_el2_applies(void)
+{
+ switch (EXTRACT_PARTNUM(read_midr())) {
+#if ERRATA_A710_3701772
+ case EXTRACT_PARTNUM(CORTEX_A710_MIDR):
+ if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_A710_3701772 */
+
+#if ERRATA_A715_3699560
+ case EXTRACT_PARTNUM(CORTEX_A715_MIDR):
+ if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_A715_3699560 */
+
+#if ERRATA_A720_3699561
+ case EXTRACT_PARTNUM(CORTEX_A720_MIDR):
+ if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;;
+ break;
+#endif /* ERRATA_A720_3699561 */
+
+#if ERRATA_A720_AE_3699562
+ case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR):
+ if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_A720_AE_3699562 */
+
+#if ERRATA_A725_3699564
+ case EXTRACT_PARTNUM(CORTEX_A725_MIDR):
+ if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_A725_3699564 */
+
+#if ERRATA_X2_3701772
+ case EXTRACT_PARTNUM(CORTEX_X2_MIDR):
+ if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_X2_3701772 */
+
+#if ERRATA_X3_3701769
+ case EXTRACT_PARTNUM(CORTEX_X3_MIDR):
+ if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_X3_3701769 */
+
+#if ERRATA_X4_3701758
+ case EXTRACT_PARTNUM(CORTEX_X4_MIDR):
+ if (check_erratum_cortex_x4_3701758(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_X4_3701758 */
+
+#if ERRATA_X925_3701747
+ case EXTRACT_PARTNUM(CORTEX_X925_MIDR):
+ if (check_erratum_cortex_x925_3701747(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_X925_3701747 */
+
+#if ERRATA_N2_3701773
+ case EXTRACT_PARTNUM(NEOVERSE_N2_MIDR):
+ if (check_erratum_neoverse_n2_3701773(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_N2_3701773 */
+
+#if ERRATA_N3_3699563
+ case EXTRACT_PARTNUM(NEOVERSE_N3_MIDR):
+ if (check_erratum_neoverse_n3_3699563(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_N3_3699563 */
+
+#if ERRATA_V3_3701767
+ case EXTRACT_PARTNUM(NEOVERSE_V3_MIDR):
+ if (check_erratum_neoverse_v3_3701767(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_V3_3701767 */
+
+ default:
+ break;
+ }
+
+ return false;
+}
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 473190c..f396752 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -1291,12 +1291,13 @@
* SCR_EL3.NS = 1 before accessing this register.
* ---------------------------------------------------------------------------
*/
-static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx)
+static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state)
{
+ u_register_t scr_el3 = read_scr_el3();
+
#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2());
#else
- u_register_t scr_el3 = read_scr_el3();
write_scr_el3(scr_el3 | SCR_NS_BIT);
isb();
@@ -1306,15 +1307,31 @@
isb();
#endif
write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2());
+
+ if (errata_ich_vmcr_el2_applies()) {
+ if (security_state == SECURE) {
+ write_scr_el3(scr_el3 & ~SCR_NS_BIT);
+ } else {
+ write_scr_el3(scr_el3 | SCR_NS_BIT);
+ }
+ isb();
+ }
+
write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2());
+
+ if (errata_ich_vmcr_el2_applies()) {
+ write_scr_el3(scr_el3);
+ isb();
+ }
}
-static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx)
+static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state)
{
+ u_register_t scr_el3 = read_scr_el3();
+
#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
#else
- u_register_t scr_el3 = read_scr_el3();
write_scr_el3(scr_el3 | SCR_NS_BIT);
isb();
@@ -1324,7 +1341,22 @@
isb();
#endif
write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2));
+
+ if (errata_ich_vmcr_el2_applies()) {
+ if (security_state == SECURE) {
+ write_scr_el3(scr_el3 & ~SCR_NS_BIT);
+ } else {
+ write_scr_el3(scr_el3 | SCR_NS_BIT);
+ }
+ isb();
+ }
+
write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2));
+
+ if (errata_ich_vmcr_el2_applies()) {
+ write_scr_el3(scr_el3);
+ isb();
+ }
}
/* -----------------------------------------------------
@@ -1416,7 +1448,7 @@
el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
el2_sysregs_context_save_common(el2_sysregs_ctx);
- el2_sysregs_context_save_gic(el2_sysregs_ctx);
+ el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state);
if (is_feat_mte2_supported()) {
write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2());
@@ -1507,7 +1539,7 @@
el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
el2_sysregs_context_restore_common(el2_sysregs_ctx);
- el2_sysregs_context_restore_gic(el2_sysregs_ctx);
+ el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state);
if (is_feat_mte2_supported()) {
write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2));
diff --git a/lib/psa/rse_platform.c b/lib/psa/rse_platform.c
index 7fc2382..ffa2f48 100644
--- a/lib/psa/rse_platform.c
+++ b/lib/psa/rse_platform.c
@@ -7,7 +7,9 @@
#include <psa/client.h>
#include <psa_manifest/sid.h>
+#if CRYPTO_SUPPORT
#include <rse_crypto_defs.h>
+#endif
#include <rse_platform_api.h>
psa_status_t
@@ -41,6 +43,7 @@
in_vec, 1, out_vec, 1);
}
+#if CRYPTO_SUPPORT
psa_status_t
rse_platform_key_read(enum rse_key_id_builtin_t key, uint8_t *data,
size_t data_size, size_t *data_length)
@@ -67,3 +70,27 @@
return status;
}
+
+psa_status_t
+rse_platform_get_entropy(uint8_t *data, size_t data_size)
+{
+ psa_status_t status;
+
+ struct rse_crypto_pack_iovec iov = {
+ .function_id = RSE_CRYPTO_GENERATE_RANDOM_SID,
+ };
+
+ psa_invec in_vec[] = {
+ {.base = &iov, .len = sizeof(struct rse_crypto_pack_iovec)},
+ };
+ psa_outvec out_vec[] = {
+ {.base = data, .len = data_size}
+ };
+
+ status = psa_call(RSE_CRYPTO_HANDLE, PSA_IPC_CALL,
+ in_vec, IOVEC_LEN(in_vec),
+ out_vec, IOVEC_LEN(out_vec));
+
+ return status;
+}
+#endif
diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk
index 12ffb5a..8211c26 100644
--- a/plat/arm/board/morello/platform.mk
+++ b/plat/arm/board/morello/platform.mk
@@ -1,12 +1,12 @@
#
-# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Making sure the Morello platform type is specified
ifeq ($(filter ${TARGET_PLATFORM}, fvp soc),)
- $(error TARGET_PLATFORM must be fvp or soc)
+ $(error TARGET_PLATFORM must be fvp or soc)
endif
MORELLO_BASE := plat/arm/board/morello
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/fdts/rdn2_stmm_sel0_manifest.dts b/plat/arm/board/neoverse_rd/platform/rdn2/fdts/rdn2_stmm_sel0_manifest.dts
index dbdc7e5..7ca55b0 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/fdts/rdn2_stmm_sel0_manifest.dts
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/fdts/rdn2_stmm_sel0_manifest.dts
@@ -28,7 +28,7 @@
description = "RDN2 StMM";
ffa-version = <0x00010001>; /* 31:16 - Major, 15:0 - Minor */
- uuid = <0x378daedc 0xf06b4446 0x831440ab 0x933c87a3>;
+ uuid = <0xdcae8d37 0x46446bf0 0xab401483 0xa3873c93>;
id = <0x8001>;
execution-ctx-count = <1>;
exception-level = <MODE_SEL0>; /* S-EL0 */
diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S
index 1fde9e9..cc2f760 100644
--- a/plat/arm/board/tc/include/tc_helpers.S
+++ b/plat/arm/board/tc/include/tc_helpers.S
@@ -9,6 +9,8 @@
#include <platform_def.h>
#include <cpu_macros.S>
+#include <cortex_gelas.h>
+
#define TC_HANDLER(rev) plat_reset_handler_tc##rev
#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev)
@@ -57,8 +59,11 @@
mov_imm x0, (MCN_CONFIG_ADDR(0))
ldr w1, [x0]
ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
- sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, \
- CPUECTLR_EL1_EXTLLC_BIT, 1
+ jump_if_cpu_midr CORTEX_GELAS_MIDR, GELAS
+ sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, CPUECTLR_EL1_EXTLLC_BIT, 1
+ ret
+GELAS:
+ sysreg_bitfield_insert_from_gpr CORTEX_GELAS_IMP_CPUECTLR_EL1, x1, CPUECTLR2_EL1_EXTLLC_BIT, 1
#endif
ret
endfunc mark_extllc_presence
@@ -83,6 +88,7 @@
func TC_HANDLER(4)
mov x9, lr
+ bl mark_extllc_presence
bl enable_dsu_pmu_el1_access
mov lr, x9
ret
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index b2b3253..21d7122 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -40,6 +40,12 @@
ENABLE_SPE_FOR_NS := 3
ENABLE_FEAT_TCR2 := 3
+ifneq ($(filter ${TARGET_PLATFORM}, 3),)
+ENABLE_FEAT_RNG_TRAP := 0
+else
+ENABLE_FEAT_RNG_TRAP := 1
+endif
+
CTX_INCLUDE_AARCH32_REGS := 0
ifeq (${SPD},spmd)
@@ -47,6 +53,8 @@
CTX_INCLUDE_PAUTH_REGS := 1
endif
+TRNG_SUPPORT := 1
+
# TC RESOLUTION - LIST OF VALID OPTIONS (this impacts only FVP)
TC_RESOLUTION_OPTIONS := 640x480p60 \
1920x1080p60
@@ -240,7 +248,8 @@
BL1_SOURCES += ${RSE_COMMS_SOURCES}
BL2_SOURCES += ${RSE_COMMS_SOURCES}
-BL31_SOURCES += ${RSE_COMMS_SOURCES}
+BL31_SOURCES += ${RSE_COMMS_SOURCES} \
+ lib/psa/rse_platform.c
# Include Measured Boot makefile before any Crypto library makefile.
# Crypto library makefile may need default definitions of Measured Boot build
@@ -285,8 +294,10 @@
endif
endif
-ifeq (${TRNG_SUPPORT},1)
- BL31_SOURCES += plat/arm/board/tc/tc_trng.c
+BL31_SOURCES += plat/arm/board/tc/tc_trng.c
+
+ifneq (${ENABLE_FEAT_RNG_TRAP},0)
+ BL31_SOURCES += plat/arm/board/tc/tc_rng_trap.c
endif
ifneq (${PLATFORM_TEST},)
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index bc8f5ec..4e346ab 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -114,6 +114,8 @@
void bl31_platform_setup(void)
{
+ psa_status_t status;
+
tc_bl31_common_platform_setup();
#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4)
enable_ns_mcn_pmu();
@@ -122,6 +124,12 @@
set_mcn_slc_alloc_mode();
plat_arm_ni_setup(NCI_BASE_ADDR);
#endif
+
+ /* Initialise RSE communication channel */
+ status = rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE);
+ if (status != PSA_SUCCESS) {
+ ERROR("Failed to initialize RSE communication channel - psa_status = %d\n", status);
+ }
}
scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused)
@@ -194,18 +202,10 @@
#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
void tc_bl31_plat_runtime_setup(void)
{
- psa_status_t status;
-
/* Start secure watchdog timer. */
plat_arm_secure_wdt_start();
arm_bl31_plat_runtime_setup();
-
- /* Initialise RSE communication channel */
- status = rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE);
- if (status != PSA_SUCCESS) {
- ERROR("Failed to initialize RSE communication channel - psa_status = %d\n", status);
- }
}
void bl31_plat_runtime_setup(void)
diff --git a/plat/arm/board/tc/tc_rng_trap.c b/plat/arm/board/tc/tc_rng_trap.c
new file mode 100644
index 0000000..b055fe4
--- /dev/null
+++ b/plat/arm/board/tc/tc_rng_trap.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <bl31/sync_handle.h>
+#include <context.h>
+#include <plat/common/plat_trng.h>
+
+#define XZR_REG_NUM 31
+
+
+int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx)
+{
+ uint64_t entropy;
+
+ /* extract the target register number from the exception syndrome */
+ unsigned int rt = get_sysreg_iss_rt(esr_el3);
+
+ /* ignore XZR accesses and writes to the register */
+ assert(rt != XZR_REG_NUM && !is_sysreg_iss_write(esr_el3));
+
+ if (!plat_get_entropy(&entropy)) {
+ ERROR("Failed to get entropy\n");
+ panic();
+ }
+
+ /* Emulate RNDR and RNDRRS */
+ gp_regs_t *gpregs = get_gpregs_ctx(ctx);
+
+ write_ctx_reg(gpregs, rt, entropy);
+
+ /*
+ * We successfully handled the trap, continue with the next
+ * instruction.
+ */
+ return TRAP_RET_CONTINUE;
+}
diff --git a/plat/arm/board/tc/tc_trng.c b/plat/arm/board/tc/tc_trng.c
index e5ec48a..793a90f 100644
--- a/plat/arm/board/tc/tc_trng.c
+++ b/plat/arm/board/tc/tc_trng.c
@@ -11,6 +11,7 @@
#include <string.h>
#include <lib/mmio.h>
+#include <lib/psa/rse_platform_api.h>
#include <lib/smccc.h>
#include <lib/utils_def.h>
#include <plat/common/platform.h>
@@ -24,20 +25,33 @@
);
uuid_t plat_trng_uuid;
-/* Dummy implementation */
bool plat_get_entropy(uint64_t *out)
{
+#if CRYPTO_SUPPORT
+ psa_status_t status;
+
+ status = rse_platform_get_entropy((uint8_t *)out, sizeof(*out));
+ if (status != PSA_SUCCESS) {
+ printf("Failed for entropy read, psa_status=%d\n", status);
+ return false;
+ }
+#else
+ /* Dummy value */
*out = 0xABBAEDDAACDCDEAD;
+#endif
return true;
}
void plat_entropy_setup(void)
{
- uint64_t dummy;
+ uint64_t entropy;
plat_trng_uuid = _plat_trng_uuid;
/* Initialise the entropy source and trigger RNG generation */
- plat_get_entropy(&dummy);
+ if (!plat_get_entropy(&entropy)) {
+ ERROR("Failed to setup entropy\n");
+ panic();
+ }
}
diff --git a/plat/common/aarch32/plat_sp_min_common.c b/plat/common/aarch32/plat_sp_min_common.c
index 9493587..8e96b96 100644
--- a/plat/common/aarch32/plat_sp_min_common.c
+++ b/plat/common/aarch32/plat_sp_min_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,9 +17,4 @@
void sp_min_plat_runtime_setup(void)
{
- /*
- * Finish the use of console driver in SP_MIN so that any runtime logs
- * from SP_MIN will be suppressed.
- */
- console_switch_state(CONSOLE_FLAG_RUNTIME);
}
diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk
index 2fdef57..5050809 100644
--- a/plat/mediatek/mt8196/platform.mk
+++ b/plat/mediatek/mt8196/platform.mk
@@ -9,6 +9,19 @@
MTK_SOC := ${PLAT}
ARM_ARCH_MAJOR := 9
+ERRATA_A720_2792132 := 1
+ERRATA_A720_2844092 := 1
+ERRATA_A720_2926083 := 1
+ERRATA_A720_2940794 := 1
+
+ERRATA_X4_2726228 := 1
+ERRATA_X4_2740089 := 1
+ERRATA_X4_2763018 := 1
+ERRATA_X4_2816013 := 1
+ERRATA_X4_2897503 := 1
+ERRATA_X4_2923985 := 1
+ERRATA_X4_3076789 := 1
+
include plat/mediatek/build_helpers/mtk_build_helpers.mk
include drivers/arm/gic/v3/gicv3.mk
include lib/xlat_tables_v2/xlat_tables.mk
diff --git a/tools/sptool/sp_mk_generator.py b/tools/sptool/sp_mk_generator.py
index 9bf5cd0..f80050e 100644
--- a/tools/sptool/sp_mk_generator.py
+++ b/tools/sptool/sp_mk_generator.py
@@ -87,6 +87,19 @@
check_sp_layout_dir(args)
return os.path.join(args["sp_layout_dir"], get_file_from_layout(sp_node["image"]))
+def get_size(sp_node):
+ if not "size" in sp_node:
+ print("WARNING: default image size 0x100000")
+ return 0x100000
+
+ # Try if it was a decimal value.
+ try:
+ return int(sp_node["size"])
+ except ValueError:
+ print("WARNING: trying to parse base 16 size")
+ # Try if it is of base 16
+ return int(sp_node["size"], 16)
+
def get_sp_pkg(sp, args :dict):
check_out_dir(args)
return os.path.join(args["out_dir"], f"{sp}.pkg")
@@ -146,7 +159,6 @@
load_address_parsed = re.search("(0x[0-9a-f]+)", load_address_lines[0])
return load_address_parsed.group(0)
-
@SpSetupActions.sp_action(global_action=True)
def check_max_sps(sp_layout, _, args :dict):
''' Check validate the maximum number of SPs is respected. '''
@@ -167,31 +179,60 @@
write_to_sp_mk_gen(f"FDT_SOURCES += {manifest_path}", args)
return args
+def generate_sp_pkg(sp_node, pkg, sp_img, sp_dtb):
+ ''' Generates the rule in case SP is to be generated in an SP Pkg. '''
+ pm_offset = get_pm_offset(sp_node)
+ sptool_args = f" --pm-offset {pm_offset}" if pm_offset is not None else ""
+ image_offset = get_image_offset(sp_node)
+ sptool_args += f" --img-offset {image_offset}" if image_offset is not None else ""
+ sptool_args += f" -o {pkg}"
+ return f'''
+{pkg}: {sp_dtb} {sp_img}
+\t$(Q)echo Generating {pkg}
+\t$(Q)$(PYTHON) $(SPTOOL) -i {sp_img}:{sp_dtb} {sptool_args}
+'''
+
+def generate_tl_pkg(sp_node, pkg, sp_img, sp_dtb, hob_path = None):
+ ''' Generate make rules for a Transfer List type package. '''
+ # TE Type for the FF-A manifest.
+ TE_FFA_MANIFEST = 0x106
+ # TE Type for the SP binary.
+ TE_SP_BINARY = 0x103
+ # TE Type for the HOB List.
+ TE_HOB_LIST = 0x3
+ tlc_add_hob = f"\t$(Q)poetry run tlc add --entry {TE_HOB_LIST} {hob_path} {pkg}" if hob_path is not None else ""
+ return f'''
+{pkg}: {sp_dtb} {sp_img}
+\t$(Q)echo Generating {pkg}
+\t$(Q)$(TLCTOOL) create --size {get_size(sp_node)} --entry {TE_FFA_MANIFEST} {sp_dtb} {pkg} --align 12
+\t$(Q)$(TLCTOOL) add --entry {TE_SP_BINARY} {sp_img} {pkg}
+'''
+
@SpSetupActions.sp_action
-def gen_sptool_args(sp_layout, sp, args :dict):
+def gen_partition_pkg(sp_layout, sp, args :dict):
''' Generate Sp Pkgs rules. '''
- sp_pkg = get_sp_pkg(sp, args)
+ pkg = get_sp_pkg(sp, args)
+
sp_dtb_name = os.path.basename(get_file_from_layout(sp_layout[sp]["pm"]))[:-1] + "b"
sp_dtb = os.path.join(args["out_dir"], f"fdts/{sp_dtb_name}")
sp_img = get_sp_img_full_path(sp_layout[sp], args)
# Do not generate rule if already there.
- if is_line_in_sp_gen(f'{sp_pkg}:', args):
+ if is_line_in_sp_gen(f'{pkg}:', args):
return args
- write_to_sp_mk_gen(f"SP_PKGS += {sp_pkg}\n", args)
- sptool_args = f" -i {sp_img}:{sp_dtb}"
- pm_offset = get_pm_offset(sp_layout[sp])
- sptool_args += f" --pm-offset {pm_offset}" if pm_offset is not None else ""
- image_offset = get_image_offset(sp_layout[sp])
- sptool_args += f" --img-offset {image_offset}" if image_offset is not None else ""
- sptool_args += f" -o {sp_pkg}"
- sppkg_rule = f'''
-{sp_pkg}: {sp_dtb} {sp_img}
-\t$(Q)echo Generating {sp_pkg}
-\t$(Q)$(PYTHON) $(SPTOOL) {sptool_args}
-'''
- write_to_sp_mk_gen(sppkg_rule, args)
+ # This should include all packages of all kinds.
+ write_to_sp_mk_gen(f"SP_PKGS += {pkg}\n", args)
+ package_type = sp_layout[sp]["package"] if "package" in sp_layout[sp] else "sp_pkg"
+
+ if package_type == "sp_pkg":
+ partition_pkg_rule = generate_sp_pkg(sp_layout[sp], pkg, sp_img, sp_dtb)
+ elif package_type == "tl_pkg":
+ partition_pkg_rule = generate_tl_pkg(sp_layout[sp], pkg, sp_img, sp_dtb)
+ else:
+ raise ValueError(f"Specified invalid pkg type {package_type}")
+
+ write_to_sp_mk_gen(partition_pkg_rule, args)
return args
@SpSetupActions.sp_action(global_action=True, exec_order=1)
@@ -202,6 +243,7 @@
args["split"] = int(MAX_SP / 2)
owners = [sp_layout[sp].get("owner") for sp in sp_layout]
args["plat_max_count"] = owners.count("Plat")
+
# If it is owned by the platform owner, it is assigned to the SiP.
args["sip_max_count"] = len(sp_layout.keys()) - args["plat_max_count"]
if args["sip_max_count"] > args["split"] or args["sip_max_count"] > args["split"]: