fix(cpus): workaround for Cortex-A78C erratum 1827440
Cortex-A78C erratum 1827440 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.
The workaround is to set CPUACTLR2_EL1[2], which forces atomic store
operations to write-back memory to be performed in the L1 data cache.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I41d8ef48f70216ec66bf2b0f4f03ea8d8c261ee7
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 73c7ac5..0f1f92a 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -353,6 +353,10 @@
Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
fixed in r0p1.
+- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to
+ Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
+ fixed in r0p1.
+
- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
it is still open.
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 88bd291..fddd24f 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -45,6 +45,33 @@
endfunc check_errata_1827430
/* --------------------------------------------------
+ * Errata Workaround for A78C Erratum 1827440.
+ * This applies to revision r0p0 of the Cortex A78C
+ * processor and is fixed in r0p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78c_1827440_wa
+ mov x17, x30
+ bl check_errata_1827440
+ cbz x0, 1f
+
+ /* Force Atomic Store to WB memory be done in L1 data cache */
+ mrs x1, CORTEX_A78C_CPUACTLR2_EL1
+ orr x1, x1, #BIT(2)
+ msr CORTEX_A78C_CPUACTLR2_EL1, x1
+1:
+ ret x17
+endfunc errata_a78c_1827440_wa
+
+func check_errata_1827440
+ /* Applies to revision r0p0 only */
+ mov x1, #0x00
+ b cpu_rev_var_ls
+endfunc check_errata_1827440
+
+/* --------------------------------------------------
* Errata Workaround for Cortex A78C Erratum 2376749.
* This applies to revision r0p1 and r0p2 of the A78C
* and is currently open. It is a Cat B erratum.
@@ -257,6 +284,11 @@
bl errata_a78c_1827430_wa
#endif
+#if ERRATA_A78C_1827440
+ mov x0, x18
+ bl errata_a78c_1827440_wa
+#endif
+
#if ERRATA_A78C_2132064
mov x0, x18
bl errata_a78c_2132064_wa
@@ -332,6 +364,7 @@
* checking functions of each errata.
*/
report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430
+ report_errata ERRATA_A78C_1827440, cortex_a78c, 1827440
report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 13cf508..82a4890 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -358,6 +358,10 @@
# to revision r0p0 of the A78C cpu. It is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A78C_1827430
+# Flag to apply erratum 1827440 workaround during reset. This erratum applies
+# to revision r0p0 of the A78C cpu. It is fixed in r0p1.
+CPU_FLAG_LIST += ERRATA_A78C_1827440
+
# Flag to apply erratum 2132064 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2132064